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GET /api/patches/2230581/?format=api
{ "id": 2230581, "url": "http://patchwork.ozlabs.org/api/patches/2230581/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260429-add-ethernet-support-for-genio-520-720-v4-8-be54e17239b7@baylibre.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260429-add-ethernet-support-for-genio-520-720-v4-8-be54e17239b7@baylibre.com>", "list_archive_url": null, "date": "2026-04-29T13:59:01", "name": "[v4,8/9] arm: dts: mt8189: Add ethernet support for Genio 520/720 boards", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "35b39ba65eb401b749ef71027d1960df82b2033a", "submitter": { "id": 84831, "url": "http://patchwork.ozlabs.org/api/people/84831/?format=api", "name": "Julien Stephan", "email": "jstephan@baylibre.com" }, "delegate": { "id": 161331, "url": "http://patchwork.ozlabs.org/api/users/161331/?format=api", "username": "dlech", "first_name": "David", "last_name": "Lechner", "email": "dlechner@baylibre.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260429-add-ethernet-support-for-genio-520-720-v4-8-be54e17239b7@baylibre.com/mbox/", "series": [ { "id": 502153, "url": "http://patchwork.ozlabs.org/api/series/502153/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=502153", "date": "2026-04-29T13:58:53", "name": "Add ethernet support for genio 520/720 EVK boards", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/502153/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230581/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230581/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20251104.gappssmtp.com\n header.i=@baylibre-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=jbv4G4Io;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260429-add-ethernet-support-for-genio-520-720-v4-8-be54e17239b7@baylibre.com>", "References": "\n <20260429-add-ethernet-support-for-genio-520-720-v4-0-be54e17239b7@baylibre.com>", "In-Reply-To": "\n <20260429-add-ethernet-support-for-genio-520-720-v4-0-be54e17239b7@baylibre.com>", "To": "u-boot@lists.denx.de", "Cc": "GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Jerome Forissier <jerome.forissier@arm.com>, Tom Rini <trini@konsulko.com>,\n Christian Marangi <ansuelsmth@gmail.com>,\n Robert Marko <robert.marko@sartura.hr>, Simon Glass <sjg@chromium.org>,\n Yao Zi <me@ziyao.cc>, Quentin Schulz <quentin.schulz@cherry.de>,\n Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n \"Lucien.Jheng\" <lucienzx159@gmail.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Romain Gantois <romain.gantois@bootlin.com>,\n Siddharth Vadapalli <s-vadapalli@ti.com>,\n Yanqing Wang <ot_yanqing.wang@mediatek.com>, Beiyan Yun <root@infi.wang>,\n Ryder Lee <ryder.lee@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n David Lechner <dlechner@baylibre.com>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Kory Maincent <kory.maincent@bootlin.com>,\n Ilias Apalodimas <ilias.apalodimas@linaro.org>,\n Kuan-Wei Chiu <visitorckw@gmail.com>,\n Raymond Mao <raymond.mao@riscstar.com>, Peng Fan <peng.fan@nxp.com>,\n Stefan Roese <stefan.roese@mailbox.org>,\n Philip Molloy <philip.molloy@analog.com>,\n fanyi zhang <fanyi.zhang@mediatek.com>, Jonas Karlman <jonas@kwiboo.se>,\n Kever Yang <kever.yang@rock-chips.com>,\n Marek Vasut <marek.vasut@mailbox.org>,\n Patrick Delaunay <patrick.delaunay@foss.st.com>,\n Heiko Stuebner <heiko@sntech.de>,\n Samuel Holland <samuel.holland@sifive.com>,\n Christophe Roullier <christophe.roullier@foss.st.com>,\n Patrice Chotard <patrice.chotard@foss.st.com>,\n Chris-QJ Chen <chris-qj.chen@mediatek.com>,\n Macpaul Lin <macpaul.lin@mediatek.com>,\n Sam Protsenko <semen.protsenko@linaro.org>,\n Michael Trimarchi <michael@amarulasolutions.com>,\n Sky Huang <SkyLake.Huang@mediatek.com>,\n Leo Yu-Chi Liang <ycliang@andestech.com>,\n Tommy Shih <tommy.shih@airoha.com>,\n Kevin-KW Huang <kevin-kw.huang@airoha.com>,\n Peter Robinson <pbrobinson@gmail.com>,\n Julien Stephan <jstephan@baylibre.com>", "X-Mailer": "b4 0.14.3", "X-Mailman-Approved-At": "Wed, 29 Apr 2026 23:15:47 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add Ethernet support for MediaTek MT8189-based Genio 520 and Genio 720\ndevelopment boards.\n\nThe ethernet interface is disabled by default in the SoC dtsi and\nenabled in the board-specific configuration with proper PHY settings.\n\nThe ethernet related nodes are not part of current dt submission on the\nkernel [1] and come from downstream u-boot. When switching to\nOF_UPSTREAM we should add them back.\n\n[1]: https://lore.kernel.org/all/20251203-add-mediatek-genio-520-720-evk-v1-3-df794b2a30ae@collabora.com/\n\nSigned-off-by: Julien Stephan <jstephan@baylibre.com>\n---\n arch/arm/dts/mt8189.dtsi | 77 ++++++++++++++++++++++++++++++++\n arch/arm/dts/mt8371-genio-common.dtsi | 83 +++++++++++++++++++++++++++++++++++\n 2 files changed, 160 insertions(+)", "diff": "diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi\nindex e550745ac5d..d4ee268a298 100644\n--- a/arch/arm/dts/mt8189.dtsi\n+++ b/arch/arm/dts/mt8189.dtsi\n@@ -364,6 +364,83 @@\n \t\t\t#reset-cells = <1>;\n \t\t};\n \n+\t\teth: ethernet@1101a000 {\n+\t\t\tcompatible = \"mediatek,mt8189-gmac\", \"snps,dwmac-5.10a\";\n+\t\t\treg = <0 0x1101a000 0 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tinterrupt-names = \"macirq\";\n+\t\t\tclock-names = \"mac_main\",\n+\t\t\t\t \"ptp_ref\";\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>;\n+\t\t\tassigned-clocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>,\n+\t\t\t\t\t <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>,\n+\t\t\t\t\t <&topckgen_clk CLK_TOP_ETH_50M_RMII_SEL>;\n+\t\t\tassigned-clock-parents = <&topckgen_clk CLK_TOP_ETHPLL_D2>,\n+\t\t\t\t\t\t <&topckgen_clk CLK_TOP_ETHPLL_D8>,\n+\t\t\t\t\t\t <&topckgen_clk CLK_TOP_ETHPLL_D10>;\n+\t\t\tmediatek,pericfg = <&pericfg_ao_clk>;\n+\t\t\tsnps,axi-config = <&stmmac_axi_setup>;\n+\t\t\tsnps,mtl-rx-config = <&mtl_rx_setup>;\n+\t\t\tsnps,mtl-tx-config = <&mtl_tx_setup>;\n+\t\t\tsnps,txpbl = <16>;\n+\t\t\tsnps,rxpbl = <16>;\n+\t\t\tclk-csr = <4>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tstmmac_axi_setup: stmmac-axi-config {\n+\t\t\t\tsnps,wr-osr-lmt = <0x7>;\n+\t\t\t\tsnps,rd-osr-lmt = <0x7>;\n+\t\t\t\tsnps,blen = <0 0 0 0 16 8 4>;\n+\t\t\t};\n+\n+\t\t\tmtl_rx_setup: rx-queues-config {\n+\t\t\t\tsnps,rx-queues-to-use = <4>;\n+\t\t\t\tsnps,rx-sched-sp;\n+\t\t\t\tqueue0 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue1 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue2 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue3 {\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,map-to-dma-channel = <0x0>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmtl_tx_setup: tx-queues-config {\n+\t\t\t\tsnps,tx-queues-to-use = <4>;\n+\t\t\t\tsnps,tx-sched-wrr;\n+\t\t\t\tqueue0 {\n+\t\t\t\t\tsnps,weight = <0x10>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x0>;\n+\t\t\t\t};\n+\t\t\t\tqueue1 {\n+\t\t\t\t\tsnps,weight = <0x11>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x1>;\n+\t\t\t\t};\n+\t\t\t\tqueue2 {\n+\t\t\t\t\tsnps,weight = <0x12>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x2>;\n+\t\t\t\t};\n+\t\t\t\tqueue3 {\n+\t\t\t\t\tsnps,weight = <0x13>;\n+\t\t\t\t\tsnps,dcb-algorithm;\n+\t\t\t\t\tsnps,priority = <0x3>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n \t\ttopckgen_clk: clock-controller@10000000 {\n \t\t\tcompatible = \"mediatek,mt8189-topckgen\", \"syscon\";\n \t\t\treg = <0 0x10000000 0 0x1000>;\ndiff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi\nindex 046e9d57752..1376a4c378c 100644\n--- a/arch/arm/dts/mt8371-genio-common.dtsi\n+++ b/arch/arm/dts/mt8371-genio-common.dtsi\n@@ -281,6 +281,68 @@\n \t\t\tbias-pull-up;\n \t\t};\n \t};\n+\n+\teth_default_pins: eth-default-pins {\n+\t\ttxd-pins {\n+\t\t\tpinmux = <PINMUX_GPIO119__FUNC_GBE_TXD3>,\n+\t\t\t\t <PINMUX_GPIO120__FUNC_GBE_TXD2>,\n+\t\t\t\t <PINMUX_GPIO121__FUNC_GBE_TXD1>,\n+\t\t\t\t <PINMUX_GPIO122__FUNC_GBE_TXD0>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t};\n+\t\tcc-pins {\n+\t\t\tpinmux = <PINMUX_GPIO127__FUNC_GBE_TXC>,\n+\t\t\t\t <PINMUX_GPIO130__FUNC_GBE_TXEN>,\n+\t\t\t\t <PINMUX_GPIO129__FUNC_GBE_RXDV>,\n+\t\t\t\t <PINMUX_GPIO128__FUNC_GBE_RXC>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t};\n+\t\trxd-pins {\n+\t\t\tpinmux = <PINMUX_GPIO123__FUNC_GBE_RXD3>,\n+\t\t\t\t <PINMUX_GPIO124__FUNC_GBE_RXD2>,\n+\t\t\t\t <PINMUX_GPIO125__FUNC_GBE_RXD1>,\n+\t\t\t\t <PINMUX_GPIO126__FUNC_GBE_RXD0>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t};\n+\t\tmdio-pins {\n+\t\t\tpinmux = <PINMUX_GPIO131__FUNC_GBE_MDC>,\n+\t\t\t\t <PINMUX_GPIO132__FUNC_GBE_MDIO>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tinput-enable;\n+\t\t};\n+\t\tpower-pins {\n+\t\t\tpinmux = <PINMUX_GPIO133__FUNC_GPIO133>,\n+\t\t\t\t <PINMUX_GPIO134__FUNC_GPIO134>;\n+\t\t\toutput-high;\n+\t\t};\n+\t};\n+\n+\teth_sleep_pins: eth-sleep-pins {\n+\t\ttxd-pins {\n+\t\t\tpinmux = <PINMUX_GPIO119__FUNC_GPIO119>,\n+\t\t\t\t <PINMUX_GPIO120__FUNC_GPIO120>,\n+\t\t\t\t <PINMUX_GPIO121__FUNC_GPIO121>,\n+\t\t\t\t <PINMUX_GPIO122__FUNC_GPIO122>;\n+\t\t};\n+\t\tcc-pins {\n+\t\t\tpinmux = <PINMUX_GPIO127__FUNC_GPIO127>,\n+\t\t\t\t <PINMUX_GPIO130__FUNC_GPIO130>,\n+\t\t\t\t <PINMUX_GPIO129__FUNC_GPIO129>,\n+\t\t\t\t <PINMUX_GPIO128__FUNC_GPIO128>;\n+\t\t};\n+\t\trxd-pins {\n+\t\t\tpinmux = <PINMUX_GPIO123__FUNC_GPIO123>,\n+\t\t\t\t <PINMUX_GPIO124__FUNC_GPIO124>,\n+\t\t\t\t <PINMUX_GPIO125__FUNC_GPIO125>,\n+\t\t\t\t <PINMUX_GPIO126__FUNC_GPIO126>;\n+\t\t};\n+\t\tmdio-pins {\n+\t\t\tpinmux = <PINMUX_GPIO131__FUNC_GPIO131>,\n+\t\t\t\t <PINMUX_GPIO132__FUNC_GPIO132>;\n+\t\t\tinput-disable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n };\n \n &pmic {\n@@ -311,3 +373,24 @@\n \tvbus-supply = <&usb_p4_vbus>;\n \tstatus = \"okay\";\n };\n+\n+ð {\n+\t/*\n+\t * TX clock is provided by MAC\n+\t */\n+\tphy-mode = \"rgmii-rxid\";\n+\tphy-handle = <&phy>;\n+\tpinctrl-names = \"default\", \"sleep\";\n+\tpinctrl-0 = <ð_default_pins>;\n+\tpinctrl-1 = <ð_sleep_pins>;\n+\tstatus = \"okay\";\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tphy: phy@0 {\n+\t\t\tcompatible = \"ethernet-phy-idc0ff.0421\";\n+\t\t\treg = <0>;\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "v4", "8/9" ] }