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Update a patch.
GET /api/patches/2228753/?format=api
{ "id": 2228753, "url": "http://patchwork.ozlabs.org/api/patches/2228753/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260427100832.581887-4-ilias.apalodimas@linaro.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260427100832.581887-4-ilias.apalodimas@linaro.org>", "list_archive_url": null, "date": "2026-04-27T10:08:24", "name": "[v3,3/6] treewide: move bi_dram[] from bd to gd", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4a893a55ee4bead101cfa7d282439fa6f0fce3ea", "submitter": { "id": 74147, "url": "http://patchwork.ozlabs.org/api/people/74147/?format=api", "name": "Ilias Apalodimas", "email": "ilias.apalodimas@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260427100832.581887-4-ilias.apalodimas@linaro.org/mbox/", "series": [ { "id": 501617, "url": "http://patchwork.ozlabs.org/api/series/501617/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501617", "date": "2026-04-27T10:08:21", "name": "Relocate U-Boot in the last bank", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501617/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228753/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228753/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Ul7XuddB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Because bd is only valid after reserve_board(),\ndram_init_banksize() must be called late in the initialization process.\nThis limitation is problematic, as it forces us to rely on a variety of\nbespoke functions to determine board RAM, bank memory sizes, and other\nearly setup requirements.\n\nBy moving bi_dram[] into the global data (gd), we can run it earlier.\nThis is particularly convenient since boards define their own\ndram_init_banksize() routines, which do not always rely on parsing\nDevice Tree (DT) memory nodes.\n\nAdditionally, U-Boot defaults to relocating to the top of the first memory\nbank. While boards currently use custom functions to override this\nbehavior, having the DRAM bank information available earlier in gd makes\nrelocating to a different bank trivial and standardizes the process.\n\nReviewed-by: Anshul Dalal <anshuld@ti.com>\nTested-by: Michal Simek <michal.simek@amd.com> # Versal Gen 2 Vek385\nTested-by: Anshul Dalal <anshuld@ti.com>\nSigned-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>\n---\n api/api_platform.c | 4 +-\n arch/arm/cpu/armv8/cache_v8.c | 6 +-\n arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 118 +++++++++---------\n arch/arm/lib/bootm-fdt.c | 5 +-\n arch/arm/lib/bootm.c | 4 +-\n arch/arm/lib/cache-cp15.c | 9 +-\n arch/arm/lib/image.c | 2 +-\n arch/arm/mach-airoha/an7581/init.c | 8 +-\n arch/arm/mach-apple/board.c | 4 +-\n arch/arm/mach-davinci/misc.c | 4 +-\n arch/arm/mach-imx/ele_ahab.c | 7 +-\n arch/arm/mach-imx/imx8/ahab.c | 7 +-\n arch/arm/mach-imx/imx8/cpu.c | 44 +++----\n arch/arm/mach-imx/imx8m/soc.c | 24 ++--\n arch/arm/mach-imx/imx8ulp/soc.c | 20 +--\n arch/arm/mach-imx/imx9/scmi/soc.c | 24 ++--\n arch/arm/mach-imx/imx9/soc.c | 24 ++--\n arch/arm/mach-imx/mx5/mx53_dram.c | 8 +-\n arch/arm/mach-imx/spl.c | 4 +-\n arch/arm/mach-k3/k3-ddr.c | 4 +-\n arch/arm/mach-mvebu/alleycat5/cpu.c | 4 +-\n arch/arm/mach-mvebu/armada3700/cpu.c | 10 +-\n arch/arm/mach-mvebu/armada8k/dram.c | 10 +-\n arch/arm/mach-mvebu/dram.c | 6 +-\n arch/arm/mach-omap2/am33xx/board.c | 4 +-\n arch/arm/mach-omap2/omap-cache.c | 5 +-\n arch/arm/mach-omap2/omap3/emif4.c | 8 +-\n arch/arm/mach-omap2/omap3/sdrc.c | 8 +-\n arch/arm/mach-owl/soc.c | 4 +-\n arch/arm/mach-renesas/memmap-gen3.c | 8 +-\n arch/arm/mach-renesas/memmap-rzg2l.c | 4 +-\n arch/arm/mach-rockchip/rk3588/rk3588.c | 8 +-\n arch/arm/mach-rockchip/sdram.c | 42 +++----\n arch/arm/mach-snapdragon/board.c | 16 +--\n arch/arm/mach-socfpga/board.c | 5 +-\n arch/arm/mach-socfpga/misc_arria10.c | 7 +-\n .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 +-\n arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 +-\n arch/arm/mach-tegra/board2.c | 14 +--\n arch/arm/mach-tegra/cboot.c | 4 +-\n arch/arm/mach-uniphier/dram_init.c | 6 +-\n arch/arm/mach-uniphier/fdt-fixup.c | 8 +-\n arch/arm/mach-versal-net/cpu.c | 8 +-\n arch/arm/mach-versal/cpu.c | 16 +--\n arch/arm/mach-versal2/cpu.c | 7 +-\n arch/arm/mach-zynqmp/cpu.c | 8 +-\n arch/mips/mach-octeon/dram.c | 4 +-\n arch/riscv/cpu/k1/dram.c | 12 +-\n arch/sandbox/cpu/spl.c | 4 +-\n arch/x86/cpu/coreboot/sdram.c | 4 +-\n arch/x86/cpu/efi/payload.c | 4 +-\n arch/x86/cpu/efi/sdram.c | 4 +-\n arch/x86/cpu/intel_common/mrc.c | 4 +-\n arch/x86/cpu/ivybridge/sdram_nop.c | 4 +-\n arch/x86/cpu/qemu/dram.c | 8 +-\n arch/x86/cpu/quark/dram.c | 4 +-\n arch/x86/cpu/slimbootloader/sdram.c | 4 +-\n arch/x86/cpu/tangier/sdram.c | 4 +-\n arch/x86/lib/bootm.c | 5 +-\n arch/x86/lib/fsp/fsp_dram.c | 18 +--\n board/CZ.NIC/turris_1x/turris_1x.c | 42 +++----\n board/armltd/corstone1000/corstone1000.c | 4 +-\n board/armltd/integrator/integrator.c | 4 +-\n board/armltd/total_compute/total_compute.c | 6 +-\n board/armltd/vexpress/vexpress_common.c | 8 +-\n board/atmel/common/video_display.c | 2 +-\n .../sam9x60_curiosity/sam9x60_curiosity.c | 2 +-\n .../sam9x75_curiosity/sam9x75_curiosity.c | 2 +-\n .../atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 2 +-\n .../sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 2 +-\n .../sama5d29_curiosity/sama5d29_curiosity.c | 2 +-\n .../atmel/sama5d2_xplained/sama5d2_xplained.c | 2 +-\n .../sama7d65_curiosity/sama7d65_curiosity.c | 2 +-\n .../sama7g54_curiosity/sama7g54_curiosity.c | 2 +-\n board/broadcom/bcmns3/ns3.c | 4 +-\n board/compulab/cm_fx6/cm_fx6.c | 28 ++---\n board/elgin/elgin_rv1108/elgin_rv1108.c | 4 +-\n board/esd/meesc/meesc.c | 4 +-\n board/friendlyarm/nanopi2/board.c | 10 +-\n board/ge/mx53ppd/mx53ppd.c | 8 +-\n board/hisilicon/hikey/hikey.c | 24 ++--\n board/hisilicon/hikey960/hikey960.c | 4 +-\n board/hisilicon/poplar/poplar.c | 4 +-\n board/k+p/kp_imx53/kp_imx53.c | 4 +-\n board/keymile/pg-wcom-ls102xa/ddr.c | 4 +-\n board/kontron/sl28/sl28.c | 4 +-\n board/kontron/sl28/spl_atf.c | 6 +-\n board/liebherr/btt/btt.c | 2 +-\n board/menlo/m53menlo/m53menlo.c | 8 +-\n board/nuvoton/arbel_evb/arbel_evb.c | 26 ++--\n board/nxp/imxrt1020-evk/imxrt1020-evk.c | 2 +-\n board/nxp/imxrt1050-evk/imxrt1050-evk.c | 2 +-\n board/nxp/imxrt1170-evk/imxrt1170-evk.c | 2 +-\n board/nxp/ls1021aqds/ddr.c | 4 +-\n board/nxp/ls1028a/ls1028a.c | 10 +-\n board/nxp/ls1043aqds/ls1043aqds.c | 8 +-\n board/nxp/ls1043ardb/ls1043ardb.c | 8 +-\n board/nxp/ls1046afrwy/ls1046afrwy.c | 8 +-\n board/nxp/ls1046aqds/ls1046aqds.c | 8 +-\n board/nxp/ls1046ardb/ls1046ardb.c | 8 +-\n board/nxp/ls1088a/ls1088a.c | 6 +-\n board/nxp/ls2080aqds/ls2080aqds.c | 14 +--\n board/nxp/ls2080ardb/ls2080ardb.c | 14 +--\n board/nxp/lx2160a/lx2160a.c | 6 +-\n board/phytec/phycore_am62x/phycore-am62x.c | 26 ++--\n board/phytec/phycore_am64x/phycore-am64x.c | 18 +--\n board/phytium/durian/durian.c | 4 +-\n board/phytium/pe2201/pe2201.c | 4 +-\n board/raspberrypi/rpi/rpi.c | 4 +-\n board/renesas/common/rcar64-common.c | 6 +-\n board/renesas/genmai/genmai.c | 4 +-\n board/renesas/sparrowhawk/sparrowhawk.c | 8 +-\n board/ronetix/pm9261/pm9261.c | 4 +-\n board/ronetix/pm9263/pm9263.c | 4 +-\n board/ronetix/pm9g45/pm9g45.c | 4 +-\n board/samsung/arndale/arndale.c | 4 +-\n board/samsung/common/board.c | 6 +-\n board/samsung/exynos-mobile/exynos-mobile.c | 4 +-\n board/samsung/goni/goni.c | 12 +-\n board/samsung/smdkc100/smdkc100.c | 4 +-\n board/samsung/smdkv310/smdkv310.c | 16 +--\n board/siemens/iot2050/board.c | 16 +--\n board/socionext/developerbox/developerbox.c | 6 +-\n board/st/stih410-b2260/board.c | 4 +-\n board/ste/stemmy/stemmy.c | 4 +-\n board/ti/dra7xx/evm.c | 8 +-\n board/ti/ks2_evm/board.c | 4 +-\n board/toradex/colibri_imx7/colibri_imx7.c | 8 +-\n board/toradex/verdin-am62/verdin-am62.c | 2 +-\n board/toradex/verdin-am62p/verdin-am62p.c | 2 +-\n board/traverse/ten64/ten64.c | 6 +-\n board/xilinx/zynq/cmds.c | 6 +-\n board/xilinx/zynqmp/zynqmp.c | 6 +-\n boot/image-board.c | 2 +-\n boot/image-fdt.c | 4 +-\n cmd/bdinfo.c | 12 +-\n cmd/ti/ddr4.c | 8 +-\n cmd/ufetch.c | 4 +-\n common/board_f.c | 10 +-\n common/init/handoff.c | 10 +-\n drivers/bootcount/bootcount_ram.c | 4 +-\n drivers/ddr/altera/sdram_agilex.c | 4 +-\n drivers/ddr/altera/sdram_agilex5.c | 18 +--\n drivers/ddr/altera/sdram_agilex7m.c | 4 +-\n drivers/ddr/altera/sdram_arria10.c | 12 +-\n drivers/ddr/altera/sdram_n5x.c | 4 +-\n drivers/ddr/altera/sdram_s10.c | 4 +-\n drivers/ddr/altera/sdram_soc64.c | 28 ++---\n drivers/mmc/mvebu_mmc.c | 4 +-\n drivers/net/mvgbe.c | 4 +-\n drivers/pci/pci-uclass.c | 8 +-\n drivers/usb/host/ehci-marvell.c | 4 +-\n drivers/video/meson/meson_vpu.c | 8 +-\n drivers/video/sunxi/sunxi_de2.c | 2 +-\n drivers/video/sunxi/sunxi_display.c | 2 +-\n include/asm-generic/global_data.h | 7 ++\n include/asm-generic/u-boot.h | 4 -\n include/configs/m53menlo.h | 4 +-\n include/configs/mx53cx9020.h | 4 +-\n include/configs/mx53loco.h | 4 +-\n include/configs/mx53ppd.h | 4 +-\n include/fdtdec.h | 7 +-\n include/init.h | 2 +-\n lib/fdtdec.c | 23 ++--\n lib/lmb.c | 13 +-\n test/cmd/bdinfo.c | 7 +-\n 166 files changed, 703 insertions(+), 710 deletions(-)\n\n--\n2.53.0", "diff": "diff --git a/api/api_platform.c b/api/api_platform.c\nindex d5cbcd6e2010..d4edf3a20fe9 100644\n--- a/api/api_platform.c\n+++ b/api/api_platform.c\n@@ -21,8 +21,8 @@ int platform_sys_info(struct sys_info *si)\n \tsi->clk_cpu = gd->cpu_clk;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)\n-\t\tplatform_set_mr(si, gd->bd->bi_dram[i].start,\n-\t\t\t\tgd->bd->bi_dram[i].size, MR_ATTR_DRAM);\n+\t\tplatform_set_mr(si, gd->dram[i].start,\n+\t\t\t\tgd->dram[i].size, MR_ATTR_DRAM);\n\n \tplatform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);\n \tplatform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);\ndiff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c\nindex 39479df7b21f..944533c30a32 100644\n--- a/arch/arm/cpu/armv8/cache_v8.c\n+++ b/arch/arm/cpu/armv8/cache_v8.c\n@@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs)\n \t}\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tmem_map[index].virt = gd->bd->bi_dram[i].start;\n-\t\tmem_map[index].phys = gd->bd->bi_dram[i].start;\n-\t\tmem_map[index].size = gd->bd->bi_dram[i].size;\n+\t\tmem_map[index].virt = gd->dram[i].start;\n+\t\tmem_map[index].phys = gd->dram[i].start;\n+\t\tmem_map[index].size = gd->dram[i].size;\n \t\tmem_map[index].attrs = attrs;\n \t\tindex++;\n \t}\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\nindex cfbaa475701a..db885c504353 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n@@ -538,16 +538,16 @@ static inline void final_mmu_setup(void)\n \t\t */\n \t\tswitch (final_map[index].virt) {\n \t\tcase CFG_SYS_FSL_DRAM_BASE1:\n-\t\t\tfinal_map[index].virt = gd->bd->bi_dram[0].start;\n-\t\t\tfinal_map[index].phys = gd->bd->bi_dram[0].start;\n-\t\t\tfinal_map[index].size = gd->bd->bi_dram[0].size;\n+\t\t\tfinal_map[index].virt = gd->dram[0].start;\n+\t\t\tfinal_map[index].phys = gd->dram[0].start;\n+\t\t\tfinal_map[index].size = gd->dram[0].size;\n \t\t\tbreak;\n #ifdef CFG_SYS_FSL_DRAM_BASE2\n \t\tcase CFG_SYS_FSL_DRAM_BASE2:\n #if (CONFIG_NR_DRAM_BANKS >= 2)\n-\t\t\tfinal_map[index].virt = gd->bd->bi_dram[1].start;\n-\t\t\tfinal_map[index].phys = gd->bd->bi_dram[1].start;\n-\t\t\tfinal_map[index].size = gd->bd->bi_dram[1].size;\n+\t\t\tfinal_map[index].virt = gd->dram[1].start;\n+\t\t\tfinal_map[index].phys = gd->dram[1].start;\n+\t\t\tfinal_map[index].size = gd->dram[1].size;\n #else\n \t\t\tfinal_map[index].size = 0;\n #endif\n@@ -556,9 +556,9 @@ static inline void final_mmu_setup(void)\n #ifdef CFG_SYS_FSL_DRAM_BASE3\n \t\tcase CFG_SYS_FSL_DRAM_BASE3:\n #if (CONFIG_NR_DRAM_BANKS >= 3)\n-\t\t\tfinal_map[index].virt = gd->bd->bi_dram[2].start;\n-\t\t\tfinal_map[index].phys = gd->bd->bi_dram[2].start;\n-\t\t\tfinal_map[index].size = gd->bd->bi_dram[2].size;\n+\t\t\tfinal_map[index].virt = gd->dram[2].start;\n+\t\t\tfinal_map[index].phys = gd->dram[2].start;\n+\t\t\tfinal_map[index].size = gd->dram[2].size;\n #else\n \t\t\tfinal_map[index].size = 0;\n #endif\n@@ -1371,10 +1371,10 @@ static int tfa_dram_init_banksize(void)\n \t\t}\n\n \t\tdebug(\"bank[%d]: start %lx, size %lx\\n\", i, res.a1, res.a2);\n-\t\tgd->bd->bi_dram[i].start = res.a1;\n-\t\tgd->bd->bi_dram[i].size = res.a2;\n+\t\tgd->dram[i].start = res.a1;\n+\t\tgd->dram[i].size = res.a2;\n\n-\t\tdram_size -= gd->bd->bi_dram[i].size;\n+\t\tdram_size -= gd->dram[i].size;\n\n \t\ti++;\n \t} while (dram_size);\n@@ -1385,24 +1385,24 @@ static int tfa_dram_init_banksize(void)\n #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)\n \t/* Assign memory for MC */\n #ifdef CONFIG_SYS_DDR_BLOCK3_BASE\n-\tif (gd->bd->bi_dram[2].size >=\n-\t board_reserve_ram_top(gd->bd->bi_dram[2].size)) {\n-\t\tgd->arch.resv_ram = gd->bd->bi_dram[2].start +\n-\t\t\t gd->bd->bi_dram[2].size -\n-\t\t\t board_reserve_ram_top(gd->bd->bi_dram[2].size);\n+\tif (gd->dram[2].size >=\n+\t board_reserve_ram_top(gd->dram[2].size)) {\n+\t\tgd->arch.resv_ram = gd->dram[2].start +\n+\t\t\t gd->dram[2].size -\n+\t\t\t board_reserve_ram_top(gd->dram[2].size);\n \t} else\n #endif\n \t{\n-\t\tif (gd->bd->bi_dram[1].size >=\n-\t\t board_reserve_ram_top(gd->bd->bi_dram[1].size)) {\n-\t\t\tgd->arch.resv_ram = gd->bd->bi_dram[1].start +\n-\t\t\t\tgd->bd->bi_dram[1].size -\n-\t\t\t\tboard_reserve_ram_top(gd->bd->bi_dram[1].size);\n-\t\t} else if (gd->bd->bi_dram[0].size >\n-\t\t\t board_reserve_ram_top(gd->bd->bi_dram[0].size)) {\n-\t\t\tgd->arch.resv_ram = gd->bd->bi_dram[0].start +\n-\t\t\t\tgd->bd->bi_dram[0].size -\n-\t\t\t\tboard_reserve_ram_top(gd->bd->bi_dram[0].size);\n+\t\tif (gd->dram[1].size >=\n+\t\t board_reserve_ram_top(gd->dram[1].size)) {\n+\t\t\tgd->arch.resv_ram = gd->dram[1].start +\n+\t\t\t\tgd->dram[1].size -\n+\t\t\t\tboard_reserve_ram_top(gd->dram[1].size);\n+\t\t} else if (gd->dram[0].size >\n+\t\t\t board_reserve_ram_top(gd->dram[0].size)) {\n+\t\t\tgd->arch.resv_ram = gd->dram[0].start +\n+\t\t\t\tgd->dram[0].size -\n+\t\t\t\tboard_reserve_ram_top(gd->dram[0].size);\n \t\t}\n \t}\n #endif\t/* CONFIG_RESV_RAM */\n@@ -1439,30 +1439,30 @@ int dram_init_banksize(void)\n \t}\n #endif\n\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n \tif (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {\n-\t\tgd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;\n-\t\tgd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;\n-\t\tgd->bd->bi_dram[1].size = gd->ram_size -\n+\t\tgd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;\n+\t\tgd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;\n+\t\tgd->dram[1].size = gd->ram_size -\n \t\t\t\t\t CFG_SYS_DDR_BLOCK1_SIZE;\n #ifdef CONFIG_SYS_DDR_BLOCK3_BASE\n-\t\tif (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {\n-\t\t\tgd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;\n-\t\t\tgd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -\n+\t\tif (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {\n+\t\t\tgd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;\n+\t\t\tgd->dram[2].size = gd->dram[1].size -\n \t\t\t\t\t\t CONFIG_SYS_DDR_BLOCK2_SIZE;\n-\t\t\tgd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;\n+\t\t\tgd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;\n \t\t}\n #endif\n \t} else {\n-\t\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\t\tgd->dram[0].size = gd->ram_size;\n \t}\n #ifdef CFG_SYS_MEM_RESERVE_SECURE\n-\tif (gd->bd->bi_dram[0].size >\n+\tif (gd->dram[0].size >\n \t\t\t\tCFG_SYS_MEM_RESERVE_SECURE) {\n-\t\tgd->bd->bi_dram[0].size -=\n+\t\tgd->dram[0].size -=\n \t\t\t\tCFG_SYS_MEM_RESERVE_SECURE;\n-\t\tgd->arch.secure_ram = gd->bd->bi_dram[0].start +\n-\t\t\t\t gd->bd->bi_dram[0].size;\n+\t\tgd->arch.secure_ram = gd->dram[0].start +\n+\t\t\t\t gd->dram[0].size;\n \t\tgd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;\n \t\tgd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;\n \t}\n@@ -1471,24 +1471,24 @@ int dram_init_banksize(void)\n #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)\n \t/* Assign memory for MC */\n #ifdef CONFIG_SYS_DDR_BLOCK3_BASE\n-\tif (gd->bd->bi_dram[2].size >=\n-\t board_reserve_ram_top(gd->bd->bi_dram[2].size)) {\n-\t\tgd->arch.resv_ram = gd->bd->bi_dram[2].start +\n-\t\t\t gd->bd->bi_dram[2].size -\n-\t\t\t board_reserve_ram_top(gd->bd->bi_dram[2].size);\n+\tif (gd->dram[2].size >=\n+\t board_reserve_ram_top(gd->dram[2].size)) {\n+\t\tgd->arch.resv_ram = gd->dram[2].start +\n+\t\t\t gd->dram[2].size -\n+\t\t\t board_reserve_ram_top(gd->dram[2].size);\n \t} else\n #endif\n \t{\n-\t\tif (gd->bd->bi_dram[1].size >=\n-\t\t board_reserve_ram_top(gd->bd->bi_dram[1].size)) {\n-\t\t\tgd->arch.resv_ram = gd->bd->bi_dram[1].start +\n-\t\t\t\tgd->bd->bi_dram[1].size -\n-\t\t\t\tboard_reserve_ram_top(gd->bd->bi_dram[1].size);\n-\t\t} else if (gd->bd->bi_dram[0].size >\n-\t\t\t board_reserve_ram_top(gd->bd->bi_dram[0].size)) {\n-\t\t\tgd->arch.resv_ram = gd->bd->bi_dram[0].start +\n-\t\t\t\tgd->bd->bi_dram[0].size -\n-\t\t\t\tboard_reserve_ram_top(gd->bd->bi_dram[0].size);\n+\t\tif (gd->dram[1].size >=\n+\t\t board_reserve_ram_top(gd->dram[1].size)) {\n+\t\t\tgd->arch.resv_ram = gd->dram[1].start +\n+\t\t\t\tgd->dram[1].size -\n+\t\t\t\tboard_reserve_ram_top(gd->dram[1].size);\n+\t\t} else if (gd->dram[0].size >\n+\t\t\t board_reserve_ram_top(gd->dram[0].size)) {\n+\t\t\tgd->arch.resv_ram = gd->dram[0].start +\n+\t\t\t\tgd->dram[0].size -\n+\t\t\t\tboard_reserve_ram_top(gd->dram[0].size);\n \t\t}\n \t}\n #endif\t/* CONFIG_RESV_RAM */\n@@ -1510,8 +1510,8 @@ int dram_init_banksize(void)\n \t\t\t\t\t CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,\n \t\t\t\t\t NULL, NULL, NULL);\n \t\tif (dp_ddr_size) {\n-\t\t\tgd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;\n-\t\t\tgd->bd->bi_dram[2].size = dp_ddr_size;\n+\t\t\tgd->dram[2].start = CONFIG_SYS_DP_DDR_BASE;\n+\t\t\tgd->dram[2].size = dp_ddr_size;\n \t\t} else {\n \t\t\tputs(\"Not detected\");\n \t\t}\n@@ -1542,8 +1542,8 @@ void lmb_arch_add_memory(void)\n \t\tif (i == 2)\n \t\t\tcontinue;\t/* skip DP-DDR */\n #endif\n-\t\tram_start = gd->bd->bi_dram[i].start;\n-\t\tram_size = gd->bd->bi_dram[i].size;\n+\t\tram_start = gd->dram[i].start;\n+\t\tram_size = gd->dram[i].size;\n #ifdef CONFIG_RESV_RAM\n \t\tif (gd->arch.resv_ram >= ram_start &&\n \t\t gd->arch.resv_ram < ram_start + ram_size)\ndiff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c\nindex 2671f9a0ebf5..a82ceeaf22ff 100644\n--- a/arch/arm/lib/bootm-fdt.c\n+++ b/arch/arm/lib/bootm-fdt.c\n@@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob)\n {\n \t__maybe_unused int ret = 0;\n #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)\n-\tstruct bd_info *bd = gd->bd;\n \tint bank;\n \tu64 start[CONFIG_NR_DRAM_BANKS];\n \tu64 size[CONFIG_NR_DRAM_BANKS];\n\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart[bank] = bd->bi_dram[bank].start;\n-\t\tsize[bank] = bd->bi_dram[bank].size;\n+\t\tstart[bank] = gd->dram[bank].start;\n+\t\tsize[bank] = gd->dram[bank].size;\n #ifdef CONFIG_ARMV7_NONSEC\n \t\tret = armv7_apply_memory_carveout(&start[bank], &size[bank]);\n \t\tif (ret)\ndiff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c\nindex 1cde655bc80c..9a115cc60784 100644\n--- a/arch/arm/lib/bootm.c\n+++ b/arch/arm/lib/bootm.c\n@@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd)\n \t\tparams->hdr.tag = ATAG_MEM;\n \t\tparams->hdr.size = tag_size (tag_mem32);\n\n-\t\tparams->u.mem.start = bd->bi_dram[i].start;\n-\t\tparams->u.mem.size = bd->bi_dram[i].size;\n+\t\tparams->u.mem.start = gd->dram[i].start;\n+\t\tparams->u.mem.size = gd->dram[i].size;\n\n \t\tparams = tag_next (params);\n \t}\ndiff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c\nindex 947012f29963..28bb6fd36c8c 100644\n--- a/arch/arm/lib/cache-cp15.c\n+++ b/arch/arm/lib/cache-cp15.c\n@@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,\n\n __weak void dram_bank_mmu_setup(int bank)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tint\ti;\n\n-\t/* bd->bi_dram is available only after relocation */\n+\t/* gd->dram is available only after relocation */\n \tif ((gd->flags & GD_FLG_RELOC) == 0)\n \t\treturn;\n\n \tdebug(\"%s: bank: %d\\n\", __func__, bank);\n-\tfor (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;\n-\t i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +\n-\t\t (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);\n+\tfor (i = gd->dram[bank].start >> MMU_SECTION_SHIFT;\n+\t i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) +\n+\t\t (gd->dram[bank].size >> MMU_SECTION_SHIFT);\n \t i++)\n \t\tset_section_dcache(i, DCACHE_DEFAULT_OPTION);\n }\ndiff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c\nindex 1f672eee2c86..2268661de93a 100644\n--- a/arch/arm/lib/image.c\n+++ b/arch/arm/lib/image.c\n@@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size,\n \tif (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3)))\n \t\tdst = image - text_offset;\n \telse\n-\t\tdst = gd->bd->bi_dram[0].start;\n+\t\tdst = gd->dram[0].start;\n\n \t*relocated_addr = ALIGN(dst, SZ_2M) + text_offset;\n\ndiff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c\nindex ab32706a79d0..f33527ca129a 100644\n--- a/arch/arm/mach-airoha/an7581/init.c\n+++ b/arch/arm/mach-airoha/an7581/init.c\n@@ -23,12 +23,12 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = gd->ram_base;\n-\tgd->bd->bi_dram[0].size = get_effective_memsize();\n+\tgd->dram[0].start = gd->ram_base;\n+\tgd->dram[0].size = get_effective_memsize();\n\n \tif (gd->ram_size > SZ_2G) {\n-\t\tgd->bd->bi_dram[1].start = gd->ram_base + SZ_2G;\n-\t\tgd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;\n+\t\tgd->dram[1].start = gd->ram_base + SZ_2G;\n+\t\tgd->dram[1].size = gd->ram_size - SZ_2G;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c\nindex 4cd8979bdc20..d65449e35861 100644\n--- a/arch/arm/mach-apple/board.c\n+++ b/arch/arm/mach-apple/board.c\n@@ -728,8 +728,8 @@ void build_mem_map(void)\n \t\t;\n\n \t/* Align RAM mapping to page boundaries */\n-\tbase = gd->bd->bi_dram[0].start;\n-\tsize = gd->bd->bi_dram[0].size;\n+\tbase = gd->dram[0].start;\n+\tsize = gd->dram[0].size;\n \tsize += (base - ALIGN_DOWN(base, SZ_4K));\n \tbase = ALIGN_DOWN(base, SZ_4K);\n \tsize = ALIGN(size, SZ_4K);\ndiff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c\nindex 07125eac7cd3..2281686d6338 100644\n--- a/arch/arm/mach-davinci/misc.c\n+++ b/arch/arm/mach-davinci/misc.c\n@@ -33,8 +33,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c\nindex 9794391fb354..f49fabf32196 100644\n--- a/arch/arm/mach-imx/ele_ahab.c\n+++ b/arch/arm/mach-imx/ele_ahab.c\n@@ -310,12 +310,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)\n static inline bool check_in_dram(ulong addr)\n {\n \tint i;\n-\tstruct bd_info *bd = gd->bd;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {\n-\t\tif (bd->bi_dram[i].size) {\n-\t\t\tif (addr >= bd->bi_dram[i].start &&\n-\t\t\t addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))\n+\t\tif (gd->dram[i].size) {\n+\t\t\tif (addr >= gd->dram[i].start &&\n+\t\t\t addr < (gd->dram[i].start + gd->dram[i].size))\n \t\t\t\treturn true;\n \t\t}\n \t}\ndiff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c\nindex f13baa871cc2..abefb9d5493c 100644\n--- a/arch/arm/mach-imx/imx8/ahab.c\n+++ b/arch/arm/mach-imx/imx8/ahab.c\n@@ -109,12 +109,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)\n static inline bool check_in_dram(ulong addr)\n {\n \tint i;\n-\tstruct bd_info *bd = gd->bd;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {\n-\t\tif (bd->bi_dram[i].size) {\n-\t\t\tif (addr >= bd->bi_dram[i].start &&\n-\t\t\t addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))\n+\t\tif (gd->dram[i].size) {\n+\t\t\tif (addr >= gd->dram[i].start &&\n+\t\t\t addr < (gd->dram[i].start + gd->dram[i].size))\n \t\t\t\treturn true;\n \t\t}\n \t}\ndiff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c\nindex f4738e3fda8b..b52675d8aba6 100644\n--- a/arch/arm/mach-imx/imx8/cpu.c\n+++ b/arch/arm/mach-imx/imx8/cpu.c\n@@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank)\n \tphys_size_t size;\n\n \twhile (current_bank > 0) {\n-\t\tif (gd->bd->bi_dram[current_bank - 1].start >\n-\t\t gd->bd->bi_dram[current_bank].start) {\n-\t\t\tstart = gd->bd->bi_dram[current_bank - 1].start;\n-\t\t\tsize = gd->bd->bi_dram[current_bank - 1].size;\n-\n-\t\t\tgd->bd->bi_dram[current_bank - 1].start =\n-\t\t\t\tgd->bd->bi_dram[current_bank].start;\n-\t\t\tgd->bd->bi_dram[current_bank - 1].size =\n-\t\t\t\tgd->bd->bi_dram[current_bank].size;\n-\n-\t\t\tgd->bd->bi_dram[current_bank].start = start;\n-\t\t\tgd->bd->bi_dram[current_bank].size = size;\n+\t\tif (gd->dram[current_bank - 1].start >\n+\t\t gd->dram[current_bank].start) {\n+\t\t\tstart = gd->dram[current_bank - 1].start;\n+\t\t\tsize = gd->dram[current_bank - 1].size;\n+\n+\t\t\tgd->dram[current_bank - 1].start =\n+\t\t\t\tgd->dram[current_bank].start;\n+\t\t\tgd->dram[current_bank - 1].size =\n+\t\t\t\tgd->dram[current_bank].size;\n+\n+\t\t\tgd->dram[current_bank].start = start;\n+\t\t\tgd->dram[current_bank].size = size;\n \t\t}\n \t\tcurrent_bank--;\n \t}\n@@ -643,24 +643,24 @@ int dram_init_banksize(void)\n \t\t\t\tcontinue;\n\n \t\t\tif (start >= phys_sdram_1_start && start <= end1) {\n-\t\t\t\tgd->bd->bi_dram[i].start = start;\n+\t\t\t\tgd->dram[i].start = start;\n\n \t\t\t\tif ((end + 1) <= end1)\n-\t\t\t\t\tgd->bd->bi_dram[i].size =\n+\t\t\t\t\tgd->dram[i].size =\n \t\t\t\t\t\tend - start + 1;\n \t\t\t\telse\n-\t\t\t\t\tgd->bd->bi_dram[i].size = end1 - start;\n+\t\t\t\t\tgd->dram[i].size = end1 - start;\n\n \t\t\t\tdram_bank_sort(i);\n \t\t\t\ti++;\n \t\t\t} else if (start >= phys_sdram_2_start && start <= end2) {\n-\t\t\t\tgd->bd->bi_dram[i].start = start;\n+\t\t\t\tgd->dram[i].start = start;\n\n \t\t\t\tif ((end + 1) <= end2)\n-\t\t\t\t\tgd->bd->bi_dram[i].size =\n+\t\t\t\t\tgd->dram[i].size =\n \t\t\t\t\t\tend - start + 1;\n \t\t\t\telse\n-\t\t\t\t\tgd->bd->bi_dram[i].size = end2 - start;\n+\t\t\t\t\tgd->dram[i].size = end2 - start;\n\n \t\t\t\tdram_bank_sort(i);\n \t\t\t\ti++;\n@@ -670,10 +670,10 @@ int dram_init_banksize(void)\n\n \t/* If error, set to the default value */\n \tif (!i) {\n-\t\tgd->bd->bi_dram[0].start = phys_sdram_1_start;\n-\t\tgd->bd->bi_dram[0].size = phys_sdram_1_size;\n-\t\tgd->bd->bi_dram[1].start = phys_sdram_2_start;\n-\t\tgd->bd->bi_dram[1].size = phys_sdram_2_size;\n+\t\tgd->dram[0].start = phys_sdram_1_start;\n+\t\tgd->dram[0].size = phys_sdram_1_size;\n+\t\tgd->dram[1].start = phys_sdram_2_start;\n+\t\tgd->dram[1].size = phys_sdram_2_size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c\nindex 1fe083ae94ff..84d4ebdb9193 100644\n--- a/arch/arm/mach-imx/imx8m/soc.c\n+++ b/arch/arm/mach-imx/imx8m/soc.c\n@@ -224,11 +224,11 @@ void enable_caches(void)\n\n \twhile (i < CONFIG_NR_DRAM_BANKS &&\n \t entry < ARRAY_SIZE(imx8m_mem_map)) {\n-\t\tif (gd->bd->bi_dram[i].start == 0)\n+\t\tif (gd->dram[i].start == 0)\n \t\t\tbreak;\n-\t\timx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;\n-\t\timx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;\n-\t\timx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;\n+\t\timx8m_mem_map[entry].phys = gd->dram[i].start;\n+\t\timx8m_mem_map[entry].virt = gd->dram[i].start;\n+\t\timx8m_mem_map[entry].size = gd->dram[i].size;\n \t\timx8m_mem_map[entry].attrs = attrs;\n \t\tdebug(\"Added memory mapping (%d): %llx %llx\\n\", entry,\n \t\t imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);\n@@ -290,24 +290,24 @@ int dram_init_banksize(void)\n \t\tsdram_b2_size = 0;\n \t}\n\n-\tgd->bd->bi_dram[bank].start = PHYS_SDRAM;\n+\tgd->dram[bank].start = PHYS_SDRAM;\n \tif (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {\n \t\tphys_addr_t optee_start = (phys_addr_t)rom_pointer[0];\n \t\tphys_size_t optee_size = (size_t)rom_pointer[1];\n\n-\t\tgd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;\n+\t\tgd->dram[bank].size = optee_start - gd->dram[bank].start;\n \t\tif ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {\n \t\t\tif (++bank >= CONFIG_NR_DRAM_BANKS) {\n \t\t\t\tputs(\"CONFIG_NR_DRAM_BANKS is not enough\\n\");\n \t\t\t\treturn -1;\n \t\t\t}\n\n-\t\t\tgd->bd->bi_dram[bank].start = optee_start + optee_size;\n-\t\t\tgd->bd->bi_dram[bank].size = PHYS_SDRAM +\n-\t\t\t\tsdram_b1_size - gd->bd->bi_dram[bank].start;\n+\t\t\tgd->dram[bank].start = optee_start + optee_size;\n+\t\t\tgd->dram[bank].size = PHYS_SDRAM +\n+\t\t\t\tsdram_b1_size - gd->dram[bank].start;\n \t\t}\n \t} else {\n-\t\tgd->bd->bi_dram[bank].size = sdram_b1_size;\n+\t\tgd->dram[bank].size = sdram_b1_size;\n \t}\n\n \tif (sdram_b2_size) {\n@@ -315,8 +315,8 @@ int dram_init_banksize(void)\n \t\t\tputs(\"CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\\n\");\n \t\t\treturn -1;\n \t\t}\n-\t\tgd->bd->bi_dram[bank].start = 0x100000000UL;\n-\t\tgd->bd->bi_dram[bank].size = sdram_b2_size;\n+\t\tgd->dram[bank].start = 0x100000000UL;\n+\t\tgd->dram[bank].size = sdram_b2_size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c\nindex 1ee483065e85..22c79c8889b2 100644\n--- a/arch/arm/mach-imx/imx8ulp/soc.c\n+++ b/arch/arm/mach-imx/imx8ulp/soc.c\n@@ -502,11 +502,11 @@ void enable_caches(void)\n\n \t\twhile (i < CONFIG_NR_DRAM_BANKS &&\n \t\t entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {\n-\t\t\tif (gd->bd->bi_dram[i].start == 0)\n+\t\t\tif (gd->dram[i].start == 0)\n \t\t\t\tbreak;\n-\t\t\timx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;\n-\t\t\timx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;\n-\t\t\timx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;\n+\t\t\timx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start;\n+\t\t\timx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start;\n+\t\t\timx8ulp_arm64_mem_map[entry].size = gd->dram[i].size;\n \t\t\timx8ulp_arm64_mem_map[entry].attrs = attrs;\n \t\t\tdebug(\"Added memory mapping (%d): %llx %llx\\n\", entry,\n \t\t\t imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);\n@@ -558,24 +558,24 @@ int dram_init_banksize(void)\n \tif (ret)\n \t\treturn ret;\n\n-\tgd->bd->bi_dram[bank].start = PHYS_SDRAM;\n+\tgd->dram[bank].start = PHYS_SDRAM;\n \tif (rom_pointer[1]) {\n \t\tphys_addr_t optee_start = (phys_addr_t)rom_pointer[0];\n \t\tphys_size_t optee_size = (size_t)rom_pointer[1];\n\n-\t\tgd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;\n+\t\tgd->dram[bank].size = optee_start - gd->dram[bank].start;\n \t\tif ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {\n \t\t\tif (++bank >= CONFIG_NR_DRAM_BANKS) {\n \t\t\t\tputs(\"CONFIG_NR_DRAM_BANKS is not enough\\n\");\n \t\t\t\treturn -1;\n \t\t\t}\n\n-\t\t\tgd->bd->bi_dram[bank].start = optee_start + optee_size;\n-\t\t\tgd->bd->bi_dram[bank].size = PHYS_SDRAM +\n-\t\t\t\tsdram_size - gd->bd->bi_dram[bank].start;\n+\t\t\tgd->dram[bank].start = optee_start + optee_size;\n+\t\t\tgd->dram[bank].size = PHYS_SDRAM +\n+\t\t\t\tsdram_size - gd->dram[bank].start;\n \t\t}\n \t} else {\n-\t\tgd->bd->bi_dram[bank].size = sdram_size;\n+\t\tgd->dram[bank].size = sdram_size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c\nindex fbee435786cd..c07ec1e1ec72 100644\n--- a/arch/arm/mach-imx/imx9/scmi/soc.c\n+++ b/arch/arm/mach-imx/imx9/scmi/soc.c\n@@ -348,11 +348,11 @@ void enable_caches(void)\n\n \twhile (i < CONFIG_NR_DRAM_BANKS &&\n \t entry < ARRAY_SIZE(imx9_mem_map)) {\n-\t\tif (gd->bd->bi_dram[i].start == 0)\n+\t\tif (gd->dram[i].start == 0)\n \t\t\tbreak;\n-\t\timx9_mem_map[entry].phys = gd->bd->bi_dram[i].start;\n-\t\timx9_mem_map[entry].virt = gd->bd->bi_dram[i].start;\n-\t\timx9_mem_map[entry].size = gd->bd->bi_dram[i].size;\n+\t\timx9_mem_map[entry].phys = gd->dram[i].start;\n+\t\timx9_mem_map[entry].virt = gd->dram[i].start;\n+\t\timx9_mem_map[entry].size = gd->dram[i].size;\n \t\timx9_mem_map[entry].attrs = attrs;\n \t\tdebug(\"Added memory mapping (%d): %llx %llx\\n\", entry,\n \t\t imx9_mem_map[entry].phys, imx9_mem_map[entry].size);\n@@ -445,24 +445,24 @@ int dram_init_banksize(void)\n \t\tsdram_b2_size = 0;\n \t}\n\n-\tgd->bd->bi_dram[bank].start = PHYS_SDRAM;\n+\tgd->dram[bank].start = PHYS_SDRAM;\n \tif (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) {\n \t\tphys_addr_t optee_start = (phys_addr_t)rom_pointer[0];\n \t\tphys_size_t optee_size = (size_t)rom_pointer[1];\n\n-\t\tgd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;\n+\t\tgd->dram[bank].size = optee_start - gd->dram[bank].start;\n \t\tif ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {\n \t\t\tif (++bank >= CONFIG_NR_DRAM_BANKS) {\n \t\t\t\tputs(\"CONFIG_NR_DRAM_BANKS is not enough\\n\");\n \t\t\t\treturn -1;\n \t\t\t}\n\n-\t\t\tgd->bd->bi_dram[bank].start = optee_start + optee_size;\n-\t\t\tgd->bd->bi_dram[bank].size = PHYS_SDRAM +\n-\t\t\t\tsdram_b1_size - gd->bd->bi_dram[bank].start;\n+\t\t\tgd->dram[bank].start = optee_start + optee_size;\n+\t\t\tgd->dram[bank].size = PHYS_SDRAM +\n+\t\t\t\tsdram_b1_size - gd->dram[bank].start;\n \t\t}\n \t} else {\n-\t\tgd->bd->bi_dram[bank].size = sdram_b1_size;\n+\t\tgd->dram[bank].size = sdram_b1_size;\n \t}\n\n \tif (sdram_b2_size) {\n@@ -470,8 +470,8 @@ int dram_init_banksize(void)\n \t\t\tputs(\"CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\\n\");\n \t\t\treturn -1;\n \t\t}\n-\t\tgd->bd->bi_dram[bank].start = 0x100000000UL;\n-\t\tgd->bd->bi_dram[bank].size = sdram_b2_size;\n+\t\tgd->dram[bank].start = 0x100000000UL;\n+\t\tgd->dram[bank].size = sdram_b2_size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c\nindex 44b3e0f53101..63806f1b484c 100644\n--- a/arch/arm/mach-imx/imx9/soc.c\n+++ b/arch/arm/mach-imx/imx9/soc.c\n@@ -370,11 +370,11 @@ void enable_caches(void)\n\n \twhile (i < CONFIG_NR_DRAM_BANKS &&\n \t entry < ARRAY_SIZE(imx93_mem_map)) {\n-\t\tif (gd->bd->bi_dram[i].start == 0)\n+\t\tif (gd->dram[i].start == 0)\n \t\t\tbreak;\n-\t\timx93_mem_map[entry].phys = gd->bd->bi_dram[i].start;\n-\t\timx93_mem_map[entry].virt = gd->bd->bi_dram[i].start;\n-\t\timx93_mem_map[entry].size = gd->bd->bi_dram[i].size;\n+\t\timx93_mem_map[entry].phys = gd->dram[i].start;\n+\t\timx93_mem_map[entry].virt = gd->dram[i].start;\n+\t\timx93_mem_map[entry].size = gd->dram[i].size;\n \t\timx93_mem_map[entry].attrs = attrs;\n \t\tdebug(\"Added memory mapping (%d): %llx %llx\\n\", entry,\n \t\t imx93_mem_map[entry].phys, imx93_mem_map[entry].size);\n@@ -448,24 +448,24 @@ int dram_init_banksize(void)\n \t\tsdram_b2_size = 0;\n \t}\n\n-\tgd->bd->bi_dram[bank].start = PHYS_SDRAM;\n+\tgd->dram[bank].start = PHYS_SDRAM;\n \tif (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {\n \t\tphys_addr_t optee_start = (phys_addr_t)rom_pointer[0];\n \t\tphys_size_t optee_size = (size_t)rom_pointer[1];\n\n-\t\tgd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;\n+\t\tgd->dram[bank].size = optee_start - gd->dram[bank].start;\n \t\tif ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {\n \t\t\tif (++bank >= CONFIG_NR_DRAM_BANKS) {\n \t\t\t\tputs(\"CONFIG_NR_DRAM_BANKS is not enough\\n\");\n \t\t\t\treturn -1;\n \t\t\t}\n\n-\t\t\tgd->bd->bi_dram[bank].start = optee_start + optee_size;\n-\t\t\tgd->bd->bi_dram[bank].size = PHYS_SDRAM +\n-\t\t\t\tsdram_b1_size - gd->bd->bi_dram[bank].start;\n+\t\t\tgd->dram[bank].start = optee_start + optee_size;\n+\t\t\tgd->dram[bank].size = PHYS_SDRAM +\n+\t\t\t\tsdram_b1_size - gd->dram[bank].start;\n \t\t}\n \t} else {\n-\t\tgd->bd->bi_dram[bank].size = sdram_b1_size;\n+\t\tgd->dram[bank].size = sdram_b1_size;\n \t}\n\n \tif (sdram_b2_size) {\n@@ -473,8 +473,8 @@ int dram_init_banksize(void)\n \t\t\tputs(\"CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\\n\");\n \t\t\treturn -1;\n \t\t}\n-\t\tgd->bd->bi_dram[bank].start = 0x100000000UL;\n-\t\tgd->bd->bi_dram[bank].size = sdram_b2_size;\n+\t\tgd->dram[bank].start = 0x100000000UL;\n+\t\tgd->dram[bank].size = sdram_b2_size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c\nindex 180a745d4351..5f7709e00b0f 100644\n--- a/arch/arm/mach-imx/mx5/mx53_dram.c\n+++ b/arch/arm/mach-imx/mx5/mx53_dram.c\n@@ -35,11 +35,11 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);\n\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_2;\n-\tgd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);\n+\tgd->dram[1].start = PHYS_SDRAM_2;\n+\tgd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c\nindex 57ae81c7834e..1029c1e4e856 100644\n--- a/arch/arm/mach-imx/spl.c\n+++ b/arch/arm/mach-imx/spl.c\n@@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit)\n #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = imx_ddr_size();\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = imx_ddr_size();\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c\nindex 6e3e60cdc865..35c30b1a16f3 100644\n--- a/arch/arm/mach-k3/k3-ddr.c\n+++ b/arch/arm/mach-k3/k3-ddr.c\n@@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image)\n \tdram_init_banksize();\n\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart[bank] = gd->bd->bi_dram[bank].start;\n-\t\tsize[bank] = gd->bd->bi_dram[bank].size;\n+\t\tstart[bank] = gd->dram[bank].start;\n+\t\tsize[bank] = gd->dram[bank].size;\n \t}\n\n \tret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,\ndiff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c\nindex be2d9a25bf90..3ebb4294bddc 100644\n--- a/arch/arm/mach-mvebu/alleycat5/cpu.c\n+++ b/arch/arm/mach-mvebu/alleycat5/cpu.c\n@@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void)\n \t/*\n \t * Config single DRAM bank\n \t */\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c\nindex 17525691e682..38d9b40f482e 100644\n--- a/arch/arm/mach-mvebu/armada3700/cpu.c\n+++ b/arch/arm/mach-mvebu/armada3700/cpu.c\n@@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void)\n \t\t * build_mem_map.\n \t\t */\n \t\tif (last_end == dram_wins[win].base) {\n-\t\t\tgd->bd->bi_dram[bank - 1].size += size;\n+\t\t\tgd->dram[bank - 1].size += size;\n \t\t\tlast_end += size;\n \t\t} else {\n \t\t\tif (bank == CONFIG_NR_DRAM_BANKS) {\n@@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void)\n \t\t\t\treturn -ENOBUFS;\n \t\t\t}\n\n-\t\t\tgd->bd->bi_dram[bank].start = dram_wins[win].base;\n-\t\t\tgd->bd->bi_dram[bank].size = size;\n+\t\t\tgd->dram[bank].start = dram_wins[win].base;\n+\t\t\tgd->dram[bank].size = size;\n \t\t\tlast_end = dram_wins[win].base + size;\n \t\t\t++bank;\n \t\t}\n@@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void)\n \t * the rest with zeros.\n \t */\n \tfor (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {\n-\t\tgd->bd->bi_dram[bank].start = 0;\n-\t\tgd->bd->bi_dram[bank].size = 0;\n+\t\tgd->dram[bank].start = 0;\n+\t\tgd->dram[bank].size = 0;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c\nindex fd58551d0e32..af37dfa22523 100644\n--- a/arch/arm/mach-mvebu/armada8k/dram.c\n+++ b/arch/arm/mach-mvebu/armada8k/dram.c\n@@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void)\n \t */\n \tphys_size_t max_bank0_size = SZ_4G - SZ_1G;\n\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n \tif (gd->ram_size <= max_bank0_size) {\n-\t\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\t\tgd->dram[0].size = gd->ram_size;\n \t\treturn 0;\n \t}\n\n-\tgd->bd->bi_dram[0].size = max_bank0_size;\n+\tgd->dram[0].size = max_bank0_size;\n \tif (CONFIG_NR_DRAM_BANKS > 1) {\n-\t\tgd->bd->bi_dram[1].start = SZ_4G;\n-\t\tgd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;\n+\t\tgd->dram[1].start = SZ_4G;\n+\t\tgd->dram[1].size = gd->ram_size - max_bank0_size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c\nindex c00c6b9b3fc2..41eaaa24bd0f 100644\n--- a/arch/arm/mach-mvebu/dram.c\n+++ b/arch/arm/mach-mvebu/dram.c\n@@ -294,11 +294,11 @@ int dram_init_banksize(void)\n \tint i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tgd->bd->bi_dram[i].start = mvebu_sdram_bar(i);\n-\t\tgd->bd->bi_dram[i].size = mvebu_sdram_bs(i);\n+\t\tgd->dram[i].start = mvebu_sdram_bar(i);\n+\t\tgd->dram[i].size = mvebu_sdram_bs(i);\n\n \t\t/* Clip the banksize to 1GiB if it exceeds the max size */\n-\t\tsize += gd->bd->bi_dram[i].size;\n+\t\tsize += gd->dram[i].size;\n \t\tif (size > MVEBU_SDRAM_SIZE_MAX)\n \t\t\tmvebu_sdram_bs_set(i, 0x40000000);\n \t}\ndiff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c\nindex 4e9ad8935e3b..38e4cfdb5b72 100644\n--- a/arch/arm/mach-omap2/am33xx/board.c\n+++ b/arch/arm/mach-omap2/am33xx/board.c\n@@ -80,8 +80,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c\nindex 200a08fa5c83..f08a9b263f64 100644\n--- a/arch/arm/mach-omap2/omap-cache.c\n+++ b/arch/arm/mach-omap2/omap-cache.c\n@@ -53,11 +53,10 @@ void enable_caches(void)\n\n void dram_bank_mmu_setup(int bank)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tint\ti;\n\n-\tu32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;\n-\tu32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;\n+\tu32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT;\n+\tu32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT;\n \tu32 end = start + size;\n\n \tdebug(\"%s: bank: %d\\n\", __func__, bank);\ndiff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c\nindex 049eedfeb65b..67e14d70e921 100644\n--- a/arch/arm/mach-omap2/omap3/emif4.c\n+++ b/arch/arm/mach-omap2/omap3/emif4.c\n@@ -150,10 +150,10 @@ int dram_init_banksize(void)\n \tsize0 = get_sdr_cs_size(CS0);\n \tsize1 = get_sdr_cs_size(CS1);\n\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = size0;\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);\n-\tgd->bd->bi_dram[1].size = size1;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = size0;\n+\tgd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);\n+\tgd->dram[1].size = size1;\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c\nindex 24fae4843698..c4187369c293 100644\n--- a/arch/arm/mach-omap2/omap3/sdrc.c\n+++ b/arch/arm/mach-omap2/omap3/sdrc.c\n@@ -222,10 +222,10 @@ int dram_init_banksize(void)\n \tsize0 = get_sdr_cs_size(CS0);\n \tsize1 = get_sdr_cs_size(CS1);\n\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = size0;\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);\n-\tgd->bd->bi_dram[1].size = size1;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = size0;\n+\tgd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);\n+\tgd->dram[1].size = size1;\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c\nindex 0130cad76782..e316c2cc40e1 100644\n--- a/arch/arm/mach-owl/soc.c\n+++ b/arch/arm/mach-owl/soc.c\n@@ -50,8 +50,8 @@ int dram_init(void)\n /* This is called after dram_init() so use get_ram_size result */\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c\nindex d24419f5daa5..f7dc2be6ccaa 100644\n--- a/arch/arm/mach-renesas/memmap-gen3.c\n+++ b/arch/arm/mach-renesas/memmap-gen3.c\n@@ -70,8 +70,8 @@ void enable_caches(void)\n\n \t/* Generate entires for DRAM in 32bit address space */\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart = gd->bd->bi_dram[bank].start;\n-\t\tsize = gd->bd->bi_dram[bank].size;\n+\t\tstart = gd->dram[bank].start;\n+\t\tsize = gd->dram[bank].size;\n\n \t\t/* Skip empty DRAM banks */\n \t\tif (!size)\n@@ -114,8 +114,8 @@ void enable_caches(void)\n\n \t/* Generate entires for DRAM in 64bit address space */\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart = gd->bd->bi_dram[bank].start;\n-\t\tsize = gd->bd->bi_dram[bank].size;\n+\t\tstart = gd->dram[bank].start;\n+\t\tsize = gd->dram[bank].size;\n\n \t\t/* Skip empty DRAM banks */\n \t\tif (!size)\ndiff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c\nindex 3b3c6f7cde9a..5981b3c9c4d2 100644\n--- a/arch/arm/mach-renesas/memmap-rzg2l.c\n+++ b/arch/arm/mach-renesas/memmap-rzg2l.c\n@@ -67,8 +67,8 @@ void enable_caches(void)\n\n \t/* Generate entries for DRAM in 32bit address space */\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart = gd->bd->bi_dram[bank].start;\n-\t\tsize = gd->bd->bi_dram[bank].size;\n+\t\tstart = gd->dram[bank].start;\n+\t\tsize = gd->dram[bank].size;\n\n \t\t/* Skip empty DRAM banks */\n \t\tif (!size)\ndiff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c\nindex eedce7b9b084..c8de1a210249 100644\n--- a/arch/arm/mach-rockchip/rk3588/rk3588.c\n+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c\n@@ -243,14 +243,14 @@ int arch_cpu_init(void)\n\n int rockchip_dram_init_banksize_fixup(struct bd_info *bd)\n {\n-\tsize_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size;\n+\tsize_t ram_top = gd->dram[1].start + gd->dram[1].size;\n\n \tif (ram_top > DRAM_GAP_START) {\n-\t\tbd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start;\n+\t\tgd->dram[1].size = DRAM_GAP_START - gd->dram[1].start;\n\n \t\tif (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) {\n-\t\t\tbd->bi_dram[2].start = DRAM_GAP_END;\n-\t\t\tbd->bi_dram[2].size = ram_top - bd->bi_dram[2].start;\n+\t\t\tgd->dram[2].start = DRAM_GAP_END;\n+\t\t\tgd->dram[2].size = ram_top - gd->dram[2].start;\n \t\t}\n \t}\n\ndiff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c\nindex ea0e3621af72..f0923186fa61 100644\n--- a/arch/arm/mach-rockchip/sdram.c\n+++ b/arch/arm/mach-rockchip/sdram.c\n@@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void)\n\n \t/*\n \t * Rockchip guaranteed DDR_MEM is ordered so no need to worry about\n-\t * bi_dram order.\n+\t * dram order.\n \t */\n \tfor (i = 0, j = 0; i < ddr_info->count; i++, j++) {\n \t\tphys_size_t size = ddr_info->bank[(i + ddr_info->count)];\n@@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void)\n \t\t\t\t * split the region in two, one for before the\n \t\t\t\t * reserved memory area and one for after.\n \t\t\t\t */\n-\t\t\t\tgd->bd->bi_dram[j].start = start_addr;\n-\t\t\t\tgd->bd->bi_dram[j].size = rsrv_start - start_addr;\n+\t\t\t\tgd->dram[j].start = start_addr;\n+\t\t\t\tgd->dram[j].size = rsrv_start - start_addr;\n\n \t\t\t\tj++;\n\n@@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void)\n \t\t\treturn -ENOMEM;\n \t\t}\n\n-\t\tgd->bd->bi_dram[j].start = start_addr;\n-\t\tgd->bd->bi_dram[j].size = size;\n+\t\tgd->dram[j].start = start_addr;\n+\t\tgd->dram[j].size = size;\n \t}\n\n \treturn 0;\n@@ -309,15 +309,15 @@ int dram_init_banksize(void)\n \t ret);\n\n \t/* Reserve 2M for ATF bl31 */\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;\n-\tgd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;\n+\tgd->dram[0].size = top - gd->dram[0].start;\n\n \t/* Add usable memory beyond the blob of space for peripheral near 4GB */\n \tif (ram_top > SZ_4G && top < SZ_4G) {\n-\t\tgd->bd->bi_dram[1].start = SZ_4G;\n-\t\tgd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;\n+\t\tgd->dram[1].start = SZ_4G;\n+\t\tgd->dram[1].size = ram_top - gd->dram[1].start;\n \t} else if (ram_top > SZ_4G && top == SZ_4G) {\n-\t\tgd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;\n+\t\tgd->dram[0].size = ram_top - gd->dram[0].start;\n \t}\n #else\n #ifdef CONFIG_SPL_OPTEE_IMAGE\n@@ -327,23 +327,23 @@ int dram_init_banksize(void)\n \t\t\tTRUST_PARAMETER_OFFSET);\n\n \tif (tos_parameter->tee_mem.flags == 1) {\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = tos_parameter->tee_mem.phy_addr\n \t\t\t\t\t- CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +\n+\t\tgd->dram[1].start = tos_parameter->tee_mem.phy_addr +\n \t\t\t\t\ttos_parameter->tee_mem.size;\n-\t\tgd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;\n+\t\tgd->dram[1].size = top - gd->dram[1].start;\n \t} else {\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x8400000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x8400000;\n \t\t/* Reserve 32M for OPTEE with TA */\n-\t\tgd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE\n-\t\t\t\t\t+ gd->bd->bi_dram[0].size + 0x2000000;\n-\t\tgd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;\n+\t\tgd->dram[1].start = CFG_SYS_SDRAM_BASE\n+\t\t\t\t\t+ gd->dram[0].size + 0x2000000;\n+\t\tgd->dram[1].size = top - gd->dram[1].start;\n \t}\n #else\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = top - gd->dram[0].start;\n #endif\n #endif\n\ndiff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\nindex 5fb3240acc5a..2a8e07ffdab5 100644\n--- a/arch/arm/mach-snapdragon/board.c\n+++ b/arch/arm/mach-snapdragon/board.c\n@@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2)\n }\n\n /* This has to be done post-relocation since gd->bd isn't preserved */\n-static void qcom_configure_bi_dram(void)\n+static void qcom_configure_dram(void)\n {\n \tint i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tgd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start;\n-\t\tgd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size;\n+\t\tgd->dram[i].start = prevbl_ddr_banks[i].start;\n+\t\tgd->dram[i].size = prevbl_ddr_banks[i].size;\n \t}\n }\n\n int dram_init_banksize(void)\n {\n-\tqcom_configure_bi_dram();\n+\tqcom_configure_dram();\n\n \treturn 0;\n }\n@@ -589,15 +589,15 @@ static void build_mem_map(void)\n \t */\n \tmem_map[0].phys = 0x1000;\n \tmem_map[0].virt = mem_map[0].phys;\n-\tmem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;\n+\tmem_map[0].size = gd->dram[0].start - mem_map[0].phys;\n \tmem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t\t\t PTE_BLOCK_NON_SHARE |\n \t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN;\n\n-\tfor (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) {\n-\t\tmem_map[i].phys = gd->bd->bi_dram[j].start;\n+\tfor (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) {\n+\t\tmem_map[i].phys = gd->dram[j].start;\n \t\tmem_map[i].virt = mem_map[i].phys;\n-\t\tmem_map[i].size = gd->bd->bi_dram[j].size;\n+\t\tmem_map[i].size = gd->dram[j].size;\n \t\tmem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \\\n \t\t\t\t PTE_BLOCK_INNER_SHARE;\n \t}\ndiff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c\nindex 4d7f0b9a79cb..b202ca258bc4 100644\n--- a/arch/arm/mach-socfpga/board.c\n+++ b/arch/arm/mach-socfpga/board.c\n@@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images)\n void lmb_arch_add_memory(void)\n {\n \tint i;\n-\tstruct bd_info *bd = gd->bd;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tif (bd->bi_dram[i].size)\n-\t\t\tlmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size);\n+\t\tif (gd->dram[i].size)\n+\t\t\tlmb_add(gd->dram[i].start, gd->dram[i].size);\n \t}\n }\n #endif\ndiff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c\nindex 7e0f3875b7cb..338f73d6e738 100644\n--- a/arch/arm/mach-socfpga/misc_arria10.c\n+++ b/arch/arm/mach-socfpga/misc_arria10.c\n@@ -246,7 +246,6 @@ int qspi_flash_software_reset(void)\n\n void dram_bank_mmu_setup(int bank)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tu32 start, size;\n \tint i;\n\n@@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank)\n \t * The default implementation of this function allows the DRAM dcache\n \t * to be enabled only after relocation. However, to speed up ECC\n \t * initialization, we want to be able to enable DRAM dcache before\n-\t * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram\n+\t * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram\n \t * is set first).\n \t */\n-\tstart = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;\n-\tsize = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;\n+\tstart = gd->dram[bank].start >> MMU_SECTION_SHIFT;\n+\tsize = gd->dram[bank].size >> MMU_SECTION_SHIFT;\n \tfor (i = start; i < start + size; i++)\n \t\tset_section_dcache(i, DCACHE_DEFAULT_OPTION);\n }\ndiff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c\nindex 835eaf48dfa5..76c324b55aeb 100644\n--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c\n+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c\n@@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data,\n \t\tdev->mtd = mtd;\n \t\tbreak;\n \tcase STM32PROG_RAM:\n-\t\tfirst_addr = gd->bd->bi_dram[0].start;\n-\t\tlast_addr = first_addr + gd->bd->bi_dram[0].size;\n+\t\tfirst_addr = gd->dram[0].start;\n+\t\tlast_addr = first_addr + gd->dram[0].size;\n \t\tdev->erase_size = 1;\n \t\tbreak;\n \tdefault:\ndiff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c\nindex 252aef1852ea..4d81c70b2300 100644\n--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c\n+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c\n@@ -52,7 +52,6 @@ u32 get_bootauth(void)\n */\n void dram_bank_mmu_setup(int bank)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tint\ti;\n \tphys_addr_t start;\n \tphys_addr_t addr;\n@@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank)\n \t\tsize = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);\n #endif\n \t} else if (gd->flags & GD_FLG_RELOC) {\n-\t\t/* bd->bi_dram is available only after relocation */\n-\t\tstart = bd->bi_dram[bank].start;\n-\t\tsize = bd->bi_dram[bank].size;\n+\t\t/* gd->dram is available only after relocation */\n+\t\tstart = gd->dram[bank].start;\n+\t\tsize = gd->dram[bank].size;\n \t\tuse_lmb = true;\n \t} else {\n \t\t/* mark cacheable and executable the beggining of the DDR */\ndiff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c\nindex 396851c5bd84..1763f95ace44 100644\n--- a/arch/arm/mach-tegra/board2.c\n+++ b/arch/arm/mach-tegra/board2.c\n@@ -393,18 +393,18 @@ int dram_init_banksize(void)\n\n \t/* fall back to default DRAM bank size computation */\n\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = usable_ram_size_below_4g();\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = usable_ram_size_below_4g();\n\n #ifdef CONFIG_PHYS_64BIT\n \tif (gd->ram_size > SZ_2G) {\n-\t\tgd->bd->bi_dram[1].start = 0x100000000;\n-\t\tgd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;\n+\t\tgd->dram[1].start = 0x100000000;\n+\t\tgd->dram[1].size = gd->ram_size - SZ_2G;\n \t} else\n #endif\n \t{\n-\t\tgd->bd->bi_dram[1].start = 0;\n-\t\tgd->bd->bi_dram[1].size = 0;\n+\t\tgd->dram[1].start = 0;\n+\t\tgd->dram[1].size = 0;\n \t}\n\n \treturn 0;\n@@ -418,7 +418,7 @@ int dram_init_banksize(void)\n * carve-out, as mentioned above.\n *\n * This function is called before dram_init_banksize(), so we can't simply\n- * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.\n+ * return gd->dram[1].start + gd->dram[1].size.\n */\n phys_addr_t board_get_usable_ram_top(phys_size_t total_size)\n {\ndiff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c\nindex e2342b2aece7..ff15fa28eb50 100644\n--- a/arch/arm/mach-tegra/cboot.c\n+++ b/arch/arm/mach-tegra/cboot.c\n@@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void)\n \t}\n\n \tfor (i = 0; i < ram_bank_count; i++) {\n-\t\tgd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;\n-\t\tgd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;\n+\t\tgd->dram[i].start = tegra_mem_map[1 + i].virt;\n+\t\tgd->dram[i].size = tegra_mem_map[1 + i].size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c\nindex 0e1164a2680f..ae495808dec9 100644\n--- a/arch/arm/mach-uniphier/dram_init.c\n+++ b/arch/arm/mach-uniphier/dram_init.c\n@@ -280,9 +280,9 @@ int dram_init_banksize(void)\n \t\treturn ret;\n\n \tfor (i = 0; i < ARRAY_SIZE(dram_map); i++) {\n-\t\tif (i < ARRAY_SIZE(gd->bd->bi_dram)) {\n-\t\t\tgd->bd->bi_dram[i].start = dram_map[i].base;\n-\t\t\tgd->bd->bi_dram[i].size = dram_map[i].size;\n+\t\tif (i < ARRAY_SIZE(gd->dram)) {\n+\t\t\tgd->dram[i].start = dram_map[i].base;\n+\t\t\tgd->dram[i].size = dram_map[i].size;\n \t\t}\n\n \t\tif (!dram_map[i].size)\ndiff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c\nindex dfa32fdd48b3..4e1de15cd98f 100644\n--- a/arch/arm/mach-uniphier/fdt-fixup.c\n+++ b/arch/arm/mach-uniphier/fdt-fixup.c\n@@ -4,6 +4,7 @@\n * Author: Masahiro Yamada <yamada.masahiro@socionext.com>\n */\n\n+#include <asm/global_data.h>\n #include <fdt_support.h>\n #include <fdtdec.h>\n #include <jffs2/load_kernel.h>\n@@ -20,6 +21,7 @@\n */\n static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd)\n {\n+\tDECLARE_GLOBAL_DATA_PTR;\n \tunsigned long rsv_addr;\n \tconst unsigned long rsv_size = 64;\n \tint i, ret;\n@@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd)\n \t uniphier_get_soc_id() != UNIPHIER_LD20_ID)\n \t\treturn 0;\n\n-\tfor (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) {\n-\t\tif (!bd->bi_dram[i].size)\n+\tfor (i = 0; i < ARRAY_SIZE(gd->dram); i++) {\n+\t\tif (!gd->dram[i].size)\n \t\t\tcontinue;\n\n-\t\trsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size;\n+\t\trsv_addr = gd->dram[i].start + gd->dram[i].size;\n \t\trsv_addr -= rsv_size;\n\n \t\tret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);\ndiff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c\nindex d088e440f638..78ead1f45f69 100644\n--- a/arch/arm/mach-versal-net/cpu.c\n+++ b/arch/arm/mach-versal-net/cpu.c\n@@ -69,12 +69,12 @@ void mem_map_fill(void)\n\n \tfor (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n \t\t/* Zero size means no more DDR that's this is end */\n-\t\tif (!gd->bd->bi_dram[i].size)\n+\t\tif (!gd->dram[i].size)\n \t\t\tbreak;\n\n-\t\tversal_mem_map[banks].virt = gd->bd->bi_dram[i].start;\n-\t\tversal_mem_map[banks].phys = gd->bd->bi_dram[i].start;\n-\t\tversal_mem_map[banks].size = gd->bd->bi_dram[i].size;\n+\t\tversal_mem_map[banks].virt = gd->dram[i].start;\n+\t\tversal_mem_map[banks].phys = gd->dram[i].start;\n+\t\tversal_mem_map[banks].size = gd->dram[i].size;\n \t\tversal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n \t\t\t\t\t PTE_BLOCK_INNER_SHARE;\n \t\tbanks = banks + 1;\ndiff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c\nindex 363ce3007fd1..0dd5cc153c47 100644\n--- a/arch/arm/mach-versal/cpu.c\n+++ b/arch/arm/mach-versal/cpu.c\n@@ -82,21 +82,21 @@ void mem_map_fill(void)\n\n \tfor (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n \t\t/* Zero size means no more DDR that's this is end */\n-\t\tif (!gd->bd->bi_dram[i].size)\n+\t\tif (!gd->dram[i].size)\n \t\t\tbreak;\n\n #if defined(CONFIG_VERSAL_NO_DDR)\n-\t\tif (gd->bd->bi_dram[i].start < 0x80000000UL ||\n-\t\t gd->bd->bi_dram[i].start > 0x100000000UL) {\n+\t\tif (gd->dram[i].start < 0x80000000UL ||\n+\t\t gd->dram[i].start > 0x100000000UL) {\n \t\t\tprintf(\"Ignore caches over %llx/%llx\\n\",\n-\t\t\t gd->bd->bi_dram[i].start,\n-\t\t\t gd->bd->bi_dram[i].size);\n+\t\t\t gd->dram[i].start,\n+\t\t\t gd->dram[i].size);\n \t\t\tcontinue;\n \t\t}\n #endif\n-\t\tversal_mem_map[banks].virt = gd->bd->bi_dram[i].start;\n-\t\tversal_mem_map[banks].phys = gd->bd->bi_dram[i].start;\n-\t\tversal_mem_map[banks].size = gd->bd->bi_dram[i].size;\n+\t\tversal_mem_map[banks].virt = gd->dram[i].start;\n+\t\tversal_mem_map[banks].phys = gd->dram[i].start;\n+\t\tversal_mem_map[banks].size = gd->dram[i].size;\n \t\tversal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n \t\t\t\t\t PTE_BLOCK_INNER_SHARE;\n \t\tbanks = banks + 1;\ndiff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c\nindex a81609cdec7f..f65c231bdab7 100644\n--- a/arch/arm/mach-versal2/cpu.c\n+++ b/arch/arm/mach-versal2/cpu.c\n@@ -109,7 +109,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks)\n * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info\n *\n * Transfers DRAM bank information from the global versal2_mem_map[]\n- * array to bd->bi_dram[] for passing memory configuration to the\n+ * array to gd->dram[] for passing memory configuration to the\n * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical\n * address and size are copied.\n *\n@@ -119,15 +119,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks)\n */\n void fill_bd_mem_info(void)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tint banks = VERSAL2_MEM_MAP_USED;\n\n \tfor (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n \t\tif (!versal2_mem_map[banks].size)\n \t\t\tbreak;\n\n-\t\tbd->bi_dram[i].start = versal2_mem_map[banks].phys;\n-\t\tbd->bi_dram[i].size = versal2_mem_map[banks].size;\n+\t\tgd->dram[i].start = versal2_mem_map[banks].phys;\n+\t\tgd->dram[i].size = versal2_mem_map[banks].size;\n \t\tbanks++;\n \t}\n }\ndiff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c\nindex 5f194aaff9a4..3dc47e5d48e4 100644\n--- a/arch/arm/mach-zynqmp/cpu.c\n+++ b/arch/arm/mach-zynqmp/cpu.c\n@@ -92,12 +92,12 @@ void mem_map_fill(void)\n #if !defined(CONFIG_ZYNQMP_NO_DDR)\n \tfor (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n \t\t/* Zero size means no more DDR that's this is end */\n-\t\tif (!gd->bd->bi_dram[i].size)\n+\t\tif (!gd->dram[i].size)\n \t\t\tbreak;\n\n-\t\tzynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;\n-\t\tzynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;\n-\t\tzynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;\n+\t\tzynqmp_mem_map[banks].virt = gd->dram[i].start;\n+\t\tzynqmp_mem_map[banks].phys = gd->dram[i].start;\n+\t\tzynqmp_mem_map[banks].size = gd->dram[i].size;\n \t\tzynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n \t\t\t\t\t PTE_BLOCK_INNER_SHARE;\n \t\tbanks = banks + 1;\ndiff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c\nindex 5b1311d8b5b9..817728aa5698 100644\n--- a/arch/mips/mach-octeon/dram.c\n+++ b/arch/mips/mach-octeon/dram.c\n@@ -41,8 +41,8 @@ int dram_init(void)\n \t\t * No DDR init yet -> run in L2 cache\n \t\t */\n \t\tgd->ram_size = (4 << 20);\n-\t\tgd->bd->bi_dram[0].size = gd->ram_size;\n-\t\tgd->bd->bi_dram[1].size = 0;\n+\t\tgd->dram[0].size = gd->ram_size;\n+\t\tgd->dram[1].size = 0;\n \t}\n\n \treturn 0;\ndiff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c\nindex cc1e903c9dd6..2893bc6b99a4 100644\n--- a/arch/riscv/cpu/k1/dram.c\n+++ b/arch/riscv/cpu/k1/dram.c\n@@ -56,12 +56,12 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);\n\n \tif (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) {\n-\t\tgd->bd->bi_dram[1].start = 0x100000000;\n-\t\tgd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;\n+\t\tgd->dram[1].start = 0x100000000;\n+\t\tgd->dram[1].size = gd->ram_size - SZ_2G;\n \t}\n\n \treturn 0;\n@@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tint i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tstart[i] = gd->bd->bi_dram[i].start;\n-\t\tsize[i] = gd->bd->bi_dram[i].size;\n+\t\tstart[i] = gd->dram[i].start;\n+\t\tsize[i] = gd->dram[i].size;\n \t}\n\n \treturn fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);\ndiff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c\nindex 7ee4975523e3..d00007a9440a 100644\n--- a/arch/sandbox/cpu/spl.c\n+++ b/arch/sandbox/cpu/spl.c\n@@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD(\"sandbox_image\", 7, BOOT_DEVICE_BOARD, load_from_image);\n int dram_init_banksize(void)\n {\n \t/* These are necessary so TFTP can use LMBs to check its load address */\n-\tgd->bd->bi_dram[0].start = gd->ram_base;\n-\tgd->bd->bi_dram[0].size = get_effective_memsize();\n+\tgd->dram[0].start = gd->ram_base;\n+\tgd->dram[0].size = get_effective_memsize();\n\n \treturn 0;\n }\ndiff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c\nindex cc1edd7badd8..81604ee12fbc 100644\n--- a/arch/x86/cpu/coreboot/sdram.c\n+++ b/arch/x86/cpu/coreboot/sdram.c\n@@ -91,8 +91,8 @@ int dram_init_banksize(void)\n \t\t\tstruct memrange *memrange = &lib_sysinfo.memrange[i];\n\n \t\t\tif (memrange->type == CB_MEM_RAM) {\n-\t\t\t\tgd->bd->bi_dram[j].start = memrange->base;\n-\t\t\t\tgd->bd->bi_dram[j].size = memrange->size;\n+\t\t\t\tgd->dram[j].start = memrange->base;\n+\t\t\t\tgd->dram[j].size = memrange->size;\n \t\t\t\tj++;\n \t\t\t\tif (j >= CONFIG_NR_DRAM_BANKS)\n \t\t\t\t\tbreak;\ndiff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c\nindex 6845ce72ff94..b86d50b2cab7 100644\n--- a/arch/x86/cpu/efi/payload.c\n+++ b/arch/x86/cpu/efi/payload.c\n@@ -123,8 +123,8 @@ int dram_init_banksize(void)\n \t\tif (desc->type != EFI_CONVENTIONAL_MEMORY ||\n \t\t (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20)\n \t\t\tcontinue;\n-\t\tgd->bd->bi_dram[num_banks].start = desc->physical_start;\n-\t\tgd->bd->bi_dram[num_banks].size = desc->num_pages <<\n+\t\tgd->dram[num_banks].start = desc->physical_start;\n+\t\tgd->dram[num_banks].size = desc->num_pages <<\n \t\t\tEFI_PAGE_SHIFT;\n \t\tnum_banks++;\n \t}\ndiff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c\nindex 6fe400711402..e09fce8bb1b8 100644\n--- a/arch/x86/cpu/efi/sdram.c\n+++ b/arch/x86/cpu/efi/sdram.c\n@@ -24,8 +24,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = efi_get_ram_base();\n-\tgd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;\n+\tgd->dram[0].start = efi_get_ram_base();\n+\tgd->dram[0].size = CONFIG_EFI_RAM_SIZE;\n\n \treturn 0;\n }\ndiff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c\nindex baa1f0e32d6b..11ce97b51435 100644\n--- a/arch/x86/cpu/intel_common/mrc.c\n+++ b/arch/x86/cpu/intel_common/mrc.c\n@@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void)\n\n \t\tif (area->start >= 1ULL << 32)\n \t\t\tcontinue;\n-\t\tgd->bd->bi_dram[num_banks].start = area->start;\n-\t\tgd->bd->bi_dram[num_banks].size = area->size;\n+\t\tgd->dram[num_banks].start = area->start;\n+\t\tgd->dram[num_banks].size = area->size;\n \t\tnum_banks++;\n \t}\n }\ndiff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c\nindex d20c9a2a379f..a5e81dfada5f 100644\n--- a/arch/x86/cpu/ivybridge/sdram_nop.c\n+++ b/arch/x86/cpu/ivybridge/sdram_nop.c\n@@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR;\n int dram_init(void)\n {\n \tgd->ram_size = 1ULL << 31;\n-\tgd->bd->bi_dram[0].start = 0;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = 0;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c\nindex ba3638e6acc6..3cba04f2c3e0 100644\n--- a/arch/x86/cpu/qemu/dram.c\n+++ b/arch/x86/cpu/qemu/dram.c\n@@ -69,13 +69,13 @@ int dram_init_banksize(void)\n {\n \tu64 high_mem_size;\n\n-\tgd->bd->bi_dram[0].start = 0;\n-\tgd->bd->bi_dram[0].size = qemu_get_low_memory_size();\n+\tgd->dram[0].start = 0;\n+\tgd->dram[0].size = qemu_get_low_memory_size();\n\n \thigh_mem_size = qemu_get_high_memory_size();\n \tif (high_mem_size) {\n-\t\tgd->bd->bi_dram[1].start = SZ_4G;\n-\t\tgd->bd->bi_dram[1].size = high_mem_size;\n+\t\tgd->dram[1].start = SZ_4G;\n+\t\tgd->dram[1].size = high_mem_size;\n \t}\n\n \treturn 0;\ndiff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c\nindex 34e576940d4f..34fdb7e026a5 100644\n--- a/arch/x86/cpu/quark/dram.c\n+++ b/arch/x86/cpu/quark/dram.c\n@@ -169,8 +169,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = 0;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = 0;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c\nindex 75ca5273625c..5aa4f6d3e070 100644\n--- a/arch/x86/cpu/slimbootloader/sdram.c\n+++ b/arch/x86/cpu/slimbootloader/sdram.c\n@@ -129,8 +129,8 @@ int dram_init_banksize(void)\n \t\treturn 0;\n\n \t/* simply use a single bank to have whole size for now */\n-\tgd->bd->bi_dram[0].start = 0;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = 0;\n+\tgd->dram[0].size = gd->ram_size;\n \treturn 0;\n }\n\ndiff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c\nindex 6192f2296b80..6ce96b0569b3 100644\n--- a/arch/x86/cpu/tangier/sdram.c\n+++ b/arch/x86/cpu/tangier/sdram.c\n@@ -160,8 +160,8 @@ static int sfi_get_bank_size(void)\n \t\tif (mentry->type != SFI_MEM_CONV)\n \t\t\tcontinue;\n\n-\t\tgd->bd->bi_dram[bank].start = mentry->phys_start;\n-\t\tgd->bd->bi_dram[bank].size = mentry->pages << 12;\n+\t\tgd->dram[bank].start = mentry->phys_start;\n+\t\tgd->dram[bank].size = mentry->pages << 12;\n \t\tbank++;\n \t}\n\ndiff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c\nindex cde4fbf35574..e054f42fa863 100644\n--- a/arch/x86/lib/bootm.c\n+++ b/arch/x86/lib/bootm.c\n@@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void)\n #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)\n int arch_fixup_memory_node(void *blob)\n {\n-\tstruct bd_info\t*bd = gd->bd;\n \tint bank;\n \tu64 start[CONFIG_NR_DRAM_BANKS];\n \tu64 size[CONFIG_NR_DRAM_BANKS];\n\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart[bank] = bd->bi_dram[bank].start;\n-\t\tsize[bank] = bd->bi_dram[bank].size;\n+\t\tstart[bank] = gd->dram[bank].start;\n+\t\tsize[bank] = gd->dram[bank].size;\n \t}\n\n \treturn fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);\ndiff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c\nindex 730721dc1768..a45e4060ef25 100644\n--- a/arch/x86/lib/fsp/fsp_dram.c\n+++ b/arch/x86/lib/fsp/fsp_dram.c\n@@ -64,8 +64,8 @@ int dram_init_banksize(void)\n \tupdate_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);\n\n \tif (!ll_boot_init()) {\n-\t\tgd->bd->bi_dram[0].start = 0;\n-\t\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\t\tgd->dram[0].start = 0;\n+\t\tgd->dram[0].size = gd->ram_size;\n\n \t\tif (update_mtrr)\n \t\t\tmtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);\n@@ -89,21 +89,21 @@ int dram_init_banksize(void)\n \t\t\tmtrr_top = max(mtrr_top,\n \t\t\t\t res_desc->phys_start + res_desc->len);\n \t\t} else {\n-\t\t\tgd->bd->bi_dram[bank].start = res_desc->phys_start;\n-\t\t\tgd->bd->bi_dram[bank].size = res_desc->len;\n+\t\t\tgd->dram[bank].start = res_desc->phys_start;\n+\t\t\tgd->dram[bank].size = res_desc->len;\n \t\t\tif (update_mtrr)\n \t\t\t\tmtrr_add_request(MTRR_TYPE_WRBACK,\n \t\t\t\t\t\t res_desc->phys_start,\n \t\t\t\t\t\t res_desc->len);\n \t\t\tlog_debug(\"ram %llx %llx\\n\",\n-\t\t\t\t gd->bd->bi_dram[bank].start,\n-\t\t\t\t gd->bd->bi_dram[bank].size);\n+\t\t\t\t gd->dram[bank].start,\n+\t\t\t\t gd->dram[bank].size);\n \t\t}\n \t}\n\n \t/* Add the memory below 4GB */\n-\tgd->bd->bi_dram[0].start = 0;\n-\tgd->bd->bi_dram[0].size = low_end;\n+\tgd->dram[0].start = 0;\n+\tgd->dram[0].size = low_end;\n\n \t/*\n \t * Set up an MTRR to the top of low, reserved memory. This is necessary\n@@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries,\n #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)\n int handoff_arch_save(struct spl_handoff *ho)\n {\n-\tho->arch.usable_ram_top = gd->bd->bi_dram[0].size;\n+\tho->arch.usable_ram_top = gd->dram[0].size;\n \tho->arch.hob_list = gd->arch.hob_list;\n\n \treturn 0;\ndiff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c\nindex 2f9557a4170f..32535ed6ee0e 100644\n--- a/board/CZ.NIC/turris_1x/turris_1x.c\n+++ b/board/CZ.NIC/turris_1x/turris_1x.c\n@@ -42,9 +42,9 @@ int dram_init_banksize(void)\n\n \tstatic_assert(CONFIG_NR_DRAM_BANKS >= 3);\n\n-\tgd->bd->bi_dram[0].start = gd->ram_base;\n-\tgd->bd->bi_dram[0].size = get_effective_memsize();\n-\tsize -= gd->bd->bi_dram[0].size;\n+\tgd->dram[0].start = gd->ram_base;\n+\tgd->dram[0].size = get_effective_memsize();\n+\tsize -= gd->dram[0].size;\n\n \t/* Note: This address space is not mapped via TLB entries in U-Boot */\n\n@@ -68,16 +68,16 @@ int dram_init_banksize(void)\n\n \tif (size > 0) {\n \t\t/* Free space between PCIe bus 3 MEM and NOR */\n-\t\tgd->bd->bi_dram[1].start = 0xc0200000;\n-\t\tgd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start);\n-\t\tsize -= gd->bd->bi_dram[1].size;\n+\t\tgd->dram[1].start = 0xc0200000;\n+\t\tgd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start);\n+\t\tsize -= gd->dram[1].size;\n \t}\n\n \tif (size > 0) {\n \t\t/* Free space between NOR and NAND */\n-\t\tgd->bd->bi_dram[2].start = 0xf0000000;\n-\t\tgd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start);\n-\t\tsize -= gd->bd->bi_dram[2].size;\n+\t\tgd->dram[2].start = 0xf0000000;\n+\t\tgd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start);\n+\t\tsize -= gd->dram[2].size;\n \t}\n #else\n \tputs(\"\\n\\n!!! TODO: fix sdcard >2GB RAM\\n\\n\\n\");\n@@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd)\n\n \tif (!env_get(\"bootm_low\") && !env_get(\"bootm_size\")) {\n \t\tfor (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) {\n-\t\t\tstart[count] = gd->bd->bi_dram[count].start;\n-\t\t\tsize[count] = gd->bd->bi_dram[count].size;\n+\t\t\tstart[count] = gd->dram[count].start;\n+\t\t\tsize[count] = gd->dram[count].size;\n \t\t\tif (!size[count])\n \t\t\t\tbreak;\n \t\t}\n@@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void)\n \tsize = gd->ram_size;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)\n-\t\tsize -= gd->bd->bi_dram[i].size;\n+\t\tsize -= gd->dram[i].size;\n\n \tif (size == 0)\n \t\treturn;\n\n \te = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3);\n-\tif (e.index < 0 && gd->bd->bi_dram[1].size > 0) {\n+\tif (e.index < 0 && gd->dram[1].size > 0) {\n \t\t/*\n \t\t * If there is no LAW for PCIe 3 MEM then 3rd PCIe controller\n \t\t * is inactive, which is the case for Turris 1.0 boards. So\n@@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void)\n \t\tprintf(\"Reserving unused \");\n \t\tprint_size(bank_size, \"\");\n \t\tprintf(\" of PCIe 3 MEM for DDR RAM\\n\");\n-\t\tgd->bd->bi_dram[1].start -= bank_size;\n-\t\tgd->bd->bi_dram[1].size += bank_size;\n+\t\tgd->dram[1].start -= bank_size;\n+\t\tgd->dram[1].size += bank_size;\n \t\tsize -= bank_size;\n \t\tif (size == 0)\n \t\t\treturn;\n@@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void)\n \t\tprintf(\"Reserving unused \");\n \t\tprint_size(free_size2, \"\");\n \t\tprintf(\" of PCIe 2 MEM for DDR RAM\\n\");\n-\t\tgd->bd->bi_dram[i].start = free_start2;\n-\t\tgd->bd->bi_dram[i].size = min(size, free_size2);\n-\t\tsize -= gd->bd->bi_dram[i].start;\n+\t\tgd->dram[i].start = free_start2;\n+\t\tgd->dram[i].size = min(size, free_size2);\n+\t\tsize -= gd->dram[i].start;\n \t\ti++;\n \t\tif (size == 0)\n \t\t\treturn;\n@@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void)\n \t\tprintf(\"Reserving unused \");\n \t\tprint_size(free_size1, \"\");\n \t\tprintf(\" of PCIe 1 MEM for DDR RAM\\n\");\n-\t\tgd->bd->bi_dram[i].start = free_start1;\n-\t\tgd->bd->bi_dram[i].size = min(size, free_size1);\n-\t\tsize -= gd->bd->bi_dram[i].size;\n+\t\tgd->dram[i].start = free_start1;\n+\t\tgd->dram[i].size = min(size, free_size1);\n+\t\tsize -= gd->dram[i].size;\n \t\ti++;\n \t\tif (size == 0)\n \t\t\treturn;\ndiff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c\nindex 16d0e679c3e2..eb0f9c068491 100644\n--- a/board/armltd/corstone1000/corstone1000.c\n+++ b/board/armltd/corstone1000/corstone1000.c\n@@ -86,8 +86,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = PHYS_SDRAM_1_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c\nindex eaf87e3bfe30..6cd24bf25fbc 100644\n--- a/board/armltd/integrator/integrator.c\n+++ b/board/armltd/integrator/integrator.c\n@@ -137,7 +137,7 @@ int misc_init_r (void)\n\n int dram_init (void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n #ifdef CONFIG_CM_SPD_DETECT\n \t{\n extern void dram_query(void);\n@@ -170,7 +170,7 @@ extern void dram_query(void);\n \t\t\t\t PHYS_SDRAM_1_SIZE);\n #endif /* CM_SPD_DETECT */\n \t/* We only have one bank of RAM, set it to whatever was detected */\n-\tgd->bd->bi_dram[0].size\t = gd->ram_size;\n+\tgd->dram[0].size\t = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c\nindex 12bb6defab25..057e916ab1b7 100644\n--- a/board/armltd/total_compute/total_compute.c\n+++ b/board/armltd/total_compute/total_compute.c\n@@ -89,9 +89,9 @@ void build_mem_map(void)\n \t\t * The first node is for I/O device, start from node 1 for\n \t\t * updating DRAM info.\n \t\t */\n-\t\tmem_map[i + 1].virt = gd->bd->bi_dram[i].start;\n-\t\tmem_map[i + 1].phys = gd->bd->bi_dram[i].start;\n-\t\tmem_map[i + 1].size = gd->bd->bi_dram[i].size;\n+\t\tmem_map[i + 1].virt = gd->dram[i].start;\n+\t\tmem_map[i + 1].phys = gd->dram[i].start;\n+\t\tmem_map[i + 1].size = gd->dram[i].size;\n \t\tmem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n \t\t\t\t PTE_BLOCK_INNER_SHARE;\n \t}\ndiff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c\nindex 3833af59b09a..87e53f64e064 100644\n--- a/board/armltd/vexpress/vexpress_common.c\n+++ b/board/armltd/vexpress/vexpress_common.c\n@@ -79,11 +79,11 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size =\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size =\n \t\t\tget_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_2;\n-\tgd->bd->bi_dram[1].size =\n+\tgd->dram[1].start = PHYS_SDRAM_2;\n+\tgd->dram[1].size =\n \t\t\tget_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);\n\n \treturn 0;\ndiff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c\nindex 771888205814..7cb492b2da68 100644\n--- a/board/atmel/common/video_display.c\n+++ b/board/atmel/common/video_display.c\n@@ -40,7 +40,7 @@ int at91_video_show_board_info(void)\n\n \tdram_size = 0;\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)\n-\t\tdram_size += gd->bd->bi_dram[i].size;\n+\t\tdram_size += gd->dram[i].size;\n\n \tnand_size = 0;\n #ifdef CONFIG_NAND_ATMEL\ndiff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c\nindex 3393478e4c8c..be557721a8a1 100644\n--- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c\n+++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c\n@@ -71,7 +71,7 @@ int misc_init_r(void)\n int board_init(void)\n {\n \t/* address of boot parameters */\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \tboard_leds_init();\n\ndiff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c\nindex 4e7c5667e214..1d5c95a6f925 100644\n--- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c\n+++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c\n@@ -50,7 +50,7 @@ int board_early_init_f(void)\n int board_init(void)\n {\n \t/* address of boot parameters */\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \treturn 0;\n }\ndiff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c\nindex bf54fc33df4b..e7a9a0f82e91 100644\n--- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c\n+++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c\n@@ -71,7 +71,7 @@ int board_early_init_f(void)\n int board_init(void)\n {\n \t/* address of boot parameters */\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \trgb_leds_init();\n\ndiff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c\nindex 897fab58ebae..2908efe1fd00 100644\n--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c\n+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c\n@@ -65,7 +65,7 @@ int board_early_init_f(void)\n int board_init(void)\n {\n \t/* address of boot parameters */\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \trgb_leds_init();\n\ndiff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c\nindex 8759ff6f01ac..1a17db1bd5bb 100644\n--- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c\n+++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c\n@@ -65,7 +65,7 @@ int board_early_init_f(void)\n int board_init(void)\n {\n \t/* address of boot parameters */\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \trgb_leds_init();\n\ndiff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c\nindex eca5b2bf1076..d493a68581cd 100644\n--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c\n+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c\n@@ -70,7 +70,7 @@ int board_early_init_f(void)\n int board_init(void)\n {\n \t/* address of boot parameters */\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \trgb_leds_init();\n\ndiff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c\nindex 713b1b9d9591..aaf84e609672 100644\n--- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c\n+++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c\n@@ -57,7 +57,7 @@ int board_early_init_f(void)\n int board_init(void)\n {\n \t/* address of boot parameters */\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \tboard_leds_init();\n\ndiff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c\nindex b05c9754c964..02543d8e99fd 100644\n--- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c\n+++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c\n@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;\n int board_init(void)\n {\n \t// Address of boot parameters\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \treturn 0;\n }\ndiff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c\nindex bb2f1e4f62ad..2683f46f41c6 100644\n--- a/board/broadcom/bcmns3/ns3.c\n+++ b/board/broadcom/bcmns3/ns3.c\n@@ -176,8 +176,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);\n-\tgd->bd->bi_dram[0].size = SZ_16M;\n+\tgd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M);\n+\tgd->dram[0].size = SZ_16M;\n\n \treturn 0;\n }\ndiff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c\nindex 40047cf67830..01ebb0a57cc0 100644\n--- a/board/compulab/cm_fx6/cm_fx6.c\n+++ b/board/compulab/cm_fx6/cm_fx6.c\n@@ -666,34 +666,34 @@ int misc_init_r(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_2;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[1].start = PHYS_SDRAM_2;\n\n \tswitch (gd->ram_size) {\n \tcase 0x10000000: /* DDR_16BIT_256MB */\n-\t\tgd->bd->bi_dram[0].size = 0x10000000;\n-\t\tgd->bd->bi_dram[1].size = 0;\n+\t\tgd->dram[0].size = 0x10000000;\n+\t\tgd->dram[1].size = 0;\n \t\tbreak;\n \tcase 0x20000000: /* DDR_32BIT_512MB */\n-\t\tgd->bd->bi_dram[0].size = 0x20000000;\n-\t\tgd->bd->bi_dram[1].size = 0;\n+\t\tgd->dram[0].size = 0x20000000;\n+\t\tgd->dram[1].size = 0;\n \t\tbreak;\n \tcase 0x40000000:\n \t\tif (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */\n-\t\t\tgd->bd->bi_dram[0].size = 0x20000000;\n-\t\t\tgd->bd->bi_dram[1].size = 0x20000000;\n+\t\t\tgd->dram[0].size = 0x20000000;\n+\t\t\tgd->dram[1].size = 0x20000000;\n \t\t} else { /* DDR_64BIT_1GB */\n-\t\t\tgd->bd->bi_dram[0].size = 0x40000000;\n-\t\t\tgd->bd->bi_dram[1].size = 0;\n+\t\t\tgd->dram[0].size = 0x40000000;\n+\t\t\tgd->dram[1].size = 0;\n \t\t}\n \t\tbreak;\n \tcase 0x80000000: /* DDR_64BIT_2GB */\n-\t\tgd->bd->bi_dram[0].size = 0x40000000;\n-\t\tgd->bd->bi_dram[1].size = 0x40000000;\n+\t\tgd->dram[0].size = 0x40000000;\n+\t\tgd->dram[1].size = 0x40000000;\n \t\tbreak;\n \tcase 0xEFF00000: /* DDR_64BIT_4GB */\n-\t\tgd->bd->bi_dram[0].size = 0x70000000;\n-\t\tgd->bd->bi_dram[1].size = 0x7FF00000;\n+\t\tgd->dram[0].size = 0x70000000;\n+\t\tgd->dram[1].size = 0x7FF00000;\n \t\tbreak;\n \t}\n\ndiff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c\nindex 9fea4f86d5aa..33f7ec6d048e 100644\n--- a/board/elgin/elgin_rv1108/elgin_rv1108.c\n+++ b/board/elgin/elgin_rv1108/elgin_rv1108.c\n@@ -66,8 +66,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = 0x60000000;\n-\tgd->bd->bi_dram[0].size = 0x8000000;\n+\tgd->dram[0].start = 0x60000000;\n+\tgd->dram[0].size = 0x8000000;\n\n \treturn 0;\n }\ndiff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c\nindex dce69abdfd1d..3d76c9360732 100644\n--- a/board/esd/meesc/meesc.c\n+++ b/board/esd/meesc/meesc.c\n@@ -141,8 +141,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM;\n+\tgd->dram[0].size = PHYS_SDRAM_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c\nindex eb10cd5143d1..5e560a7f9275 100644\n--- a/board/friendlyarm/nanopi2/board.c\n+++ b/board/friendlyarm/nanopi2/board.c\n@@ -532,17 +532,17 @@ int dram_init_banksize(void)\n \t/* set global data memory */\n \tgd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;\n\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = CFG_SYS_SDRAM_SIZE;\n\n \t/* Number of Row: 14 bits */\n \tif ((reg_val >> 28) == 14)\n-\t\tgd->bd->bi_dram[0].size -= 0x20000000;\n+\t\tgd->dram[0].size -= 0x20000000;\n\n \t/* Number of Memory Chips */\n \tif ((reg_val & 0x3) > 1) {\n-\t\tgd->bd->bi_dram[1].start = 0x80000000;\n-\t\tgd->bd->bi_dram[1].size = 0x40000000;\n+\t\tgd->dram[1].start = 0x80000000;\n+\t\tgd->dram[1].size = 0x40000000;\n \t}\n \treturn 0;\n }\ndiff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c\nindex cb9b88a1a58e..d3a385bf6b7c 100644\n--- a/board/ge/mx53ppd/mx53ppd.c\n+++ b/board/ge/mx53ppd/mx53ppd.c\n@@ -71,11 +71,11 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = mx53_dram_size[0];\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = mx53_dram_size[0];\n\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_2;\n-\tgd->bd->bi_dram[1].size = mx53_dram_size[1];\n+\tgd->dram[1].start = PHYS_SDRAM_2;\n+\tgd->dram[1].size = mx53_dram_size[1];\n\n \treturn 0;\n }\ndiff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c\nindex 5e60ab9d7b71..ba0465cf96f6 100644\n--- a/board/hisilicon/hikey/hikey.c\n+++ b/board/hisilicon/hikey/hikey.c\n@@ -456,23 +456,23 @@ int dram_init_banksize(void)\n \t * 0x3e00,0000 - 0x3fff,ffff: OP-TEE\n \t*/\n\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = 0x05e00000;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = 0x05e00000;\n\n-\tgd->bd->bi_dram[1].start = 0x05f00000;\n-\tgd->bd->bi_dram[1].size = 0x00001000;\n+\tgd->dram[1].start = 0x05f00000;\n+\tgd->dram[1].size = 0x00001000;\n\n-\tgd->bd->bi_dram[2].start = 0x05f02000;\n-\tgd->bd->bi_dram[2].size = 0x00efd000;\n+\tgd->dram[2].start = 0x05f02000;\n+\tgd->dram[2].size = 0x00efd000;\n\n-\tgd->bd->bi_dram[3].start = 0x06e00000;\n-\tgd->bd->bi_dram[3].size = 0x0060f000;\n+\tgd->dram[3].start = 0x06e00000;\n+\tgd->dram[3].size = 0x0060f000;\n\n-\tgd->bd->bi_dram[4].start = 0x07410000;\n-\tgd->bd->bi_dram[4].size = 0x1aaf0000;\n+\tgd->dram[4].start = 0x07410000;\n+\tgd->dram[4].size = 0x1aaf0000;\n\n-\tgd->bd->bi_dram[5].start = 0x22000000;\n-\tgd->bd->bi_dram[5].size = 0x1c000000;\n+\tgd->dram[5].start = 0x22000000;\n+\tgd->dram[5].size = 0x1c000000;\n\n \treturn 0;\n }\ndiff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c\nindex fb56762fff68..e7908d4c0480 100644\n--- a/board/hisilicon/hikey960/hikey960.c\n+++ b/board/hisilicon/hikey960/hikey960.c\n@@ -74,8 +74,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c\nindex c3ea080ff75a..dbab67d6f651 100644\n--- a/board/hisilicon/poplar/poplar.c\n+++ b/board/hisilicon/poplar/poplar.c\n@@ -87,8 +87,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;\n-\tgd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;\n+\tgd->dram[0].start = KERNEL_TEXT_OFFSET;\n+\tgd->dram[0].size = gd->ram_size - gd->dram[0].start;\n\n \treturn 0;\n }\ndiff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c\nindex efb7b49cbe08..07668bae7a9d 100644\n--- a/board/k+p/kp_imx53/kp_imx53.c\n+++ b/board/k+p/kp_imx53/kp_imx53.c\n@@ -39,8 +39,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = PHYS_SDRAM_1_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c\nindex 51938a1b4d88..e37d4e767dbf 100644\n--- a/board/keymile/pg-wcom-ls102xa/ddr.c\n+++ b/board/keymile/pg-wcom-ls102xa/ddr.c\n@@ -84,8 +84,8 @@ int fsl_initdram(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c\nindex 8a9502037fb6..ce778bc0849a 100644\n--- a/board/kontron/sl28/sl28.c\n+++ b/board/kontron/sl28/sl28.c\n@@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n\n \t/* fixup DT for the two GPP DDR banks */\n \tfor (i = 0; i < nbanks; i++) {\n-\t\tbase[i] = gd->bd->bi_dram[i].start;\n-\t\tsize[i] = gd->bd->bi_dram[i].size;\n+\t\tbase[i] = gd->dram[i].start;\n+\t\tsize[i] = gd->dram[i].size;\n \t}\n\n \tfdt_fixup_memory_banks(blob, base, size, nbanks);\ndiff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c\nindex 0710316a48bc..cc741dea5048 100644\n--- a/board/kontron/sl28/spl_atf.c\n+++ b/board/kontron/sl28/spl_atf.c\n@@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,\n\n \tdram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS;\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tdram_regions_info.region[i].addr = gd->bd->bi_dram[i].start;\n-\t\tdram_regions_info.region[i].size = gd->bd->bi_dram[i].size;\n-\t\tdram_regions_info.total_dram_size += gd->bd->bi_dram[i].size;\n+\t\tdram_regions_info.region[i].addr = gd->dram[i].start;\n+\t\tdram_regions_info.region[i].size = gd->dram[i].size;\n+\t\tdram_regions_info.total_dram_size += gd->dram[i].size;\n \t}\n\n \tbl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry,\ndiff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c\nindex e1ff041c54f5..ba922b43064f 100644\n--- a/board/liebherr/btt/btt.c\n+++ b/board/liebherr/btt/btt.c\n@@ -239,7 +239,7 @@ int spl_start_uboot(void)\n\n static const char *get_board_name(void)\n {\n-\tif (gd->bd->bi_dram[0].size == SZ_128M)\n+\tif (gd->dram[0].size == SZ_128M)\n \t\treturn STR_BTTC;\n\n \treturn STR_BTT3;\ndiff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c\nindex fc76d5765fa7..5e76942783f3 100644\n--- a/board/menlo/m53menlo/m53menlo.c\n+++ b/board/menlo/m53menlo/m53menlo.c\n@@ -69,11 +69,11 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = mx53_dram_size[0];\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = mx53_dram_size[0];\n\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_2;\n-\tgd->bd->bi_dram[1].size = mx53_dram_size[1];\n+\tgd->dram[1].start = PHYS_SDRAM_2;\n+\tgd->dram[1].size = mx53_dram_size[1];\n\n \treturn 0;\n }\ndiff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c\nindex 05c4dd187fe3..68d516c7db86 100644\n--- a/board/nuvoton/arbel_evb/arbel_evb.c\n+++ b/board/nuvoton/arbel_evb/arbel_evb.c\n@@ -57,7 +57,7 @@ int dram_init_banksize(void)\n {\n \tphys_size_t ram_size = gd->ram_size;\n\n-\tgd->bd->bi_dram[0].start = 0;\n+\tgd->dram[0].start = 0;\n\n \t#if defined(CONFIG_SYS_MEM_TOP_HIDE)\n \t\tram_size += CONFIG_SYS_MEM_TOP_HIDE;\n@@ -69,25 +69,25 @@ int dram_init_banksize(void)\n \tcase DRAM_1GB_SIZE:\n \tcase DRAM_2GB_ECC_SIZE:\n \tcase DRAM_2GB_SIZE:\n-\t\tgd->bd->bi_dram[0].size = ram_size;\n-\t\tgd->bd->bi_dram[1].start = 0;\n-\t\tgd->bd->bi_dram[1].size = 0;\n+\t\tgd->dram[0].size = ram_size;\n+\t\tgd->dram[1].start = 0;\n+\t\tgd->dram[1].size = 0;\n \t\tbreak;\n \tcase DRAM_4GB_ECC_SIZE:\n-\t\tgd->bd->bi_dram[0].size = DRAM_2GB_SIZE;\n-\t\tgd->bd->bi_dram[1].start = DRAM_4GB_SIZE;\n-\t\tgd->bd->bi_dram[1].size = DRAM_2GB_SIZE -\n+\t\tgd->dram[0].size = DRAM_2GB_SIZE;\n+\t\tgd->dram[1].start = DRAM_4GB_SIZE;\n+\t\tgd->dram[1].size = DRAM_2GB_SIZE -\n \t\t\t(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);\n \t\tbreak;\n \tcase DRAM_4GB_SIZE:\n-\t\tgd->bd->bi_dram[0].size = DRAM_2GB_SIZE;\n-\t\tgd->bd->bi_dram[1].start = DRAM_4GB_SIZE;\n-\t\tgd->bd->bi_dram[1].size = DRAM_2GB_SIZE;\n+\t\tgd->dram[0].size = DRAM_2GB_SIZE;\n+\t\tgd->dram[1].start = DRAM_4GB_SIZE;\n+\t\tgd->dram[1].size = DRAM_2GB_SIZE;\n \t\tbreak;\n \tdefault:\n-\t\tgd->bd->bi_dram[0].size = DRAM_1GB_SIZE;\n-\t\tgd->bd->bi_dram[1].start = 0;\n-\t\tgd->bd->bi_dram[1].size = 0;\n+\t\tgd->dram[0].size = DRAM_1GB_SIZE;\n+\t\tgd->dram[1].start = 0;\n+\t\tgd->dram[1].size = 0;\n \t\tbreak;\n \t}\n\ndiff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c\nindex 11dbef846881..6843b33679d0 100644\n--- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c\n+++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c\n@@ -73,7 +73,7 @@ u32 spl_boot_device(void)\n\n int board_init(void)\n {\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \treturn 0;\n }\ndiff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c\nindex 056489932ac7..19d068fc6268 100644\n--- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c\n+++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c\n@@ -78,7 +78,7 @@ u32 spl_boot_device(void)\n\n int board_init(void)\n {\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \treturn 0;\n }\ndiff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c\nindex 047aea8181ae..3afd5ae2136d 100644\n--- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c\n+++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c\n@@ -73,7 +73,7 @@ u32 spl_boot_device(void)\n\n int board_init(void)\n {\n-\tgd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;\n+\tgd->bd->bi_boot_params = gd->dram[0].start + 0x100;\n\n \treturn 0;\n }\ndiff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c\nindex fd897e832c82..8d07f6110ce6 100644\n--- a/board/nxp/ls1021aqds/ddr.c\n+++ b/board/nxp/ls1021aqds/ddr.c\n@@ -192,8 +192,8 @@ int fsl_initdram(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn 0;\n }\ndiff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c\nindex db94d9c1fa80..c0ab4afac0e3 100644\n--- a/board/nxp/ls1028a/ls1028a.c\n+++ b/board/nxp/ls1028a/ls1028a.c\n@@ -152,7 +152,7 @@ int board_early_init_f(void)\n void detail_board_ddr_info(void)\n {\n \tputs(\"\\nDDR \");\n-\tprint_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, \"\");\n+\tprint_size(gd->dram[0].size + gd->dram[1].size, \"\");\n \tprint_ddr_info(0);\n }\n\n@@ -205,10 +205,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tft_cpu_setup(blob, bd);\n\n \t/* fixup DT for the two GPP DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n #ifdef CONFIG_RESV_RAM\n \t/* reduce size if reserved memory is within this bank */\ndiff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c\nindex f043599fbb88..7b2c6151d917 100644\n--- a/board/nxp/ls1043aqds/ls1043aqds.c\n+++ b/board/nxp/ls1043aqds/ls1043aqds.c\n@@ -542,10 +542,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tu8 reg;\n\n \t/* fixup DT for the two DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n \tfdt_fixup_memory_banks(blob, base, size, 2);\n \tft_cpu_setup(blob, bd);\ndiff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c\nindex bba041065b5c..678c529cf552 100644\n--- a/board/nxp/ls1043ardb/ls1043ardb.c\n+++ b/board/nxp/ls1043ardb/ls1043ardb.c\n@@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tu64 size[CONFIG_NR_DRAM_BANKS];\n\n \t/* fixup DT for the two DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n \tfdt_fixup_memory_banks(blob, base, size, 2);\n \tft_cpu_setup(blob, bd);\ndiff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c\nindex 8889c24f1f0c..6c35c0a4347d 100644\n--- a/board/nxp/ls1046afrwy/ls1046afrwy.c\n+++ b/board/nxp/ls1046afrwy/ls1046afrwy.c\n@@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tu64 size[CONFIG_NR_DRAM_BANKS];\n\n \t/* fixup DT for the two DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n \tfdt_fixup_memory_banks(blob, base, size, 2);\n \tft_cpu_setup(blob, bd);\ndiff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c\nindex 7df125508686..f04e75eac13d 100644\n--- a/board/nxp/ls1046aqds/ls1046aqds.c\n+++ b/board/nxp/ls1046aqds/ls1046aqds.c\n@@ -426,10 +426,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tu8 reg;\n\n \t/* fixup DT for the two DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n \tfdt_fixup_memory_banks(blob, base, size, 2);\n \tft_cpu_setup(blob, bd);\ndiff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c\nindex 83b280f7646a..6677e271029d 100644\n--- a/board/nxp/ls1046ardb/ls1046ardb.c\n+++ b/board/nxp/ls1046ardb/ls1046ardb.c\n@@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tu64 size[CONFIG_NR_DRAM_BANKS];\n\n \t/* fixup DT for the two DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n \tfdt_fixup_memory_banks(blob, base, size, 2);\n \tft_cpu_setup(blob, bd);\ndiff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c\nindex 51ec055be63a..49bb25531a79 100644\n--- a/board/nxp/ls1088a/ls1088a.c\n+++ b/board/nxp/ls1088a/ls1088a.c\n@@ -830,7 +830,7 @@ int board_init(void)\n void detail_board_ddr_info(void)\n {\n \tputs(\"\\nDDR \");\n-\tprint_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, \"\");\n+\tprint_size(gd->dram[0].size + gd->dram[1].size, \"\");\n \tprint_ddr_info(0);\n }\n\n@@ -959,8 +959,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n\n \t/* fixup DT for the two GPP DDR banks */\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tbase[i] = gd->bd->bi_dram[i].start;\n-\t\tsize[i] = gd->bd->bi_dram[i].size;\n+\t\tbase[i] = gd->dram[i].start;\n+\t\tsize[i] = gd->dram[i].size;\n \t}\n\n #ifdef CONFIG_RESV_RAM\ndiff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c\nindex aba0560181af..325dc817aaf6 100644\n--- a/board/nxp/ls2080aqds/ls2080aqds.c\n+++ b/board/nxp/ls2080aqds/ls2080aqds.c\n@@ -253,12 +253,12 @@ int misc_init_r(void)\n void detail_board_ddr_info(void)\n {\n \tputs(\"\\nDDR \");\n-\tprint_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, \"\");\n+\tprint_size(gd->dram[0].size + gd->dram[1].size, \"\");\n \tprint_ddr_info(0);\n #ifdef CONFIG_SYS_FSL_HAS_DP_DDR\n-\tif (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {\n+\tif (soc_has_dp_ddr() && gd->dram[2].size) {\n \t\tputs(\"\\nDP-DDR \");\n-\t\tprint_size(gd->bd->bi_dram[2].size, \"\");\n+\t\tprint_size(gd->dram[2].size, \"\");\n \t\tprint_ddr_info(CONFIG_DP_DDR_CTRL);\n \t}\n #endif\n@@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tft_cpu_setup(blob, bd);\n\n \t/* fixup DT for the two GPP DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n #ifdef CONFIG_RESV_RAM\n \t/* reduce size if reserved memory is within this bank */\ndiff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c\nindex 6f824f57c478..f894539e717e 100644\n--- a/board/nxp/ls2080ardb/ls2080ardb.c\n+++ b/board/nxp/ls2080ardb/ls2080ardb.c\n@@ -359,12 +359,12 @@ int misc_init_r(void)\n void detail_board_ddr_info(void)\n {\n \tputs(\"\\nDDR \");\n-\tprint_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, \"\");\n+\tprint_size(gd->dram[0].size + gd->dram[1].size, \"\");\n \tprint_ddr_info(0);\n #ifdef CONFIG_SYS_FSL_HAS_DP_DDR\n-\tif (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {\n+\tif (soc_has_dp_ddr() && gd->dram[2].size) {\n \t\tputs(\"\\nDP-DDR \");\n-\t\tprint_size(gd->bd->bi_dram[2].size, \"\");\n+\t\tprint_size(gd->dram[2].size, \"\");\n \t\tprint_ddr_info(CONFIG_DP_DDR_CTRL);\n \t}\n #endif\n@@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \tsize = calloc(total_memory_banks, sizeof(u64));\n\n \t/* fixup DT for the two GPP DDR banks */\n-\tbase[0] = gd->bd->bi_dram[0].start;\n-\tsize[0] = gd->bd->bi_dram[0].size;\n-\tbase[1] = gd->bd->bi_dram[1].start;\n-\tsize[1] = gd->bd->bi_dram[1].size;\n+\tbase[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n+\tbase[1] = gd->dram[1].start;\n+\tsize[1] = gd->dram[1].size;\n\n #ifdef CONFIG_RESV_RAM\n \t/* reduce size if reserved memory is within this bank */\ndiff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c\nindex 341f82ce7245..9debeb5044c7 100644\n--- a/board/nxp/lx2160a/lx2160a.c\n+++ b/board/nxp/lx2160a/lx2160a.c\n@@ -567,7 +567,7 @@ void detail_board_ddr_info(void)\n\n \tputs(\"\\nDDR \");\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)\n-\t\tddr_size += gd->bd->bi_dram[i].size;\n+\t\tddr_size += gd->dram[i].size;\n \tprint_size(ddr_size, \"\");\n \tprint_ddr_info(0);\n }\n@@ -800,8 +800,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n\n \t/* fixup DT for the three GPP DDR banks */\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tbase[i] = gd->bd->bi_dram[i].start;\n-\t\tsize[i] = gd->bd->bi_dram[i].size;\n+\t\tbase[i] = gd->dram[i].start;\n+\t\tsize[i] = gd->dram[i].size;\n \t}\n\n #ifdef CONFIG_RESV_RAM\ndiff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c\nindex 3cdcbf2ecc97..6df521d789f5 100644\n--- a/board/phytec/phycore_am62x/phycore-am62x.c\n+++ b/board/phytec/phycore_am62x/phycore-am62x.c\n@@ -93,7 +93,7 @@ int dram_init_banksize(void)\n {\n \tu8 ram_size;\n\n-\tmemset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS);\n+\tmemset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS);\n\n \tif (!IS_ENABLED(CONFIG_CPU_V7R))\n \t\treturn fdtdec_setup_memory_banksize();\n@@ -101,34 +101,34 @@ int dram_init_banksize(void)\n \tram_size = phytec_get_am62_ddr_size_default();\n \tswitch (ram_size) {\n \tcase EEPROM_RAM_SIZE_1GB:\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x40000000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x40000000;\n \t\tgd->ram_size = 0x40000000;\n \t\tbreak;\n\n \tcase EEPROM_RAM_SIZE_2GB:\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x80000000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x80000000;\n \t\tgd->ram_size = 0x80000000;\n \t\tbreak;\n\n \tcase EEPROM_RAM_SIZE_4GB:\n \t\t/* Bank 0 declares the memory available in the DDR low region */\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x80000000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x80000000;\n \t\tgd->ram_size = 0x80000000;\n\n #ifdef CONFIG_PHYS_64BIT\n \t\t/* Bank 1 declares the memory available in the DDR upper region */\n-\t\tgd->bd->bi_dram[1].start = 0x880000000;\n-\t\tgd->bd->bi_dram[1].size = 0x80000000;\n+\t\tgd->dram[1].start = 0x880000000;\n+\t\tgd->dram[1].size = 0x80000000;\n \t\tgd->ram_size = 0x100000000;\n #endif\n \t\tbreak;\n \tdefault:\n \t\t/* Continue with default 2GB setup */\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x80000000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x80000000;\n \t\tgd->ram_size = 0x80000000;\n \t\tprintf(\"DDR size %d is not supported\\n\", ram_size);\n \t}\n@@ -186,8 +186,8 @@ int do_board_detect(void)\n \tdram_init_banksize();\n\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart[bank] = gd->bd->bi_dram[bank].start;\n-\t\tsize[bank] = gd->bd->bi_dram[bank].size;\n+\t\tstart[bank] = gd->dram[bank].start;\n+\t\tsize[bank] = gd->dram[bank].size;\n \t}\n\n \tret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS);\ndiff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c\nindex 114aa2170235..5e077872152f 100644\n--- a/board/phytec/phycore_am64x/phycore-am64x.c\n+++ b/board/phytec/phycore_am64x/phycore-am64x.c\n@@ -66,7 +66,7 @@ int dram_init_banksize(void)\n {\n \tu8 ram_size;\n\n-\tmemset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS);\n+\tmemset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS);\n\n \tif (!IS_ENABLED(CONFIG_CPU_V7R))\n \t\treturn fdtdec_setup_memory_banksize();\n@@ -74,21 +74,21 @@ int dram_init_banksize(void)\n \tram_size = phytec_get_am64_ddr_size_default();\n \tswitch (ram_size) {\n \tcase EEPROM_RAM_SIZE_1GB:\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x40000000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x40000000;\n \t\tgd->ram_size = 0x40000000;\n \t\tbreak;\n\n \tcase EEPROM_RAM_SIZE_2GB:\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x80000000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x80000000;\n \t\tgd->ram_size = 0x80000000;\n \t\tbreak;\n\n \tdefault:\n \t\t/* Continue with default 2GB setup */\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = 0x80000000;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = 0x80000000;\n \t\tgd->ram_size = 0x80000000;\n \t\tprintf(\"DDR size %d is not supported\\n\", ram_size);\n \t}\n@@ -109,8 +109,8 @@ int do_board_detect(void)\n \tdram_init_banksize();\n\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tstart[bank] = gd->bd->bi_dram[bank].start;\n-\t\tsize[bank] = gd->bd->bi_dram[bank].size;\n+\t\tstart[bank] = gd->dram[bank].start;\n+\t\tsize[bank] = gd->dram[bank].size;\n \t}\n\n \treturn fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS);\ndiff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c\nindex 9fc63febdac9..a738e3542e2d 100644\n--- a/board/phytium/durian/durian.c\n+++ b/board/phytium/durian/durian.c\n@@ -31,8 +31,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = PHYS_SDRAM_1_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c\nindex 6824454cdf4f..421e193e730d 100644\n--- a/board/phytium/pe2201/pe2201.c\n+++ b/board/phytium/pe2201/pe2201.c\n@@ -44,8 +44,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = PHYS_SDRAM_1_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c\nindex b0a1484c0fa4..885c660a289b 100644\n--- a/board/raspberrypi/rpi/rpi.c\n+++ b/board/raspberrypi/rpi/rpi.c\n@@ -356,9 +356,9 @@ int dram_init_banksize(void)\n\n \t/* Update gd->ram_size to reflect total RAM across all banks */\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tif (gd->bd->bi_dram[i].size == 0)\n+\t\tif (gd->dram[i].size == 0)\n \t\t\tbreak;\n-\t\ttotal_size += gd->bd->bi_dram[i].size;\n+\t\ttotal_size += gd->dram[i].size;\n \t}\n \tgd->ram_size = total_size;\n\ndiff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c\nindex 3d537be4d02f..09667d46d996 100644\n--- a/board/renesas/common/rcar64-common.c\n+++ b/board/renesas/common/rcar64-common.c\n@@ -49,15 +49,15 @@ int dram_init_banksize(void)\n \t\treturn 0;\n\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tif (gd->bd->bi_dram[bank].start != 0x48000000)\n+\t\tif (gd->dram[bank].start != 0x48000000)\n \t\t\tcontinue;\n\n \t\t/*\n \t\t * If this U-Boot runs in EL3, make the bottom 128 MiB\n \t\t * available for loading of follow up firmware blobs.\n \t\t */\n-\t\tgd->bd->bi_dram[bank].start -= 0x8000000;\n-\t\tgd->bd->bi_dram[bank].size += 0x8000000;\n+\t\tgd->dram[bank].start -= 0x8000000;\n+\t\tgd->dram[bank].size += 0x8000000;\n \t\tbreak;\n \t}\n\ndiff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c\nindex 8153aed15e3d..9245bf348f8c 100644\n--- a/board/renesas/genmai/genmai.c\n+++ b/board/renesas/genmai/genmai.c\n@@ -43,7 +43,7 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = gd->ram_base;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].start = gd->ram_base;\n+\tgd->dram[0].size = gd->ram_size;\n \treturn 0;\n }\ndiff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c\nindex f5b1a5614b10..9ae3b2667f58 100644\n--- a/board/renesas/sparrowhawk/sparrowhawk.c\n+++ b/board/renesas/sparrowhawk/sparrowhawk.c\n@@ -261,10 +261,10 @@ void renesas_dram_init_banksize(void)\n\n \t/* 16 GiB device, adjust memory map. */\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tif (gd->bd->bi_dram[bank].start == 0x480000000ULL)\n-\t\t\tgd->bd->bi_dram[bank].size = 0x180000000ULL;\n-\t\telse if (gd->bd->bi_dram[bank].start == 0x600000000ULL)\n-\t\t\tgd->bd->bi_dram[bank].size = 0x200000000ULL;\n+\t\tif (gd->dram[bank].start == 0x480000000ULL)\n+\t\t\tgd->dram[bank].size = 0x180000000ULL;\n+\t\telse if (gd->dram[bank].start == 0x600000000ULL)\n+\t\t\tgd->dram[bank].size = 0x200000000ULL;\n \t}\n }\n\ndiff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c\nindex ee578749bce7..64ed844e4fb1 100644\n--- a/board/ronetix/pm9261/pm9261.c\n+++ b/board/ronetix/pm9261/pm9261.c\n@@ -108,8 +108,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM;\n+\tgd->dram[0].size = PHYS_SDRAM_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c\nindex 8125f064cf11..142647cfca6f 100644\n--- a/board/ronetix/pm9263/pm9263.c\n+++ b/board/ronetix/pm9263/pm9263.c\n@@ -102,8 +102,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM;\n+\tgd->dram[0].size = PHYS_SDRAM_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c\nindex 5d5edd9f2530..b5664296a81a 100644\n--- a/board/ronetix/pm9g45/pm9g45.c\n+++ b/board/ronetix/pm9g45/pm9g45.c\n@@ -150,8 +150,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = CFG_SYS_SDRAM_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c\nindex e70b4a82687c..130136e85966 100644\n--- a/board/samsung/arndale/arndale.c\n+++ b/board/samsung/arndale/arndale.c\n@@ -67,8 +67,8 @@ int dram_init_banksize(void)\n \t\taddr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);\n \t\tsize = get_ram_size((long *)addr, SDRAM_BANK_SIZE);\n\n-\t\tgd->bd->bi_dram[i].start = addr;\n-\t\tgd->bd->bi_dram[i].size = size;\n+\t\tgd->dram[i].start = addr;\n+\t\tgd->dram[i].size = size;\n \t}\n\n \treturn 0;\ndiff --git a/board/samsung/common/board.c b/board/samsung/common/board.c\nindex eed1c2450fa6..da3510023c4d 100644\n--- a/board/samsung/common/board.c\n+++ b/board/samsung/common/board.c\n@@ -115,7 +115,7 @@ int board_init(void)\n \tulong size = CONFIG_SYS_MEM_TOP_HIDE;\n\n \tgd->ram_size -= size;\n-\tgd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;\n+\tgd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;\n #endif\n \texynos_init();\n\n@@ -143,8 +143,8 @@ int dram_init_banksize(void)\n \t\taddr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);\n \t\tsize = get_ram_size((long *)addr, SDRAM_BANK_SIZE);\n\n-\t\tgd->bd->bi_dram[i].start = addr;\n-\t\tgd->bd->bi_dram[i].size = size;\n+\t\tgd->dram[i].start = addr;\n+\t\tgd->dram[i].size = size;\n \t}\n\n \treturn 0;\ndiff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c\nindex 6b2b15236636..d91e2e7d3f24 100644\n--- a/board/samsung/exynos-mobile/exynos-mobile.c\n+++ b/board/samsung/exynos-mobile/exynos-mobile.c\n@@ -346,8 +346,8 @@ int dram_init_banksize(void)\n \tunsigned int i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tgd->bd->bi_dram[i].start = mem_map[i + 1].phys;\n-\t\tgd->bd->bi_dram[i].size = mem_map[i + 1].size;\n+\t\tgd->dram[i].start = mem_map[i + 1].phys;\n+\t\tgd->dram[i].size = mem_map[i + 1].size;\n \t}\n\n \treturn 0;\ndiff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c\nindex a1047f3fd2a2..96a411233d1d 100644\n--- a/board/samsung/goni/goni.c\n+++ b/board/samsung/goni/goni.c\n@@ -43,12 +43,12 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_2;\n-\tgd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;\n-\tgd->bd->bi_dram[2].start = PHYS_SDRAM_3;\n-\tgd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = PHYS_SDRAM_1_SIZE;\n+\tgd->dram[1].start = PHYS_SDRAM_2;\n+\tgd->dram[1].size = PHYS_SDRAM_2_SIZE;\n+\tgd->dram[2].start = PHYS_SDRAM_3;\n+\tgd->dram[2].size = PHYS_SDRAM_3_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c\nindex 7d0b0fcb0ae1..7e992c23a1b9 100644\n--- a/board/samsung/smdkc100/smdkc100.c\n+++ b/board/samsung/smdkc100/smdkc100.c\n@@ -56,8 +56,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = PHYS_SDRAM_1_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c\nindex 5a4874b29cdf..f013893b465f 100644\n--- a/board/samsung/smdkv310/smdkv310.c\n+++ b/board/samsung/smdkv310/smdkv310.c\n@@ -57,17 +57,17 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,\n \t\t\t\t\t\t\tPHYS_SDRAM_1_SIZE);\n-\tgd->bd->bi_dram[1].start = PHYS_SDRAM_2;\n-\tgd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,\n+\tgd->dram[1].start = PHYS_SDRAM_2;\n+\tgd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,\n \t\t\t\t\t\t\tPHYS_SDRAM_2_SIZE);\n-\tgd->bd->bi_dram[2].start = PHYS_SDRAM_3;\n-\tgd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,\n+\tgd->dram[2].start = PHYS_SDRAM_3;\n+\tgd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,\n \t\t\t\t\t\t\tPHYS_SDRAM_3_SIZE);\n-\tgd->bd->bi_dram[3].start = PHYS_SDRAM_4;\n-\tgd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,\n+\tgd->dram[3].start = PHYS_SDRAM_4;\n+\tgd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,\n \t\t\t\t\t\t\tPHYS_SDRAM_4_SIZE);\n\n \treturn 0;\ndiff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c\nindex c75f4a0d084d..50eb5e1294c7 100644\n--- a/board/siemens/iot2050/board.c\n+++ b/board/siemens/iot2050/board.c\n@@ -397,20 +397,20 @@ int dram_init_banksize(void)\n\n \tif (gd->ram_size > SZ_2G) {\n \t\t/* Bank 0 declares the memory available in the DDR low region */\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = SZ_2G;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = SZ_2G;\n\n \t\t/* Bank 1 declares the memory available in the DDR high region */\n-\t\tgd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;\n-\t\tgd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;\n+\t\tgd->dram[1].start = CFG_SYS_SDRAM_BASE1;\n+\t\tgd->dram[1].size = gd->ram_size - SZ_2G;\n \t} else {\n \t\t/* Bank 0 declares the memory available in the DDR low region */\n-\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\t\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\t\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->dram[0].size = gd->ram_size;\n\n \t\t/* Bank 1 declares the memory available in the DDR high region */\n-\t\tgd->bd->bi_dram[1].start = 0;\n-\t\tgd->bd->bi_dram[1].size = 0;\n+\t\tgd->dram[1].start = 0;\n+\t\tgd->dram[1].size = 0;\n \t}\n\n \treturn 0;\ndiff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c\nindex 556a9ed527e7..a7bd08f69ade 100644\n--- a/board/socionext/developerbox/developerbox.c\n+++ b/board/socionext/developerbox/developerbox.c\n@@ -170,11 +170,11 @@ int dram_init_banksize(void)\n \tstruct draminfo_entry *ent = synquacer_draminfo->entry;\n \tint i;\n\n-\tfor (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {\n+\tfor (i = 0; i < ARRAY_SIZE(gd->dram); i++) {\n \t\tif (i < synquacer_draminfo->nr_regions) {\n \t\t\tdebug(\"%s: dram[%d] = %llx@%llx\\n\", __func__, i, ent[i].size, ent[i].base);\n-\t\t\tgd->bd->bi_dram[i].start = ent[i].base;\n-\t\t\tgd->bd->bi_dram[i].size = ent[i].size;\n+\t\t\tgd->dram[i].start = ent[i].base;\n+\t\t\tgd->dram[i].size = ent[i].size;\n \t\t}\n \t}\n\ndiff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c\nindex f5174720434a..a1b0265d5acb 100644\n--- a/board/st/stih410-b2260/board.c\n+++ b/board/st/stih410-b2260/board.c\n@@ -18,8 +18,8 @@ int dram_init(void)\n\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = PHYS_SDRAM_1;\n-\tgd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;\n+\tgd->dram[0].start = PHYS_SDRAM_1;\n+\tgd->dram[0].size = PHYS_SDRAM_1_SIZE;\n\n \treturn 0;\n }\ndiff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c\nindex 826c002907d6..66330184af86 100644\n--- a/board/ste/stemmy/stemmy.c\n+++ b/board/ste/stemmy/stemmy.c\n@@ -70,8 +70,8 @@ int dram_init_banksize(void)\n \t\tif (t->hdr.tag != ATAG_MEM)\n \t\t\tcontinue;\n\n-\t\tgd->bd->bi_dram[bank].start = t->u.mem.start;\n-\t\tgd->bd->bi_dram[bank].size = t->u.mem.size;\n+\t\tgd->dram[bank].start = t->u.mem.start;\n+\t\tgd->dram[bank].size = t->u.mem.size;\n \t\tif (++bank == CONFIG_NR_DRAM_BANKS)\n \t\t\tbreak;\n \t}\ndiff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c\nindex 0966db2bb620..6f1fed43e361 100644\n--- a/board/ti/dra7xx/evm.c\n+++ b/board/ti/dra7xx/evm.c\n@@ -643,11 +643,11 @@ int dram_init_banksize(void)\n\n \tram_size = board_ti_get_emif_size();\n\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = get_effective_memsize();\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = get_effective_memsize();\n \tif (ram_size > CFG_MAX_MEM_MAPPED) {\n-\t\tgd->bd->bi_dram[1].start = 0x200000000;\n-\t\tgd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;\n+\t\tgd->dram[1].start = 0x200000000;\n+\t\tgd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;\n \t}\n\n \treturn 0;\ndiff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c\nindex a92aa5cfc671..43330993955d 100644\n--- a/board/ti/ks2_evm/board.c\n+++ b/board/ti/ks2_evm/board.c\n@@ -117,8 +117,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \t}\n\n \tnbanks = 1;\n-\tstart[0] = bd->bi_dram[0].start;\n-\tsize[0] = bd->bi_dram[0].size;\n+\tstart[0] = gd->dram[0].start;\n+\tsize[0] = gd->dram[0].size;\n\n \t/* adjust memory start address for LPAE */\n \tif (lpae) {\ndiff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c\nindex 69a8a18d3a75..c63812bd966c 100644\n--- a/board/toradex/colibri_imx7/colibri_imx7.c\n+++ b/board/toradex/colibri_imx7/colibri_imx7.c\n@@ -288,13 +288,13 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n \t\t * Reserve 1MB of memory for M4 (1MiB is also the minimum\n \t\t * alignment for Linux due to MMU section size restrictions).\n \t\t */\n-\t\tstart[0] = gd->bd->bi_dram[0].start;\n+\t\tstart[0] = gd->dram[0].start;\n \t\tsize[0] = SZ_256M - SZ_1M;\n\n \t\t/* If needed, create a second entry for memory beyond 256M */\n-\t\tif (gd->bd->bi_dram[0].size > SZ_256M) {\n-\t\t\tstart[1] = gd->bd->bi_dram[0].start + SZ_256M;\n-\t\t\tsize[1] = gd->bd->bi_dram[0].size - SZ_256M;\n+\t\tif (gd->dram[0].size > SZ_256M) {\n+\t\t\tstart[1] = gd->dram[0].start + SZ_256M;\n+\t\t\tsize[1] = gd->dram[0].size - SZ_256M;\n \t\t\tareas = 2;\n \t\t}\n\ndiff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c\nindex 19ac2ae93136..26af1af2069f 100644\n--- a/board/toradex/verdin-am62/verdin-am62.c\n+++ b/board/toradex/verdin-am62/verdin-am62.c\n@@ -44,7 +44,7 @@ int dram_init_banksize(void)\n \t\tprintf(\"Error setting up memory banksize. %d\\n\", ret);\n\n \t/* Use the detected RAM size, we only support 1 bank right now. */\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn ret;\n }\ndiff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c\nindex 1234b3887c6a..ec7775e06a7e 100644\n--- a/board/toradex/verdin-am62p/verdin-am62p.c\n+++ b/board/toradex/verdin-am62p/verdin-am62p.c\n@@ -78,7 +78,7 @@ int dram_init_banksize(void)\n \t\tprintf(\"Error setting up memory banksize. %d\\n\", ret);\n\n \t/* Use the detected RAM size, we only support 1 bank right now. */\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tgd->dram[0].size = gd->ram_size;\n\n \treturn ret;\n }\ndiff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c\nindex d41bd2e9deeb..494ec0694558 100644\n--- a/board/traverse/ten64/ten64.c\n+++ b/board/traverse/ten64/ten64.c\n@@ -148,7 +148,7 @@ int fsl_initdram(void)\n void detail_board_ddr_info(void)\n {\n \tputs(\"\\nDDR \");\n-\tprint_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, \"\");\n+\tprint_size(gd->dram[0].size + gd->dram[1].size, \"\");\n \tprint_ddr_info(0);\n }\n\n@@ -225,8 +225,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)\n\n \t/* fixup DT for the two GPP DDR banks */\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tbase[i] = gd->bd->bi_dram[i].start;\n-\t\tsize[i] = gd->bd->bi_dram[i].size;\n+\t\tbase[i] = gd->dram[i].start;\n+\t\tsize[i] = gd->dram[i].size;\n \t\t/* reduce size if reserved memory is within this bank */\n \t\tif (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i))\n \t\t\tsize[i] = gd->arch.resv_ram - base[i];\ndiff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c\nindex 05ecb75406b4..d8eff203a56f 100644\n--- a/board/xilinx/zynq/cmds.c\n+++ b/board/xilinx/zynq/cmds.c\n@@ -347,10 +347,10 @@ static int zynq_verify_image(u32 src_ptr)\n \t\t * This validation is just for PS DDR.\n \t\t * TODO: Update this for PL DDR check as well.\n \t\t */\n-\t\tif (part_load_addr < gd->bd->bi_dram[0].start &&\n+\t\tif (part_load_addr < gd->dram[0].start &&\n \t\t ((part_load_addr + part_data_len) >\n-\t\t (gd->bd->bi_dram[0].start +\n-\t\t gd->bd->bi_dram[0].size))) {\n+\t\t (gd->dram[0].start +\n+\t\t gd->dram[0].size))) {\n \t\t\tprintf(\"INVALID_LOAD_ADDRESS_FAIL\\n\");\n \t\t\treturn -1;\n \t\t}\ndiff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c\nindex a1d8ae266730..01ac379336b4 100644\n--- a/board/xilinx/zynqmp/zynqmp.c\n+++ b/board/xilinx/zynqmp/zynqmp.c\n@@ -84,7 +84,7 @@ int __maybe_unused psu_uboot_init(void)\n\n \t/* Delay is required for clocks to be propagated */\n \tudelay(1000000);\n-\n+\n \treturn 0;\n }\n\n@@ -279,8 +279,8 @@ int dram_init(void)\n #else\n int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = get_effective_memsize();\n+\tgd->dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->dram[0].size = get_effective_memsize();\n\n \tmem_map_fill();\n\ndiff --git a/boot/image-board.c b/boot/image-board.c\nindex 005d60caf5c9..57bee7e37732 100644\n--- a/boot/image-board.c\n+++ b/boot/image-board.c\n@@ -118,7 +118,7 @@ phys_addr_t env_get_bootm_low(void)\n #if defined(CFG_SYS_SDRAM_BASE)\n \treturn CFG_SYS_SDRAM_BASE;\n #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)\n-\treturn gd->bd->bi_dram[0].start;\n+\treturn gd->dram[0].start;\n #else\n \treturn 0;\n #endif\ndiff --git a/boot/image-fdt.c b/boot/image-fdt.c\nindex a3a4fb8b558f..91612dcf91b3 100644\n--- a/boot/image-fdt.c\n+++ b/boot/image-fdt.c\n@@ -223,8 +223,8 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size)\n \t\tof_start = NULL;\n\n \t\tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\t\tstart = gd->bd->bi_dram[bank].start;\n-\t\t\tsize = gd->bd->bi_dram[bank].size;\n+\t\t\tstart = gd->dram[bank].start;\n+\t\t\tsize = gd->dram[bank].size;\n\n \t\t\t/* DRAM bank addresses are too low, skip it. */\n \t\t\tif (start + size < low)\ndiff --git a/cmd/bdinfo.c b/cmd/bdinfo.c\nindex dc7c2c3c853c..d230dc07d68b 100644\n--- a/cmd/bdinfo.c\n+++ b/cmd/bdinfo.c\n@@ -77,15 +77,15 @@ void bdinfo_print_mhz(const char *name, unsigned long hz)\n \tprintf(\"%-12s= %6s MHz\\n\", name, strmhz(buf, hz));\n }\n\n-static void print_bi_dram(const struct bd_info *bd)\n+static void print_dram(const struct bd_info *bd)\n {\n \tint i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {\n-\t\tif (bd->bi_dram[i].size) {\n+\t\tif (gd->dram[i].size) {\n \t\t\tbdinfo_print_num_l(\"DRAM bank\",\ti);\n-\t\t\tbdinfo_print_num_ll(\"-> start\",\tbd->bi_dram[i].start);\n-\t\t\tbdinfo_print_num_ll(\"-> size\",\tbd->bi_dram[i].size);\n+\t\t\tbdinfo_print_num_ll(\"-> start\",\tgd->dram[i].start);\n+\t\t\tbdinfo_print_num_ll(\"-> size\",\tgd->dram[i].size);\n \t\t}\n \t}\n }\n@@ -144,7 +144,7 @@ static int bdinfo_print_all(struct bd_info *bd)\n \tbdinfo_print_num_l(\"bd address\", (ulong)bd);\n #endif\n \tbdinfo_print_num_l(\"boot_params\", (ulong)bd->bi_boot_params);\n-\tprint_bi_dram(bd);\n+\tprint_dram(bd);\n \tbdinfo_print_num_l(\"flashstart\", (ulong)bd->bi_flashstart);\n \tbdinfo_print_num_l(\"flashsize\", (ulong)bd->bi_flashsize);\n \tbdinfo_print_num_l(\"flashoffset\", (ulong)bd->bi_flashoffset);\n@@ -200,7 +200,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])\n \t\t\tprint_eth();\n \t\t\treturn CMD_RET_SUCCESS;\n \t\tcase 'm':\n-\t\t\tprint_bi_dram(bd);\n+\t\t\tprint_dram(bd);\n \t\t\treturn CMD_RET_SUCCESS;\n \t\tdefault:\n \t\t\treturn CMD_RET_USAGE;\ndiff --git a/cmd/ti/ddr4.c b/cmd/ti/ddr4.c\nindex a8d71d11a919..36277cc154cb 100644\n--- a/cmd/ti/ddr4.c\n+++ b/cmd/ti/ddr4.c\n@@ -227,10 +227,10 @@ static int do_ddr4_ecc_inject(struct cmd_tbl *cmdtp, int flag, int argc,\n \t\treturn CMD_RET_FAILURE;\n \t}\n\n-\tif (!((start_addr >= gd->bd->bi_dram[0].start &&\n-\t (start_addr <= (gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - 1))) ||\n-\t (start_addr >= gd->bd->bi_dram[1].start &&\n-\t (start_addr <= (gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size - 1))))) {\n+\tif (!((start_addr >= gd->dram[0].start &&\n+\t (start_addr <= (gd->dram[0].start + gd->dram[0].size - 1))) ||\n+\t (start_addr >= gd->dram[1].start &&\n+\t (start_addr <= (gd->dram[1].start + gd->dram[1].size - 1))))) {\n \t\tputs(\"Address is not in the DDR range\\n\");\n \t\treturn CMD_RET_FAILURE;\n \t}\ndiff --git a/cmd/ufetch.c b/cmd/ufetch.c\nindex bc5db08eee1b..7f6b5f86b4b0 100644\n--- a/cmd/ufetch.c\n+++ b/cmd/ufetch.c\n@@ -191,8 +191,8 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,\n \t\t\tprintf(\"CPU: \" RESET CONFIG_SYS_ARCH \" (%d cores, 1 in use)\\n\", n_cpus);\n \t\t\tbreak;\n \t\tcase MEMORY:\n-\t\t\tfor (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++)\n-\t\t\t\tsize += gd->bd->bi_dram[j].size;\n+\t\t\tfor (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->dram[j].size; j++)\n+\t\t\t\tsize += gd->dram[j].size;\n \t\t\tprintf(\"Memory:\" RESET \" \");\n \t\t\tprint_size(size, \"\\n\");\n \t\t\tbreak;\ndiff --git a/common/board_f.c b/common/board_f.c\nindex ce87c619e680..f0d07cb6f593 100644\n--- a/common/board_f.c\n+++ b/common/board_f.c\n@@ -222,11 +222,11 @@ static int show_dram_config(void)\n\n \tdebug(\"\\nRAM Configuration:\\n\");\n \tfor (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tsize += gd->bd->bi_dram[i].size;\n+\t\tsize += gd->dram[i].size;\n \t\tdebug(\"Bank #%d: %llx \", i,\n-\t\t (unsigned long long)(gd->bd->bi_dram[i].start));\n+\t\t (unsigned long long)(gd->dram[i].start));\n #ifdef DEBUG\n-\t\tprint_size(gd->bd->bi_dram[i].size, \"\\n\");\n+\t\tprint_size(gd->dram[i].size, \"\\n\");\n #endif\n \t}\n \tdebug(\"\\nDRAM: \");\n@@ -244,8 +244,8 @@ static int show_dram_config(void)\n\n __weak int dram_init_banksize(void)\n {\n-\tgd->bd->bi_dram[0].start = gd->ram_base;\n-\tgd->bd->bi_dram[0].size = get_effective_memsize();\n+\tgd->dram[0].start = gd->ram_base;\n+\tgd->dram[0].size = get_effective_memsize();\n\n \treturn 0;\n }\ndiff --git a/common/init/handoff.c b/common/init/handoff.c\nindex a7cd065fb385..a4d9d14393b8 100644\n--- a/common/init/handoff.c\n+++ b/common/init/handoff.c\n@@ -12,14 +12,13 @@ DECLARE_GLOBAL_DATA_PTR;\n\n void handoff_save_dram(struct spl_handoff *ho)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tint i;\n\n \tho->ram_size = gd->ram_size;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tho->ram_bank[i].start = bd->bi_dram[i].start;\n-\t\tho->ram_bank[i].size = bd->bi_dram[i].size;\n+\t\tho->ram_bank[i].start = gd->dram[i].start;\n+\t\tho->ram_bank[i].size = gd->dram[i].size;\n \t}\n }\n\n@@ -30,11 +29,10 @@ void handoff_load_dram_size(struct spl_handoff *ho)\n\n void handoff_load_dram_banks(struct spl_handoff *ho)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tint i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tbd->bi_dram[i].start = ho->ram_bank[i].start;\n-\t\tbd->bi_dram[i].size = ho->ram_bank[i].size;\n+\t\tgd->dram[i].start = ho->ram_bank[i].start;\n+\t\tgd->dram[i].size = ho->ram_bank[i].size;\n \t}\n }\ndiff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c\nindex 33e157b865a1..f726d9ab0162 100644\n--- a/drivers/bootcount/bootcount_ram.c\n+++ b/drivers/bootcount/bootcount_ram.c\n@@ -27,7 +27,7 @@ void bootcount_store(ulong a)\n \tint i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)\n-\t\tsize += gd->bd->bi_dram[i].size;\n+\t\tsize += gd->dram[i].size;\n \tsave_addr = (ulong *)(size - BOOTCOUNT_ADDR);\n \twritel(a, save_addr);\n \twritel(CONFIG_SYS_BOOTCOUNT_MAGIC, &save_addr[1]);\n@@ -50,7 +50,7 @@ ulong bootcount_load(void)\n \tint i, tmp;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)\n-\t\tsize += gd->bd->bi_dram[i].size;\n+\t\tsize += gd->dram[i].size;\n \tsave_addr = (ulong *)(size - BOOTCOUNT_ADDR);\n\n \tcounter = readl(&save_addr[0]);\ndiff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c\nindex b36a765a5de7..2d2b72cf7660 100644\n--- a/drivers/ddr/altera/sdram_agilex.c\n+++ b/drivers/ddr/altera/sdram_agilex.c\n@@ -104,7 +104,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \t/* Get bank configuration from devicetree */\n \tret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,\n-\t\t\t\t (phys_size_t *)&gd->ram_size, &bd);\n+\t\t\t\t (phys_size_t *)&gd->ram_size, gd);\n \tif (ret) {\n \t\tputs(\"DDR: Failed to decode memory node\\n\");\n \t\treturn -ENXIO;\n@@ -158,7 +158,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \tsdram_set_firewall(&bd);\n\n-\tpriv->info.base = bd.bi_dram[0].start;\n+\tpriv->info.base = gd->dram[0].start;\n \tpriv->info.size = gd->ram_size;\n\n \tdebug(\"DDR: HMC init success\\n\");\ndiff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c\nindex ee66c72157a6..d14e4bc5dcc1 100644\n--- a/drivers/ddr/altera/sdram_agilex5.c\n+++ b/drivers/ddr/altera/sdram_agilex5.c\n@@ -302,7 +302,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \t/* Get bank configuration from devicetree */\n \tret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,\n-\t\t\t\t (phys_size_t *)&gd->ram_size, gd->bd);\n+\t\t\t\t (phys_size_t *)&gd->ram_size, gd);\n \tif (ret) {\n \t\tputs(\"DDR: Failed to decode memory node\\n\");\n \t\tret = -ENXIO;\n@@ -345,19 +345,19 @@ int sdram_mmr_init_full(struct udevice *dev)\n \t\tfor (i = 0; i < config_dram_banks; i++) {\n \t\t\tremaining_size = hw_size - size_counter;\n \t\t\tif (remaining_size <= dram_bank_info[i].max_size) {\n-\t\t\t\tgd->bd->bi_dram[i].start = dram_bank_info[i].start;\n-\t\t\t\tgd->bd->bi_dram[i].size = remaining_size;\n+\t\t\t\tgd->dram[i].start = dram_bank_info[i].start;\n+\t\t\t\tgd->dram[i].size = remaining_size;\n \t\t\t\tdebug(\"Memory bank[%d] Starting address: 0x%llx size: 0x%llx\\n\",\n-\t\t\t\t i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);\n+\t\t\t\t i, gd->dram[i].start, gd->dram[i].size);\n \t\t\t\tbreak;\n \t\t\t}\n\n-\t\t\tgd->bd->bi_dram[i].start = dram_bank_info[i].start;\n-\t\t\tgd->bd->bi_dram[i].size = dram_bank_info[i].max_size;\n+\t\t\tgd->dram[i].start = dram_bank_info[i].start;\n+\t\t\tgd->dram[i].size = dram_bank_info[i].max_size;\n\n \t\t\tdebug(\"Memory bank[%d] Starting address: 0x%llx size: 0x%llx\\n\",\n-\t\t\t i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);\n-\t\t\tsize_counter += gd->bd->bi_dram[i].size;\n+\t\t\t i, gd->dram[i].start, gd->dram[i].size);\n+\t\t\tsize_counter += gd->dram[i].size;\n \t\t}\n\n \t\tgd->ram_size = hw_size;\n@@ -408,7 +408,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \tprintf(\"DDR: firewall init success\\n\");\n\n-\tpriv->info.base = gd->bd->bi_dram[0].start;\n+\tpriv->info.base = gd->dram[0].start;\n \tpriv->info.size = gd->ram_size;\n\n \t/* Ending DDR driver initialization success tracking */\ndiff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c\nindex 9b3cc5c7b869..e4d522202d8f 100644\n--- a/drivers/ddr/altera/sdram_agilex7m.c\n+++ b/drivers/ddr/altera/sdram_agilex7m.c\n@@ -375,7 +375,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \t/* Get bank configuration from devicetree */\n \tret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,\n-\t\t\t\t (phys_size_t *)&gd->ram_size, &bd);\n+\t\t\t\t (phys_size_t *)&gd->ram_size, gd);\n \tif (ret) {\n \t\tprintf(\"%s: Failed to decode memory node\\n\", memory_type_in_use(dev));\n\n@@ -484,7 +484,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \tprintf(\"%s: firewall init success\\n\", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : \"HBM\"));\n\n-\tpriv->info.base = bd.bi_dram[0].start;\n+\tpriv->info.base = gd->dram[0].start;\n \tpriv->info.size = gd->ram_size;\n\n \t/* Ending DDR driver initialization success tracking */\ndiff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c\nindex c281f711fdfd..9cc809b80014 100644\n--- a/drivers/ddr/altera/sdram_arria10.c\n+++ b/drivers/ddr/altera/sdram_arria10.c\n@@ -674,9 +674,9 @@ static void sdram_size_check(void)\n\n \tdebug(\"DDR: Running SDRAM size sanity check\\n\");\n\n-\tram_check = get_ram_size((long *)gd->bd->bi_dram[0].start,\n-\t\t\t\t gd->bd->bi_dram[0].size);\n-\tif (ram_check != gd->bd->bi_dram[0].size) {\n+\tram_check = get_ram_size((long *)gd->dram[0].start,\n+\t\t\t\t gd->dram[0].size);\n+\tif (ram_check != gd->dram[0].size) {\n \t\tputs(\"DDR: SDRAM size check failed!\\n\");\n \t\thang();\n \t}\n@@ -719,14 +719,14 @@ int ddr_calibration_sequence(void)\n \t/* setup the dram info within bd */\n \tdram_init_banksize();\n\n-\tif (gd->ram_size != gd->bd->bi_dram[0].size) {\n+\tif (gd->ram_size != gd->dram[0].size) {\n \t\tprintf(\"DDR: Warning: DRAM size from device tree (%ld MiB)\\n\",\n-\t\t gd->bd->bi_dram[0].size >> 20);\n+\t\t gd->dram[0].size >> 20);\n \t\tprintf(\" mismatch with hardware (%ld MiB).\\n\",\n \t\t gd->ram_size >> 20);\n \t}\n\n-\tif (gd->bd->bi_dram[0].size > gd->ram_size) {\n+\tif (gd->dram[0].size > gd->ram_size) {\n \t\tprintf(\"DDR: Error: DRAM size from device tree is greater\\n\");\n \t\tprintf(\" than hardware size.\\n\");\n \t\thang();\ndiff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c\nindex 17ec6afa82b0..900d4f599891 100644\n--- a/drivers/ddr/altera/sdram_n5x.c\n+++ b/drivers/ddr/altera/sdram_n5x.c\n@@ -2279,7 +2279,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \t/* Get bank configuration from devicetree */\n \tret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,\n-\t\t\t\t (phys_size_t *)&gd->ram_size, &bd);\n+\t\t\t\t (phys_size_t *)&gd->ram_size, gd);\n \tif (ret) {\n \t\tdebug(\"%s: Failed to decode memory node\\n\", __func__);\n \t\treturn -1;\n@@ -2287,7 +2287,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \tprintf(\"DDR: %lld MiB\\n\", gd->ram_size >> 20);\n\n-\tpriv->info.base = bd.bi_dram[0].start;\n+\tpriv->info.base = gd->dram[0].start;\n \tpriv->info.size = gd->ram_size;\n\n \tsdram_size_check(&bd);\ndiff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c\nindex 4ac4c79e0ac3..6664090f86a1 100644\n--- a/drivers/ddr/altera/sdram_s10.c\n+++ b/drivers/ddr/altera/sdram_s10.c\n@@ -285,7 +285,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \t/* Get bank configuration from devicetree */\n \tret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,\n-\t\t\t\t (phys_size_t *)&gd->ram_size, &bd);\n+\t\t\t\t (phys_size_t *)&gd->ram_size, gd);\n \tif (ret) {\n \t\tputs(\"DDR: Failed to decode memory node\\n\");\n \t\treturn -1;\n@@ -328,7 +328,7 @@ int sdram_mmr_init_full(struct udevice *dev)\n\n \tsdram_size_check(&bd);\n\n-\tpriv->info.base = bd.bi_dram[0].start;\n+\tpriv->info.base = gd->dram[0].start;\n \tpriv->info.size = gd->ram_size;\n\n \tdebug(\"DDR: HMC init success\\n\");\ndiff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c\nindex 8ee7049b164b..93df3d1812ab 100644\n--- a/drivers/ddr/altera/sdram_soc64.c\n+++ b/drivers/ddr/altera/sdram_soc64.c\n@@ -150,8 +150,8 @@ void sdram_init_ecc_bits(struct bd_info *bd)\n\n \ticache_enable();\n\n-\tstart_addr = bd->bi_dram[0].start;\n-\tsize = bd->bi_dram[0].size;\n+\tstart_addr = gd->dram[0].start;\n+\tsize = gd->dram[0].size;\n\n \t/* Initialize small block for page table */\n \tmemset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);\n@@ -174,8 +174,8 @@ void sdram_init_ecc_bits(struct bd_info *bd)\n \t\tif (bank >= CONFIG_NR_DRAM_BANKS)\n \t\t\tbreak;\n\n-\t\tstart_addr = bd->bi_dram[bank].start;\n-\t\tsize = bd->bi_dram[bank].size;\n+\t\tstart_addr = gd->dram[bank].start;\n+\t\tsize = gd->dram[bank].size;\n \t}\n\n \tdcache_disable();\n@@ -198,12 +198,12 @@ void sdram_size_check(struct bd_info *bd)\n \t\tphys_addr_t start = 0;\n \t\tphys_size_t remaining_size;\n\n-\t\tstart = bd->bi_dram[bank].start;\n-\t\tremaining_size = bd->bi_dram[bank].size;\n+\t\tstart = gd->dram[bank].start;\n+\t\tremaining_size = gd->dram[bank].size;\n \t\tdebug(\"Checking bank %d: start=0x%llx, size=0x%llx\\n\",\n \t\t bank, start, remaining_size);\n\n-\t\twhile (ram_check < bd->bi_dram[bank].size) {\n+\t\twhile (ram_check < gd->dram[bank].size) {\n \t\t\tphys_size_t size, test_size, detected_size;\n\n \t\t\tsize = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size);\n@@ -232,7 +232,7 @@ void sdram_size_check(struct bd_info *bd)\n \t\t\t}\n\n \t\t\tram_check += detected_size;\n-\t\t\tremaining_size = bd->bi_dram[bank].size - ram_check;\n+\t\t\tremaining_size = gd->dram[bank].size - ram_check;\n \t\t}\n\n \t\ttotal_ram_check += ram_check;\n@@ -292,10 +292,10 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd)\n \tu32 lower, upper;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tif (!bd->bi_dram[i].size)\n+\t\tif (!gd->dram[i].size)\n \t\t\tcontinue;\n\n-\t\tvalue = bd->bi_dram[i].start;\n+\t\tvalue = gd->dram[i].start;\n\n \t\t/* Keep first 1MB of SDRAM memory region as secure region when\n \t\t * using ATF flow, where the ATF code is located.\n@@ -322,7 +322,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd)\n \t\t\t\t (i * 4 * sizeof(u32)));\n\n \t\t/* Setting non-secure MPU limit and limit extended */\n-\t\tvalue = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;\n+\t\tvalue = gd->dram[i].start + gd->dram[i].size - 1;\n\n \t\tlower = lower_32_bits(value);\n \t\tupper = upper_32_bits(value);\n@@ -354,10 +354,10 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd)\n \tphys_size_t value;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tif (!bd->bi_dram[i].size)\n+\t\tif (!gd->dram[i].size)\n \t\t\tcontinue;\n\n-\t\tvalue = bd->bi_dram[i].start;\n+\t\tvalue = gd->dram[i].start;\n\n \t\t/* Keep first 1MB of SDRAM memory region as secure region when\n \t\t * using ATF flow, where the ATF code is located.\n@@ -376,7 +376,7 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd)\n \t\t\t\t\t (i * 4 * sizeof(u32)));\n\n \t\t/* Setting limit and limit extended */\n-\t\tvalue = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;\n+\t\tvalue = gd->dram[i].start + gd->dram[i].size - 1;\n\n \t\tlower = lower_32_bits(value);\n \t\tupper = upper_32_bits(value);\ndiff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c\nindex 5af1953cd148..89d511c1a6f6 100644\n--- a/drivers/mmc/mvebu_mmc.c\n+++ b/drivers/mmc/mvebu_mmc.c\n@@ -375,8 +375,8 @@ static void mvebu_window_setup(const struct mmc *mmc)\n \t\t\tbreak;\n \t\t}\n\n-\t\tsize = gd->bd->bi_dram[i].size;\n-\t\tbase = gd->bd->bi_dram[i].start;\n+\t\tsize = gd->dram[i].size;\n+\t\tbase = gd->dram[i].start;\n \t\tif (size && attrib) {\n \t\t\tmvebu_mmc_write(mmc, WINDOW_CTRL(i),\n \t\t\t\t\tMVCPU_WIN_CTRL_DATA(size,\ndiff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c\nindex 107a33aa9f54..4dc738980cbc 100644\n--- a/drivers/net/mvgbe.c\n+++ b/drivers/net/mvgbe.c\n@@ -256,8 +256,8 @@ static void set_dram_access(struct mvgbe_registers *regs)\n \t\twin_param.access_ctrl = EWIN_ACCESS_FULL;\n \t\twin_param.high_addr = 0;\n \t\t/* Get bank base and size */\n-\t\twin_param.base_addr = gd->bd->bi_dram[i].start;\n-\t\twin_param.size = gd->bd->bi_dram[i].size;\n+\t\twin_param.base_addr = gd->dram[i].start;\n+\t\twin_param.size = gd->dram[i].size;\n \t\tif (win_param.size == 0)\n \t\t\twin_param.enable = 0;\n \t\telse\ndiff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c\nindex 83b76d01f24a..1ac9f9b1a462 100644\n--- a/drivers/pci/pci-uclass.c\n+++ b/drivers/pci/pci-uclass.c\n@@ -1126,14 +1126,14 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,\n \t\treturn 0;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {\n-\t\tif (bd->bi_dram[i].size) {\n-\t\t\tphys_addr_t start = bd->bi_dram[i].start;\n+\t\tif (gd->dram[i].size) {\n+\t\t\tphys_addr_t start = gd->dram[i].start;\n\n \t\t\tif (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))\n-\t\t\t\tstart = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);\n+\t\t\t\tstart = virt_to_phys((void *)(uintptr_t)gd->dram[i].start);\n\n \t\t\tpci_set_region(hose->regions + hose->region_count++,\n-\t\t\t\t start, start, bd->bi_dram[i].size,\n+\t\t\t\t start, start, gd->dram[i].size,\n \t\t\t\t PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);\n \t\t}\n \t}\ndiff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c\nindex 794a41689138..38ee17f063d2 100644\n--- a/drivers/usb/host/ehci-marvell.c\n+++ b/drivers/usb/host/ehci-marvell.c\n@@ -222,8 +222,8 @@ static void usb_brg_adrdec_setup(int index)\n \t\t\tbreak;\n \t\t}\n\n-\t\tsize = gd->bd->bi_dram[i].size;\n-\t\tbase = gd->bd->bi_dram[i].start;\n+\t\tsize = gd->dram[i].size;\n+\t\tbase = gd->dram[i].start;\n \t\tif ((size) && (attrib))\n \t\t\twritel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,\n \t\t\t\t\t\t attrib, MVCPU_WIN_ENABLE),\ndiff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c\nindex ca627728743b..a686faf9f586 100644\n--- a/drivers/video/meson/meson_vpu.c\n+++ b/drivers/video/meson/meson_vpu.c\n@@ -81,8 +81,8 @@ cvbs:\n \tmeson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize *\n \t\t\t\t ((1 << VPU_MAX_LOG2_BPP) / 8) +\n \t\t\t\t MESON_VPU_OVERSCAN, EFI_PAGE_SIZE);\n-\tmeson_fb.base = gd->bd->bi_dram[0].start +\n-\t\t\tgd->bd->bi_dram[0].size - meson_fb.fb_size;\n+\tmeson_fb.base = gd->dram[0].start +\n+\t\t\tgd->dram[0].size - meson_fb.fb_size;\n\n \t/* Override the framebuffer address */\n \tuc_plat->base = meson_fb.base;\n@@ -175,8 +175,8 @@ static void meson_vpu_setup_simplefb(void *fdt)\n \t * at the end of the RAM and we strip this portion from the kernel\n \t * allowed region\n \t */\n-\tmem_start = gd->bd->bi_dram[0].start;\n-\tmem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size;\n+\tmem_start = gd->dram[0].start;\n+\tmem_size = gd->dram[0].size - meson_fb.fb_size;\n \tret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1);\n \tif (ret) {\n \t\teprintf(\"Cannot setup simplefb: Error reserving memory\\n\");\ndiff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c\nindex 154641b9a699..ab36ee1595b9 100644\n--- a/drivers/video/sunxi/sunxi_de2.c\n+++ b/drivers/video/sunxi/sunxi_de2.c\n@@ -368,7 +368,7 @@ int sunxi_simplefb_setup(void *blob)\n \t\treturn 0; /* Keep older kernels working */\n \t}\n\n-\tstart = gd->bd->bi_dram[0].start;\n+\tstart = gd->dram[0].start;\n \tsize = de2_plat->base - start;\n \tret = fdt_fixup_memory_banks(blob, &start, &size, 1);\n \tif (ret) {\ndiff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c\nindex 4a6a89ef9d26..fa492c661db2 100644\n--- a/drivers/video/sunxi/sunxi_display.c\n+++ b/drivers/video/sunxi/sunxi_display.c\n@@ -1336,7 +1336,7 @@ int sunxi_simplefb_setup(void *blob)\n \t * and e.g. Linux refuses to iomap RAM on ARM, see:\n \t * linux/arch/arm/mm/ioremap.c around line 301.\n \t */\n-\tstart = gd->bd->bi_dram[0].start;\n+\tstart = gd->dram[0].start;\n \tsize = sunxi_display->fb_addr - start;\n \tret = fdt_fixup_memory_banks(blob, &start, &size, 1);\n \tif (ret) {\ndiff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h\nindex 745d2c3a9663..72acd26a3d02 100644\n--- a/include/asm-generic/global_data.h\n+++ b/include/asm-generic/global_data.h\n@@ -448,6 +448,13 @@ struct global_data {\n \t */\n \tstruct upl *upl;\n #endif\n+\t/**\n+\t * @dram: array describing DRAM banks (start address and size for each bank)\n+\t */\n+\tstruct {\t\t\t/* RAM configuration */\n+\t\tphys_addr_t start;\n+\t\tphys_size_t size;\n+\t} dram[CONFIG_NR_DRAM_BANKS];\n };\n #ifndef DO_DEPS_ONLY\n static_assert(sizeof(struct global_data) == GD_SIZE);\ndiff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h\nindex 8c619c1b74a1..931fe2f32741 100644\n--- a/include/asm-generic/u-boot.h\n+++ b/include/asm-generic/u-boot.h\n@@ -59,10 +59,6 @@ struct bd_info {\n #endif\n \tulong\t bi_arch_number;\t/* unique id for this board */\n \tulong\t bi_boot_params;\t/* where this board expects params */\n-\tstruct {\t\t\t/* RAM configuration */\n-\t\tphys_addr_t start;\n-\t\tphys_size_t size;\n-\t} bi_dram[CONFIG_NR_DRAM_BANKS];\n };\n\n #endif /* __ASSEMBLY__ */\ndiff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h\nindex a6aafb518542..36e330887cd2 100644\n--- a/include/configs/m53menlo.h\n+++ b/include/configs/m53menlo.h\n@@ -15,9 +15,9 @@\n * Memory configurations\n */\n #define PHYS_SDRAM_1\t\t\tCSD0_BASE_ADDR\n-#define PHYS_SDRAM_1_SIZE\t\t(gd->bd->bi_dram[0].size)\n+#define PHYS_SDRAM_1_SIZE\t\t(gd->dram[0].size)\n #define PHYS_SDRAM_2\t\t\tCSD1_BASE_ADDR\n-#define PHYS_SDRAM_2_SIZE\t\t(gd->bd->bi_dram[1].size)\n+#define PHYS_SDRAM_2_SIZE\t\t(gd->dram[1].size)\n #define PHYS_SDRAM_SIZE\t\t\t(gd->ram_size)\n\n #define CFG_SYS_SDRAM_BASE\t\t(PHYS_SDRAM_1)\ndiff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h\nindex 2bd1426c7d9d..e823611d2e46 100644\n--- a/include/configs/mx53cx9020.h\n+++ b/include/configs/mx53cx9020.h\n@@ -51,9 +51,9 @@\n\n /* Physical Memory Map */\n #define PHYS_SDRAM_1\t\t\tCSD0_BASE_ADDR\n-#define PHYS_SDRAM_1_SIZE\t\t(gd->bd->bi_dram[0].size)\n+#define PHYS_SDRAM_1_SIZE\t\t(gd->dram[0].size)\n #define PHYS_SDRAM_2\t\t\tCSD1_BASE_ADDR\n-#define PHYS_SDRAM_2_SIZE\t\t(gd->bd->bi_dram[1].size)\n+#define PHYS_SDRAM_2_SIZE\t\t(gd->dram[1].size)\n #define PHYS_SDRAM_SIZE\t\t\t(gd->ram_size)\n\n #define CFG_SYS_SDRAM_BASE\t\t(PHYS_SDRAM_1)\ndiff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h\nindex 14095b99f034..acd6eb6f8ac3 100644\n--- a/include/configs/mx53loco.h\n+++ b/include/configs/mx53loco.h\n@@ -86,9 +86,9 @@\n\n /* Physical Memory Map */\n #define PHYS_SDRAM_1\t\t\tCSD0_BASE_ADDR\n-#define PHYS_SDRAM_1_SIZE\t\t(gd->bd->bi_dram[0].size)\n+#define PHYS_SDRAM_1_SIZE\t\t(gd->dram[0].size)\n #define PHYS_SDRAM_2\t\t\tCSD1_BASE_ADDR\n-#define PHYS_SDRAM_2_SIZE\t\t(gd->bd->bi_dram[1].size)\n+#define PHYS_SDRAM_2_SIZE\t\t(gd->dram[1].size)\n #define PHYS_SDRAM_SIZE\t\t\t(gd->ram_size)\n\n #define CFG_SYS_SDRAM_BASE\t\t(PHYS_SDRAM_1)\ndiff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h\nindex 3707de254e14..65babf50546d 100644\n--- a/include/configs/mx53ppd.h\n+++ b/include/configs/mx53ppd.h\n@@ -81,9 +81,9 @@\n\n /* Physical Memory Map */\n #define PHYS_SDRAM_1\t\t\tCSD0_BASE_ADDR\n-#define PHYS_SDRAM_1_SIZE\t\t(gd->bd->bi_dram[0].size)\n+#define PHYS_SDRAM_1_SIZE\t\t(gd->dram[0].size)\n #define PHYS_SDRAM_2\t\t\tCSD1_BASE_ADDR\n-#define PHYS_SDRAM_2_SIZE\t\t(gd->bd->bi_dram[1].size)\n+#define PHYS_SDRAM_2_SIZE\t\t(gd->dram[1].size)\n #define PHYS_SDRAM_SIZE\t\t\t(gd->ram_size)\n\n #define CFG_SYS_SDRAM_BASE\t\t(PHYS_SDRAM_1)\ndiff --git a/include/fdtdec.h b/include/fdtdec.h\nindex c43e78de4147..917dfaaa6740 100644\n--- a/include/fdtdec.h\n+++ b/include/fdtdec.h\n@@ -57,6 +57,7 @@ struct fdt_memory {\n };\n\n struct bd_info;\n+struct global_data;\n\n /**\n * enum fdt_source_t - indicates where the devicetree came from\n@@ -990,7 +991,7 @@ int fdtdec_setup_mem_size_base_lowest(void);\n int fdtdec_setup_mem_ram_top(void);\n\n /**\n- * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram\n+ * fdtdec_setup_memory_banksize() - decode and populate gd->dram\n *\n * Decode the /memory 'reg' property to determine the address and size of the\n * memory banks. Use this data to populate the global data board info with the\n@@ -1272,12 +1273,12 @@ int board_fdt_blob_setup(void **fdtp);\n * @param basep\t\tReturns base address of first memory bank (NULL to\n *\t\t\tignore)\n * @param sizep\t\tReturns total memory size (NULL to ignore)\n- * @param bd\t\tUpdated with the memory bank information (NULL to skip)\n+ * @param gd_ptr\tUpdated with the memory bank information (NULL to skip)\n * Return: 0 if OK, -ve on error\n */\n int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,\n \t\t\t phys_addr_t *basep, phys_size_t *sizep,\n-\t\t\t struct bd_info *bd);\n+\t\t\t struct global_data *gd_ptr);\n\n /**\n * fdtdec_get_srcname() - Get the name of where the devicetree comes from\ndiff --git a/include/init.h b/include/init.h\nindex c31ebd83b85e..2fc9ee783603 100644\n--- a/include/init.h\n+++ b/include/init.h\n@@ -80,7 +80,7 @@ int dram_init(void);\n * dram_init_banksize() - Set up DRAM bank sizes\n *\n * This can be implemented by boards to set up the DRAM bank information in\n- * gd->bd->bi_dram(). It is called just before relocation, after dram_init()\n+ * gd->dram(). It is called just before relocation, after dram_init()\n * is called.\n *\n * If this is not provided, a default implementation will try to set up a\ndiff --git a/lib/fdtdec.c b/lib/fdtdec.c\nindex 288966936606..1d00b3688de3 100644\n--- a/lib/fdtdec.c\n+++ b/lib/fdtdec.c\n@@ -35,6 +35,7 @@\n #include <linux/ctype.h>\n #include <linux/lzo.h>\n #include <linux/ioport.h>\n+#include <asm/global_data.h>\n\n DECLARE_GLOBAL_DATA_PTR;\n\n@@ -1150,13 +1151,13 @@ static int fdtdec_setup_mem_for_each_bank(void (*bankfn)(struct resource *res, i\n\n static void fdtdec_setup_memory_banksize_bankfn(struct resource *res, int bank)\n {\n-\tgd->bd->bi_dram[bank].start = (phys_addr_t)res->start;\n-\tgd->bd->bi_dram[bank].size = (phys_size_t)(res->end - res->start + 1);\n+\tgd->dram[bank].start = (phys_addr_t)res->start;\n+\tgd->dram[bank].size = (phys_size_t)(res->end - res->start + 1);\n\n \tdebug(\"%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\\n\",\n \t __func__, bank,\n-\t (unsigned long long)gd->bd->bi_dram[bank].start,\n-\t (unsigned long long)gd->bd->bi_dram[bank].size);\n+\t (unsigned long long)gd->dram[bank].start,\n+\t (unsigned long long)gd->dram[bank].size);\n }\n\n int fdtdec_setup_memory_banksize(void)\n@@ -1825,7 +1826,7 @@ int fdtdec_resetup(int *rescan)\n\n int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,\n \t\t\t phys_addr_t *basep, phys_size_t *sizep,\n-\t\t\t struct bd_info *bd)\n+\t\t\t gd_t *gd_ptr)\n {\n \tint addr_cells, size_cells;\n \tconst u32 *cell, *end;\n@@ -1877,8 +1878,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,\n \t}\n \t/* Note: if no matching subnode was found we use the parent node */\n\n-\tif (bd) {\n-\t\tmemset(bd->bi_dram, '\\0', sizeof(bd->bi_dram[0]) *\n+\tif (gd_ptr) {\n+\t\tmemset(gd_ptr->dram, '\\0', sizeof(gd_ptr->dram[0]) *\n \t\t\t\t\t\tCONFIG_NR_DRAM_BANKS);\n \t}\n\n@@ -1894,8 +1895,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,\n \t\tif (addr_cells == 2)\n \t\t\taddr += (u64)fdt32_to_cpu(*cell++) << 32UL;\n \t\taddr += fdt32_to_cpu(*cell++);\n-\t\tif (bd)\n-\t\t\tbd->bi_dram[bank].start = addr;\n+\t\tif (gd_ptr)\n+\t\t\tgd_ptr->dram[bank].start = addr;\n \t\tif (basep && !bank)\n \t\t\t*basep = (phys_addr_t)addr;\n\n@@ -1917,8 +1918,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,\n \t\t\t}\n \t\t}\n\n-\t\tif (bd)\n-\t\t\tbd->bi_dram[bank].size = size;\n+\t\tif (gd_ptr)\n+\t\t\tgd_ptr->dram[bank].size = size;\n \t\ttotal_size += size;\n \t}\n\ndiff --git a/lib/lmb.c b/lib/lmb.c\nindex 8f12c6ad8e59..2364cb767472 100644\n--- a/lib/lmb.c\n+++ b/lib/lmb.c\n@@ -554,12 +554,12 @@ static void lmb_reserve_uboot_region(void)\n #endif\n\n \tfor (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {\n-\t\tif (!gd->bd->bi_dram[bank].size ||\n-\t\t rsv_start < gd->bd->bi_dram[bank].start)\n+\t\tif (!gd->dram[bank].size ||\n+\t\t rsv_start < gd->dram[bank].start)\n \t\t\tcontinue;\n \t\t/* Watch out for RAM at end of address space! */\n-\t\tbank_end = gd->bd->bi_dram[bank].start +\n-\t\t\tgd->bd->bi_dram[bank].size - 1;\n+\t\tbank_end = gd->dram[bank].start +\n+\t\t\tgd->dram[bank].size - 1;\n \t\tif (rsv_start > bank_end)\n \t\t\tcontinue;\n \t\tif (bank_end > end)\n@@ -613,7 +613,6 @@ static void lmb_add_memory(void)\n \tint i;\n \tphys_size_t size;\n \tu64 ram_top = gd->ram_top;\n-\tstruct bd_info *bd = gd->bd;\n\n \tif (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP))\n \t\treturn lmb_arch_add_memory();\n@@ -623,10 +622,10 @@ static void lmb_add_memory(void)\n \t\tram_top = 0x100000000ULL;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n-\t\tsize = bd->bi_dram[i].size;\n+\t\tsize = gd->dram[i].size;\n\n \t\tif (size)\n-\t\t\tlmb_add(bd->bi_dram[i].start, size);\n+\t\t\tlmb_add(gd->dram[i].start, size);\n \t}\n }\n\ndiff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c\nindex c3a3519d16d4..e1b9b0cd8c30 100644\n--- a/test/cmd/bdinfo.c\n+++ b/test/cmd/bdinfo.c\n@@ -138,16 +138,15 @@ static int lmb_test_dump_all(struct unit_test_state *uts)\n\n static int bdinfo_check_mem(struct unit_test_state *uts)\n {\n-\tstruct bd_info *bd = gd->bd;\n \tint i;\n\n \tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {\n-\t\tif (bd->bi_dram[i].size) {\n+\t\tif (gd->dram[i].size) {\n \t\t\tut_assertok(test_num_l(uts, \"DRAM bank\", i));\n \t\t\tut_assertok(test_num_ll(uts, \"-> start\",\n-\t\t\t\t\t\tbd->bi_dram[i].start));\n+\t\t\t\t\t\tgd->dram[i].start));\n \t\t\tut_assertok(test_num_ll(uts, \"-> size\",\n-\t\t\t\t\t\tbd->bi_dram[i].size));\n+\t\t\t\t\t\tgd->dram[i].size));\n \t\t}\n \t}\n\n", "prefixes": [ "v3", "3/6" ] }