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GET /api/patches/2228733/?format=api
{ "id": 2228733, "url": "http://patchwork.ozlabs.org/api/patches/2228733/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-27T09:26:10", "name": "[v2,6/7] drivers: ufs: qcom: Initialize and enable clocks before hardware access", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b3b800aa7110a6aa3b9ef10f85d915912d932441", "submitter": { "id": 90810, "url": "http://patchwork.ozlabs.org/api/people/90810/?format=api", "name": "Balaji Selvanathan", "email": "balaji.selvanathan@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com/mbox/", "series": [ { "id": 501613, "url": "http://patchwork.ozlabs.org/api/series/501613/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501613", "date": "2026-04-27T09:26:04", "name": "Add UFS clock support for Qualcomm SoCs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501613/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228733/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228733/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=YjMJw99T;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=F8AUMsHZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"YjMJw99T\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"F8AUMsHZ\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=balaji.selvanathan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3yrZ3pSTz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 19:27:10 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 7089384119;\n\tMon, 27 Apr 2026 11:26:52 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id E044184119; Mon, 27 Apr 2026 11:26:50 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id AB58C84310\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 11:26:48 +0200 (CEST)", "from pps.filterd (m0279868.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63R8TCoe4054507\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 09:26:47 GMT", "from mail-pf1-f199.google.com (mail-pf1-f199.google.com\n [209.85.210.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4drnkxdfmq-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 09:26:47 +0000 (GMT)", "by mail-pf1-f199.google.com with SMTP id\n d2e1a72fcca58-82f07078eaaso7643183b3a.0\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 02:26:46 -0700 (PDT)", "from hu-bselvana-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com>", "References": "<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>", "In-Reply-To": "<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>", "To": "u-boot@lists.denx.de, Sumit Garg <sumit.garg@kernel.org>,\n u-boot-qcom@groups.io", "Cc": "Lukasz Majewski <lukma@denx.de>, Tom Rini <trini@konsulko.com>,\n Casey Connolly <casey.connolly@linaro.org>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n David Wronek <david.wronek@mainlining.org>,\n Jens Reidel <adrian@mainlining.org>, Luca Weiss <luca.weiss@fairphone.com>,\n Swathi Tamilselvan <swathi.tamilselvan@oss.qualcomm.com>,\n Aswin Murugan <aswin.murugan@oss.qualcomm.com>,\n Bhupesh Sharma <bhupesh.linux@gmail.com>,\n Neha Malcom Francis <n-francis@ti.com>,\n Julien Stephan <jstephan@baylibre.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; 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When these bootloaders failed to do so,\nUFS registers became inaccessible, causing initialization to fail.\nThis change makes U-Boot initialize and enable UFS clocks early\nin the init sequence, removing the dependency on previous\nbootloaders.\n\nSigned-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>\n---\nChanges in v2:\n- Remove ufs_qcom_init_clks function and move the clock enabling and\n rate set codes to ufs_qcom_init\n- Add clk_release_bulk if ufs_qcom_enable_clks fails\n---\n drivers/ufs/ufs-qcom.c | 53 ++++++++++++++++++++++++++++++++++----------------\n 1 file changed, 36 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c\nindex dc40ee62daf..ae33f62fbee 100644\n--- a/drivers/ufs/ufs-qcom.c\n+++ b/drivers/ufs/ufs-qcom.c\n@@ -30,6 +30,7 @@\n #define UFS_CPU_MAX_BANDWIDTH\t819200\n \n static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable);\n+static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba);\n \n static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)\n {\n@@ -47,17 +48,6 @@ static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)\n \treturn 0;\n }\n \n-static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv)\n-{\n-\tint err;\n-\tstruct udevice *dev = priv->hba->dev;\n-\n-\terr = clk_get_bulk(dev, &priv->clks);\n-\tif (err)\n-\t\treturn err;\n-\n-\treturn 0;\n-}\n \n static int ufs_qcom_check_hibern8(struct ufs_hba *hba)\n {\n@@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable)\n static int ufs_qcom_init(struct ufs_hba *hba)\n {\n \tstruct ufs_qcom_priv *priv = dev_get_priv(hba->dev);\n+\tstruct udevice *dev = hba->dev;\n+\tstruct clk clk;\n+\tu32 max_freq;\n+\tlong rate;\n \tint err;\n \n \tpriv->hba = hba;\n \n+\t/* Get maximum frequency for core_clk_unipro from device tree */\n+\tmax_freq = ufs_qcom_get_core_clk_unipro_max_freq(hba);\n+\n+\t/* Get and configure core_clk_unipro */\n+\terr = clk_get_by_name(dev, \"core_clk_unipro\", &clk);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to get core_clk_unipro: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\trate = clk_set_rate(&clk, max_freq);\n+\tif (rate < 0) {\n+\t\tdev_err(dev, \"Failed to set core_clk_unipro rate to %u Hz: %ld\\n\",\n+\t\t\tmax_freq, rate);\n+\t}\n+\n+\t/* Get all clocks */\n+\terr = clk_get_bulk(dev, &priv->clks);\n+\tif (err) {\n+\t\tdev_err(dev, \"clk_get_bulk failed: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\t/* Enable clocks */\n+\terr = ufs_qcom_enable_clks(priv);\n+\tif (err) {\n+\t\tdev_err(dev, \"failed to enable clocks: %d\\n\", err);\n+\t\tclk_release_bulk(&priv->clks);\n+\t\treturn err;\n+\t}\n+\n \t/* setup clocks */\n \tufs_qcom_setup_clocks(hba, true, PRE_CHANGE);\n \n@@ -579,12 +604,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)\n \t\t priv->hw_ver.minor,\n \t\t priv->hw_ver.step);\n \n-\terr = ufs_qcom_init_clks(priv);\n-\tif (err) {\n-\t\tdev_err(hba->dev, \"failed to initialize clocks, err:%d\\n\", err);\n-\t\treturn err;\n-\t}\n-\n \tufs_qcom_advertise_quirks(hba);\n \tufs_qcom_setup_clocks(hba, true, POST_CHANGE);\n \n", "prefixes": [ "v2", "6/7" ] }