Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2228732/?format=api
{ "id": 2228732, "url": "http://patchwork.ozlabs.org/api/patches/2228732/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-27T09:26:09", "name": "[v2,5/7] clk: qcom: sc7280: Add UFS clock support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ff613a5bfa8aee87902440736da45c42c24a2a04", "submitter": { "id": 90810, "url": "http://patchwork.ozlabs.org/api/people/90810/?format=api", "name": "Balaji Selvanathan", "email": "balaji.selvanathan@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com/mbox/", "series": [ { "id": 501613, "url": "http://patchwork.ozlabs.org/api/series/501613/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501613", "date": "2026-04-27T09:26:04", "name": "Add UFS clock support for Qualcomm SoCs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501613/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228732/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228732/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ERxshGxe;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=P3yJgFnV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"ERxshGxe\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"P3yJgFnV\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=balaji.selvanathan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3yrQ3fJmz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 19:27:02 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 34421842EF;\n\tMon, 27 Apr 2026 11:26:47 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id B1330842CE; Mon, 27 Apr 2026 11:26:45 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 715B5842EF\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 11:26:43 +0200 (CEST)", "from pps.filterd (m0279869.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63R8TA181501431\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 09:26:42 GMT", "from mail-pf1-f199.google.com (mail-pf1-f199.google.com\n [209.85.210.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4drnqrne0s-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 09:26:41 +0000 (GMT)", "by mail-pf1-f199.google.com with SMTP id\n d2e1a72fcca58-82fa2165c3eso6119431b3a.0\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 02:26:41 -0700 (PDT)", "from hu-bselvana-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19])\n by smtp.gmail.com with ESMTPSA id\n d2e1a72fcca58-82f8e9819fesm31903133b3a.4.2026.04.27.02.26.35\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 27 Apr 2026 02:26:40 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=qcppdkim1; bh=\n iniVKzhcpPyiZN7o5tUgItYQ+lNVZn6uv3VwDDI8Utg=; b=ERxshGxe/+oBjcjr\n +c7jso57T8QAgJhaHjqp5c+cnRKLlu6GvOMIXcNWL3XgqrOyBGHDZfQ0Df+0lMa+\n JNSbtBV/QupqoBNPZKs/0+EqgQSgHKQN95f1rI2pS4cAa/IdHZzQktSuUaHdgXDn\n Nq3gwU/81hvV01EIwneRvflDMvwwVDmtCxby5DAvO5x1i0F3N0dBmL+1jW+Co654\n HleviRGK3GtP9bI6xZGNEdrZRsEIpAZHYwq4Y4xTrGOB8UEHfbRkqn/g6yzbBTwF\n 7Iusz91Ak5+Z0/vbAmHMjl3BkTyIQy0M/kGxlXFJvMm7RUXhqlXJHHNqFeZ3kNCY\n 65VovA==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1777282001; x=1777886801; darn=lists.denx.de;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to; bh=iniVKzhcpPyiZN7o5tUgItYQ+lNVZn6uv3VwDDI8Utg=;\n b=P3yJgFnVTf1yXm+NkHn2Gg+QlMLB1o5lpZL5GS+8HTbC5pY1WeLKDomuciQyNe0Bo+\n O/Ugf1fYK4Qn4EjxV8cn9LFKkOodhGbG7xwwBe4GHGKDN0SwPgn19dMgTRWS/Z9kIZFi\n Xv2CJdyR2CCqQIUR6yOFV/wclezRYnL8G8qRxW43t6+38A8/Dypi3P1UNCAJTxhnuPDx\n WyRAameWMairwnUVN9IY3AoU6rWMDSKD7vIeQAQbbviJtDN+0Jqmr70YxT9ci5Rv/ZP9\n LFu1F6xT21zvqgRIcBvRHQgXUZUd8I0/Twnt1Cp+2uiOD3AJpaZfcJ33hebfgVJlr+GE\n ljjw==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777282001; x=1777886801;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=iniVKzhcpPyiZN7o5tUgItYQ+lNVZn6uv3VwDDI8Utg=;\n b=G0OtiyzVNMKMRjVvSaRLOJ0aXzP43VP8MnhNfv+NPoFgOTfc2rmCpWRRgsAaPr3jc9\n lJyzWJaQZ4g5uuzxMfZtw++M9Szj/CvNFEHkD9jBEDJlo/LQFm2mjRfoIScI11HJ7kvF\n xPrhyvZUDPfq1a7qWUusL/M6pKWBOF/vIA1BqEKrSJPrUJlprYSlgRLgGR05YZD4cvIJ\n 6O3g6qux53qq88IFCRcYO63W2M4Y42nh1ThpF0erLKdQBUfFF6QcKE6bHppFfYqhgIMP\n BZGeiYA1qks2u8CbnLZVJvxN1hvtkf/CjlyVwkAusGM3LsDmImQFYWJ+jCH2k4N/1nBn\n 1r3w==", "X-Gm-Message-State": "AOJu0Yy1ejIGFSLUQBEIe0tCj2SQxg+xZ3eFzFY7jiJH7Q5pturzjdYy\n UNUYcVAMqQPArXvVC9HaANocWghveM0CYuVOCG9pBIidnle8kh86G5rqIvK0K+ezPkLlZERU/n0\n Ra+5UUZuCOC36tzWmnGhYHVZwnrDpwr170vJEUVotuwLvPmwc7O8LXy3D", "X-Gm-Gg": "AeBDiesbW573leXn/EO8TJ47ncdhem7vf1RB7oYKV0AfTL3yDXCVVmJbGOzdEJD8nzW\n oanCTs09ZME5pF3BOHbSfhq1e7k53oxDEi/vPw0Wnt4swKCEGwE+5wRAjiSRy6fpflnAS2JyjLn\n 80FrOfuJ9pX5MlI1lyoi6gW/4V8Ij3Qxsck6w/Se9ai1bECDtX7LeoWTNvkxuLpMNfJ0Vrm5BiI\n CPiUno9ojgdP+j6fE57Q+nSdamE9k2IryNjIz2TjmFK92fVKdSC/M2B99WtBfw5KBi58sazcNsb\n WpzoNoJhXKJJQLezKDFZSBZyub3dGnVs6smD57qypfCBPcg1jC/FGLbC9pgeO2ZMeK5pqEHMEt9\n /tdrs4lfbKpSXL59OMQ8yYJQqc8hv26Jvi5ibHpUimvGhfx06aeL8EQjRkkDG6sOfz7lL3FP0k+\n fFI7RAxQjYbTVzgEnUMbNqyq7/3Lb0tRRoDbD/47e8lj00wMhpLRF3JrneXA0H", "X-Received": [ "by 2002:a05:6a00:92a7:b0:827:4bca:f1a2 with SMTP id\n d2e1a72fcca58-82f8c87e27fmr41804644b3a.10.1777282000802;\n Mon, 27 Apr 2026 02:26:40 -0700 (PDT)", "by 2002:a05:6a00:92a7:b0:827:4bca:f1a2 with SMTP id\n d2e1a72fcca58-82f8c87e27fmr41804608b3a.10.1777282000328;\n Mon, 27 Apr 2026 02:26:40 -0700 (PDT)" ], "From": "Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>", "Date": "Mon, 27 Apr 2026 14:56:09 +0530", "Subject": "[PATCH v2 5/7] clk: qcom: sc7280: Add UFS clock support", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com>", "References": "<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>", "In-Reply-To": "<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>", "To": "u-boot@lists.denx.de, Sumit Garg <sumit.garg@kernel.org>,\n u-boot-qcom@groups.io", "Cc": "Lukasz Majewski <lukma@denx.de>, Tom Rini <trini@konsulko.com>,\n Casey Connolly <casey.connolly@linaro.org>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n David Wronek <david.wronek@mainlining.org>,\n Jens Reidel <adrian@mainlining.org>, Luca Weiss <luca.weiss@fairphone.com>,\n Swathi Tamilselvan <swathi.tamilselvan@oss.qualcomm.com>,\n Aswin Murugan <aswin.murugan@oss.qualcomm.com>,\n Bhupesh Sharma <bhupesh.linux@gmail.com>,\n Neha Malcom Francis <n-francis@ti.com>,\n Julien Stephan <jstephan@baylibre.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>,\n Sumit Garg <sumit.garg@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777281967; l=3878;\n i=balaji.selvanathan@oss.qualcomm.com; s=20260213; h=from:subject:message-id;\n bh=nnSDAdUzhEYg5qXPlhXxxO5xcXi/9sOmp6rgKApLAA8=;\n b=xXBBa1lBVQOUAcgZ6dfAZqVbPGg4ZG8UUMFVw60iCTzLOv2glflmA8v97nJ6ZCRfeSjOoPDy3\n hK2z5RCldTLDDEY1srMDytmXXyHMyl0Ctqt2ghOX6p7VjrrkViJbCqw", "X-Developer-Key": "i=balaji.selvanathan@oss.qualcomm.com; a=ed25519;\n pk=CDpYiUU3SH7KGEtsBvY2tBGPiWfMxqWJF0p2LftOfnc=", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI3MDEwMCBTYWx0ZWRfX83EB6q+tZKH2\n Skg+/s43xmLYoDntplg2XHIUW8jrVjT+ZcSOsazXj4KmCeBn2yzetj/ddVB4pG1QkPArp+QQl4t\n PBDPZPO+QC13KDWXz20NgRYnwpLozsg2P5n7KeFAZG8+aPF+nLrzT7I90PCrrymkC7/5KkG819U\n 9Qqgf4FenxTE7o+Do+dhHiX27J/wGp44d/SK79habpFGPZ7lcyb2L2uOkIO0L5L0DTrQ4uaYxoP\n +m4YguZrnqh8FOiYXFSSGiqlGfZDtuqx6lD6OGlk6IZ5/4h/gX/ChAh0P/slY6TjYWfV7rgCWVa\n KNYOtz5t6L55grwG2CHMIgnDHO/YSbvWWLYQzwebXXCtd0T16f/tV5EZzdPf+PqU8+fwJ6yyxW5\n GysYxKyZm97oLlh6P2oHRhhiCjjPw8Wt/hP6UpS88ocKUoFo1ylI66g+wGcbLuUC1trokP4r7qH\n AgM+6oJABNh97qZitlA==", "X-Proofpoint-ORIG-GUID": "4rBX8wLFCEMmm0P1wZImL_wqkm6GNaEl", "X-Proofpoint-GUID": "4rBX8wLFCEMmm0P1wZImL_wqkm6GNaEl", "X-Authority-Analysis": "v=2.4 cv=UcthjqSN c=1 sm=1 tr=0 ts=69ef2bd1 cx=c_pps\n a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22\n a=EUspDBNiAAAA:8 a=lctD2BjJw215xePkaksA:9 a=QEXdDO2ut3YA:10\n a=OpyuDcXvxspvyRM73sMx:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-27_02,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0\n adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add UFS clock support for sc7280 including register definitions,\nrate configuration, and gate clocks.\n\nReviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>\nSigned-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>\n---\nChanges in v2:\n- No changes\n---\n drivers/clk/qcom/clock-sc7280.c | 52 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 52 insertions(+)", "diff": "diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c\nindex 7b6ed826023..2c73c26484f 100644\n--- a/drivers/clk/qcom/clock-sc7280.c\n+++ b/drivers/clk/qcom/clock-sc7280.c\n@@ -23,6 +23,10 @@\n #define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058\n #define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c\n #define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054\n+#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024\n+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c\n+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0\n+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084\n \n static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {\n \tF(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),\n@@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {\n \t{ }\n };\n \n+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {\n+\tF(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),\n+\t{ }\n+};\n+\n+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),\n+\t{ }\n+};\n+\n+static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {\n+\tF(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),\n+\t{ }\n+};\n+\n+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),\n+\t{ }\n+};\n+\n static ulong sc7280_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)\n \tcase GCC_PCIE1_PHY_RCHNG_CLK:\n \t\tclk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);\n \t\treturn 100000000;\n+\tcase GCC_UFS_PHY_AXI_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_ICE_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_PHY_AUX_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_UNIPRO_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n \tdefault:\n \t\treturn rate;\n \t}\n@@ -147,6 +198,7 @@ static const struct gate_clk sc7280_clks[] = {\n \tGATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),\n \tGATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)),\n", "prefixes": [ "v2", "5/7" ] }