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GET /api/patches/2228731/?format=api
{ "id": 2228731, "url": "http://patchwork.ozlabs.org/api/patches/2228731/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-27T09:26:08", "name": "[v2,4/7] clk: qcom: qcs615: Add UFS clock support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "58e6fbc1eef745f55c1cdf4473c596ded89e10bb", "submitter": { "id": 90810, "url": "http://patchwork.ozlabs.org/api/people/90810/?format=api", "name": "Balaji Selvanathan", "email": "balaji.selvanathan@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com/mbox/", "series": [ { "id": 501613, "url": "http://patchwork.ozlabs.org/api/series/501613/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501613", "date": "2026-04-27T09:26:04", "name": "Add UFS clock support for Qualcomm SoCs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501613/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228731/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228731/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=k0MhkBai;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=UpPNHqkg;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"k0MhkBai\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"UpPNHqkg\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=balaji.selvanathan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3yrF3P7Mz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 19:26:53 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D0652842D7;\n\tMon, 27 Apr 2026 11:26:41 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id AB81A842C7; Mon, 27 Apr 2026 11:26:40 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 75E3C83693\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 11:26:38 +0200 (CEST)", "from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63R8T7IL3639521\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 09:26:37 GMT", "from mail-pg1-f198.google.com (mail-pg1-f198.google.com\n [209.85.215.198])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dsya01epp-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 09:26:36 +0000 (GMT)", "by mail-pg1-f198.google.com with SMTP id\n 41be03b00d2f7-c79907d4c57so3185074a12.0\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 02:26:36 -0700 (PDT)", "from hu-bselvana-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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"text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com>", "References": "<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>", "In-Reply-To": "<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>", "To": "u-boot@lists.denx.de, Sumit Garg <sumit.garg@kernel.org>,\n u-boot-qcom@groups.io", "Cc": "Lukasz Majewski <lukma@denx.de>, Tom Rini <trini@konsulko.com>,\n Casey Connolly <casey.connolly@linaro.org>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n David Wronek <david.wronek@mainlining.org>,\n Jens Reidel <adrian@mainlining.org>, Luca Weiss <luca.weiss@fairphone.com>,\n Swathi Tamilselvan <swathi.tamilselvan@oss.qualcomm.com>,\n Aswin Murugan <aswin.murugan@oss.qualcomm.com>,\n Bhupesh Sharma <bhupesh.linux@gmail.com>,\n Neha Malcom Francis <n-francis@ti.com>,\n Julien Stephan <jstephan@baylibre.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Balaji Selvanathan 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priorityscore=1501 malwarescore=0 impostorscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604270100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add UFS clock support for qcs615 including register definitions,\nrate configuration, and gate clocks.\n\nReviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>\nSigned-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>\n---\nChanges in v2:\n- No changes\n---\n drivers/clk/qcom/clock-qcs615.c | 63 ++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 62 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c\nindex 2087fc38f63..7b3fe49de9c 100644\n--- a/drivers/clk/qcom/clock-qcs615.c\n+++ b/drivers/clk/qcom/clock-qcs615.c\n@@ -19,6 +19,11 @@\n #define USB30_PRIM_MASTER_CLK_CMD_RCGR\t\t0xf01c\n #define USB3_PRIM_PHY_AUX_CMD_RCGR\t\t0xf060\n \n+#define UFS_PHY_AXI_CLK_CMD_RCGR\t\t0x77020\n+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR\t\t0x77048\n+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR\t0x77060\n+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR\t\t0x7707c\n+\n #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)\n #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)\n #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)\n@@ -33,9 +38,37 @@\n #define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26)\n #define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27)\n \n+/* UFS PHY AXI clock frequency table */\n+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {\n+\tF(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),\n+\tF(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),\n+\tF(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),\n+\tF(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),\n+\tF(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),\n+\t{ }\n+};\n+\n+/* UFS PHY ICE CORE clock frequency table */\n+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {\n+\tF(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n+/* UFS PHY UNIPRO CORE clock frequency table */\n+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {\n+\tF(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),\n+\tF(75000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),\n+\t{ }\n+};\n+\n static ulong qcs615_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct freq_tbl *freq;\n \n \tif (clk->id < priv->data->num_clks)\n \t\tdebug(\"%s: %s, requested rate=%ld\\n\", __func__,\n@@ -52,6 +85,24 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)\n \t\t\t\t 5, 0, 0, CFG_CLK_SRC_GPLL0, 8);\n \t\tclk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);\n \t\treturn rate;\n+\tcase GCC_UFS_PHY_AXI_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_UNIPRO_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_ICE_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_PHY_AUX_CLK:\n+\t\tclk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);\n+\t\treturn 19200000;\n \tdefault:\n \t\treturn 0;\n \t}\n@@ -81,7 +132,17 @@ static const struct gate_clk qcs615_clks[] = {\n \tGATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),\n \tGATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),\n \tGATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),\n-\tGATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0))\n+\tGATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),\n+\t/* UFS clocks */\n+\tGATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),\n+\tGATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)),\n+\tGATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),\n };\n \n static int qcs615_enable(struct clk *clk)\n", "prefixes": [ "v2", "4/7" ] }