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GET /api/patches/2228665/?format=api
{ "id": 2228665, "url": "http://patchwork.ozlabs.org/api/patches/2228665/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260427080642.371531-3-artemiy.volkov@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260427080642.371531-3-artemiy.volkov@arm.com>", "list_archive_url": null, "date": "2026-04-27T08:06:09", "name": "[2/4] aarch64: initialize vectors from starting subsequence", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fb5bed69d30b5714b247dc8f27af96c6d0e28cee", "submitter": { "id": 91911, "url": "http://patchwork.ozlabs.org/api/people/91911/?format=api", "name": "Artemiy Volkov", "email": "artemiy.volkov@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260427080642.371531-3-artemiy.volkov@arm.com/mbox/", "series": [ { "id": 501601, "url": "http://patchwork.ozlabs.org/api/series/501601/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501601", "date": "2026-04-27T08:06:07", "name": "aarch64: vector initialization improvements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501601/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228665/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228665/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=FuEf0xWH;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=FuEf0xWH;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Artemiy Volkov <artemiy.volkov@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<tamar.christina@arm.com>, <wilco.dijkstra@arm.com>,\n <andrew.pinski@oss.qualcomm.com>, <richard.earnshaw@arm.com>,\n <ktkachov@nvidia.com>, <alice.carlotti@arm.com>, <alex.coplan@arm.com>,\n Artemiy Volkov <artemiy.volkov@arm.com>", "Subject": "[PATCH 2/4] aarch64: initialize vectors from starting subsequence", "Date": "Mon, 27 Apr 2026 08:06:09 +0000", "Message-ID": "<20260427080642.371531-3-artemiy.volkov@arm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427080642.371531-1-artemiy.volkov@arm.com>", "References": "<20260427080642.371531-1-artemiy.volkov@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n AM2PEPF0001C711:EE_|GV1PR08MB10854:EE_|AM1PEPF000252E0:EE_|MRWPR08MB11236:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6b2ebefb-81ee-47d3-c478-08dea43426ae", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|82310400026|1800799024|376014|36860700016|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info-Original": "\n E02qG3R/vTtIADTWqtk8fUrAOZSI0F4h3Y1PyJEN5EAJR/F+v8VSEgl7Pw5KNzSq4SCFK9vfd2pk11JT0xzGgfl+bT2tfd8cEyE7uuvxBnzW7vbnYmuetCWRd/9fo1h+xHxz2wRyyQt4lgYf/AZYCpgxDNmAP7EPscMRsUW7I+/B3OHx8skG9qZyQfmFnR2A/gVujMUfmzXz9svEJtriyZ3s8oD/kcjhMH9iGJkfIFZ9qlVOY2XDH29RpXHmo7BeGVgZ2fUgqhMXjqjzUQBrV3CyhHaEuq28n49gpoBsksimjkmlZdTvAw1Ou9nXYItbmz3oQM/WeQT+yFRLYQ4Gr9hKlFb2o7Yon7PtXZ7KZUsqVTdi2XznsJnuOtheDZD5Rf83/l2BAboNTOgJv03oXkqLXRl1/HSY3UN5kjjdleBdEH7L1WkVzQv1A5szv1KDg3uBNkpQyJ+KFvYbCYLB9guWOT3vZ8qrGHj2XGl/PR40/XFvkgHoWEwiMhTovvjbJJ9YoZYL1R/Qb94QIMZrsHAE3na+KjgoIXmyoTgAuD1+TfebKeWzkhPeJoF7Wzo744b/VTZ90EqTREXJtY4x2m9+Mu1E4Y0IESUYD6j6pbldvQWsl77VymZX+Zk6DBn0hdfOdzPLAsFHYZ+1qg3LX2hVmTyumd+hLDTOJEaGLlLO8QNKNn0yt/kVc6EFDxuQqjgb1Zm4J0LUvXIFqaOuhA0UrOCmRmReBAkhbMZuL/k=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM1PEPF000252E0.eurprd07.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Now that we have 2- and 4-element vector modes for all the sub-word scalar\nmodes, we can emit more efficient code when the elements of a vector\nconstructor can be generated from a common starting subsequence of length\npower of two. To do this, first detect the shortest possible starting\nsubsequence by repeatedly folding the initial constructor element array\nin half, as long as the left and the right halves are equal. Afterwards,\nafter emitting the subsequence, duplicate it by generating a\nvec_duplicate with the correct source mode.\n\nOn the MD side, this requires implementing the vec_duplicate optab to\nduplicate an arbitrary sub-128-bit value into a full 64- or a 128-bit\nAdvSIMD register, as well as the vec_set insn for the VSUB64 modes (needed\nas fallback for the divide-and-conquer approach). The latter uses a\nproperly scaled and shifted \"bfi\" for integer values, and a properly\nindexed \"ins\" for FP elements.\n\nThis change allows us to get rid of long chains of inserts and compile\nthings like:\n\nint16x8_t f (int16_t x, int16_t y, int16_t z, int16_t w)\n{\n\treturn (int16x8_t) {x, y, z, w, x, y, z, w};\n}\n\ninto:\n\tbfi w0, w2, 16, 16\n\tbfi w1, w3, 16, 16\n\tdup v31.2s, w0\n\tdup v0.2s, w1\n\tzip1 v0.8h, v31.8h, v0.8h\n\tret\n\nrather than:\n\n\tdup v31.4h, w0\n\tdup v0.4h, w1\n\tins v31.h[1], w2\n\tins v0.h[1], w3\n\tins v31.h[3], w2\n\tins v0.h[3], w3\n\tzip1 v0.8h, v31.8h, v0.8h\n\tret\n\nThis patch also includes an extensive new test, which includes the above\ncase, as well as adjustments to existing codegen tests as necessary.\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-simd.md (*aarch64_simd_dup_subvector<VQ:mode><VDUP:mode>):\n\tNew insn pattern.\n\t(*aarch64_simd_dup_subvector<VD:mode><VDUP:mode>): Likewise.\n\t(@aarch64_simd_vec_set<mode>): Likewise.\n\t(vec_set<mode>): Handle 16- and 32-bit vector modes in the expander.\n\t* config/aarch64/aarch64.cc (aarch64_choose_vector_init_constant):\n\tHandle 16- and 32-bit vector modes.\n\t(aarch64_expand_vector_init_fallback): Add logic to initialize vector\n\tfrom starting subsequence. Make static.\n\t(scalar_move_insn_p): Consider sub-64-bit vector moves scalar.\n\t* config/aarch64/iterators.md (VDUP): New iterator.\n\t(elem_bits): Define attribute for sub-64-bit vector modes.\n\t(Vetype): Likewise.\n\t(VEL): Likewise.\n\t(single_wx): Define attribute for sub-64-bit vector and scalar modes.\n\t(single_type): Likewise.\n\t(Vqduptype): New mode attribute.\n\t(Vdduptype): Likewise.\n\t(vstype): Define attribute for 64-bit vector and sub-128-bit scalar\n\tmodes.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/ldp_stp_16.c: Adjust testcase.\n\t* gcc.target/aarch64/sve/slp_1.c: Likewise.\n\t* gcc.target/aarch64/vec-init-18.c: Likewise.\n\t* gcc.target/aarch64/vec-init-23.c: New test.\n---\n gcc/config/aarch64/aarch64-simd.md | 48 +-\n gcc/config/aarch64/aarch64.cc | 46 +-\n gcc/config/aarch64/iterators.md | 62 ++-\n gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c | 5 +-\n gcc/testsuite/gcc.target/aarch64/sve/slp_1.c | 7 +-\n .../gcc.target/aarch64/vec-init-18.c | 7 +-\n .../gcc.target/aarch64/vec-init-23.c | 435 ++++++++++++++++++\n 7 files changed, 587 insertions(+), 23 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/vec-init-23.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 855b1ba353c..4bb26621efc 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -136,6 +136,28 @@\n }\n )\n \n+(define_insn \"*aarch64_simd_dup_subvector<VQ:mode><VDUP:mode>\"\n+ [(set (match_operand:VQ 0 \"register_operand\")\n+\t(vec_duplicate:VQ\n+\t (match_operand:VDUP 1 \"register_operand\")))]\n+ \"TARGET_SIMD\"\n+ {@ [ cons: =0 , 1 ; attrs: type ]\n+ [ w , w ; neon_dup<VQ:q> ] dup\\t%0.<VDUP:Vqduptype>, %1.<VDUP:vstype>[0]\n+ [ w , r ; neon_from_gp<VQ:q> ] dup\\t%0.<VDUP:Vqduptype>, %<VDUP:single_wx>1\n+ }\n+)\n+\n+(define_insn \"*aarch64_simd_dup_subvector<VD:mode><VDUP:mode>\"\n+ [(set (match_operand:VD 0 \"register_operand\")\n+\t(vec_duplicate:VD\n+\t (match_operand:VDUP 1 \"register_operand\")))]\n+ \"TARGET_SIMD\"\n+ {@ [ cons: =0 , 1 ; attrs: type ]\n+ [ w , w ; neon_dup<VD:q> ] dup\\t%0.<VDUP:Vdduptype>, %1.<VDUP:vstype>[0]\n+ [ w , r ; neon_from_gp<VD:q> ] dup\\t%0.<VDUP:Vdduptype>, %<VDUP:single_wx>1\n+ }\n+)\n+\n (define_insn \"@aarch64_dup_lane<mode>\"\n [(set (match_operand:VALL_F16 0 \"register_operand\" \"=w\")\n \t(vec_duplicate:VALL_F16\n@@ -1282,6 +1304,30 @@\n [(set_attr \"type\" \"neon_ins<q>, neon_from_gp<q>, neon_load1_one_lane<q>\")]\n )\n \n+(define_insn \"@aarch64_simd_vec_set<mode>\"\n+ [(set (match_operand:VSUB64 0 \"register_operand\" \"=r, w\")\n+\t(vec_merge:VSUB64\n+\t (vec_duplicate:VSUB64\n+\t\t(match_operand:<VEL> 1 \"aarch64_simd_nonimmediate_operand\" \"r, w\"))\n+\t (match_operand:VSUB64 3 \"register_operand\" \"0, 0\")\n+\t (match_operand:SI 2 \"immediate_operand\" \"i, i\")))]\n+ \"TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0\"\n+ {\n+ int elt = exact_log2 (INTVAL (operands[2]));\n+ switch (which_alternative)\n+ {\n+ case 0:\n+\toperands[2] = GEN_INT (elt * <elem_bits>);\n+\treturn \"bfi\\t%w0, %w1, %2, <elem_bits>\";\n+ case 1:\n+\treturn \"ins\\t%0.<Vetype>[%p2], %1.<Vetype>[0]\";\n+ default:\n+\tgcc_unreachable ();\n+ }\n+ }\n+ [(set_attr \"type\" \"bfm, neon_ins\")]\n+)\n+\n ;; Inserting from the zero register into a vector lane is treated as an\n ;; expensive GP->FP move on all CPUs. Avoid it when optimizing for speed.\n (define_insn \"aarch64_simd_vec_set_zero<mode>\"\n@@ -1711,7 +1757,7 @@\n )\n \n (define_expand \"vec_set<mode>\"\n- [(match_operand:VALL_F16 0 \"register_operand\")\n+ [(match_operand:VALL_F16_SUB64 0 \"register_operand\")\n (match_operand:<VEL> 1 \"aarch64_simd_nonimmediate_operand\")\n (match_operand:SI 2 \"immediate_operand\")]\n \"TARGET_SIMD\"\ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 257c193fa64..5b1afa50ff8 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -25446,7 +25446,9 @@ aarch64_choose_vector_init_constant (machine_mode mode, rtx vals)\n }\n \n rtx c = gen_rtx_CONST_VECTOR (mode, copy);\n- if (aarch64_simd_valid_mov_imm (c))\n+ if (aarch64_simd_valid_mov_imm (c)\n+ || (INTEGRAL_MODE_P (mode)\n+\t && aarch64_advsimd_partial_mode_p (mode)))\n return c;\n \n /* Try generating a stepped sequence. */\n@@ -25487,7 +25489,7 @@ aarch64_choose_vector_init_constant (machine_mode mode, rtx vals)\n The caller has already tried a divide-and-conquer approach, so do\n not consider that case here. */\n \n-void\n+static void\n aarch64_expand_vector_init_fallback (rtx target, rtx vals)\n {\n machine_mode mode = GET_MODE (target);\n@@ -25545,6 +25547,43 @@ aarch64_expand_vector_init_fallback (rtx target, rtx vals)\n return;\n }\n \n+ /* Check if the vector can be represented as a duplicate of a\n+ subvector starting at index 0. */\n+ if (pow2p_hwi (n_elts))\n+ {\n+\tbool halves_equal = true;\n+\tint n_seq = n_elts;\n+\twhile (n_seq > 2)\n+\t {\n+\t for (int i = 0; i < n_seq / 2; i++)\n+\t if (!rtx_equal_p (XVECEXP (vals, 0, i),\n+\t\t\t\tXVECEXP (vals, 0, i + n_seq / 2)))\n+\t\t{\n+\t\t halves_equal = false;\n+\t\t break;\n+\t\t}\n+\n+\t if (!halves_equal)\n+\t break;\n+\n+\t n_seq /= 2;\n+\t }\n+\n+\tif (n_seq != n_elts)\n+\t {\n+\t machine_mode subv_mode = mode_for_vector (inner_mode,\n+\t\t\t\t\t\t n_seq).require ();\n+\t rtx new_target = gen_reg_rtx (subv_mode);\n+\t rtvec new_vals = rtvec_alloc (n_seq);\n+\t for (int i = 0; i < n_seq; i++)\n+\t RTVEC_ELT (new_vals, i) = XVECEXP (vals, 0, i);\n+\t aarch64_expand_vector_init (new_target,\n+\t\t\t\t\tgen_rtx_PARALLEL (subv_mode, new_vals));\n+\t aarch64_emit_move (target, gen_vec_duplicate (mode, new_target));\n+\t return;\n+\t }\n+ }\n+\n enum insn_code icode = optab_handler (vec_set_optab, mode);\n gcc_assert (icode != CODE_FOR_nothing);\n \n@@ -25704,7 +25743,8 @@ scalar_move_insn_p (rtx set)\n rtx src = SET_SRC (set);\n rtx dest = SET_DEST (set);\n return (is_a<scalar_mode> (GET_MODE (dest))\n-\t && aarch64_mov_operand (src, GET_MODE (dest)));\n+\t && aarch64_mov_operand (src, GET_MODE (dest)))\n+\t || aarch64_advsimd_partial_mode_p (GET_MODE (dest));\n }\n \n /* Similar to seq_cost, but ignore cost for scalar moves. */\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex dfca3327f1f..1fc67d95bd4 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -139,6 +139,10 @@\n ;; VQMOV without 2-element modes.\n (define_mode_iterator VQMOV_NO2E [V16QI V8HI V4SI V8HF V8BF V4SF])\n \n+;; Modes that can be duplicated into a 64/128-bit register.\n+(define_mode_iterator VDUP [V8QI V4QI V2QI QI V4HI V2HI HI V2SI SI DI\n+\t\t\t V4BF V2BF BF V4HF V2HF HF V2SF SF DF])\n+\n ;; Double integer vector modes.\n (define_mode_iterator VD_I [V8QI V4HI V2SI DI])\n \n@@ -1488,7 +1492,9 @@\n \n ;; The number of bits in a vector element, or controlled by a predicate\n ;; element.\n-(define_mode_attr elem_bits [(VNx16BI \"8\") (VNx8BI \"16\")\n+(define_mode_attr elem_bits [(V2QI \"8\") (V4QI \"8\") (V2HF \"16\") (V2HI \"16\")\n+\t\t\t (V2BF \"16\")\n+\t\t\t (VNx16BI \"8\") (VNx8BI \"16\")\n \t\t\t (VNx4BI \"32\") (VNx2BI \"64\")\n \t\t\t (VNx16QI \"8\") (VNx32QI \"8\") (VNx64QI \"8\")\n \t\t\t (VNx8HI \"16\") (VNx16HI \"16\") (VNx32HI \"16\")\n@@ -1593,11 +1599,12 @@\n \n ;; Mode-to-individual element type mapping.\n (define_mode_attr Vetype [(V8QI \"b\") (V16QI \"b\")\n-\t\t\t (V4HI \"h\") (V8HI \"h\")\n+\t\t\t (V2QI \"b\") (V4QI \"b\")\n+\t\t\t (V4HI \"h\") (V8HI \"h\") (V2HI \"h\")\n \t\t\t (V2SI \"s\") (V4SI \"s\")\n \t\t\t (V2DI \"d\") (V1DI \"d\")\n-\t\t\t (V4HF \"h\") (V8HF \"h\")\n-\t\t\t (V2SF \"s\") (V4SF \"s\")\n+\t\t\t (V4HF \"h\") (V8HF \"h\") (V2HF \"h\")\n+\t\t\t (V2SF \"s\") (V4SF \"s\") (V2BF \"h\")\n \t\t\t (V2DF \"d\") (V1DF \"d\")\n \t\t\t (V2x8QI \"b\") (V2x4HI \"h\")\n \t\t\t (V2x2SI \"s\") (V2x1DI \"d\")\n@@ -1772,8 +1779,10 @@\n \t\t\t (V4x2DF \"v2df\") (V4x8BF \"v8bf\")])\n \n ;; Define element mode for each vector mode.\n-(define_mode_attr VEL [(V8QI \"QI\") (V16QI \"QI\")\n+(define_mode_attr VEL [(V8QI \"QI\") (V16QI \"QI\")\n+\t\t (V2QI \"QI\") (V4QI \"QI\")\n \t\t (V4HI \"HI\") (V8HI \"HI\")\n+\t\t (V2HI \"HI\") (V2HF \"HF\")\n \t\t (V2SI \"SI\") (V4SI \"SI\")\n \t\t (DI \"DI\") (V1DI \"DI\")\n \t\t (V2DI \"DI\")\n@@ -1784,6 +1793,7 @@\n \t\t (SI \"SI\") (HI \"HI\")\n \t\t (QI \"QI\")\n \t\t (V4BF \"BF\") (V8BF \"BF\")\n+\t\t (V2BF \"BF\")\n \t\t (V2x8QI \"QI\") (V2x4HI \"HI\")\n \t\t (V2x2SI \"SI\") (V2x1DI \"DI\")\n \t\t (V2x4HF \"HF\") (V2x2SF \"SF\")\n@@ -2037,6 +2047,26 @@\n (define_mode_attr V2ntype [(V8HI \"16b\") (V4SI \"8h\")\n \t\t\t (V2DI \"4s\")])\n \n+;; Register suffix used when duplicating a value of a certain mode\n+;; into a full 128-bit AdvSIMD register.\n+(define_mode_attr Vqduptype [(QI \"16b\") (V2QI \"8h\") (V4QI \"4s\") (V8QI \"2d\")\n+\t\t\t (HI \"8h\") (V2HI \"4s\") (V4HI \"2d\")\n+\t\t\t (HF \"8h\") (V2HF \"4s\") (V4HF \"2d\")\n+\t\t\t (BF \"8h\") (V2BF \"4s\") (V4BF \"2d\")\n+\t\t\t (SI \"4s\") (V2SI \"2d\")\n+\t\t\t (SF \"4s\") (V2SF \"2d\")\n+\t\t\t (DI \"2d\") (DF \"2d\")])\n+\n+;; Register suffix used when duplicating a value of a certain mode\n+;; into a partial 64-bit AdvSIMD register.\n+(define_mode_attr Vdduptype [(QI \"8b\") (V2QI \"4h\") (V4QI \"2s\") (V8QI \"\")\n+\t\t\t (HI \"4h\") (V2HI \"2s\") (V4HI \"\")\n+\t\t\t (HF \"4h\") (V2HF \"2s\") (V4HF \"\")\n+\t\t\t (BF \"4h\") (V2BF \"2s\") (V4BF \"\")\n+\t\t\t (SI \"2s\") (V2SI \"\")\n+\t\t\t (SF \"2s\") (V2SF \"\")\n+\t\t\t (DI \"\") (DF \"\")])\n+\n ;; The result of FCVTN on two vectors of the given mode. The result has\n ;; twice as many QI elements as the input.\n (define_mode_attr VPACKB [(V4HF \"V8QI\") (V8HF \"V16QI\") (V4SF \"V8QI\")])\n@@ -2161,8 +2191,13 @@\n ;; Whether a mode fits in W or X registers (i.e. \"w\" for 32-bit modes\n ;; and \"x\" for 64-bit modes).\n (define_mode_attr single_wx [(SI \"w\") (SF \"w\")\n+\t\t\t (V2QI \"w\") (V4QI \"w\")\n \t\t\t (V8QI \"x\") (V4HI \"x\")\n \t\t\t (V4HF \"x\") (V4BF \"x\")\n+\t\t\t (V2HI \"w\") (V2HF \"w\")\n+\t\t\t (HF \"w\") (QI \"w\")\n+\t\t\t (V2BF \"w\") (BF \"w\")\n+\t\t\t (HI \"w\")\n \t\t\t (V2SI \"x\") (V2SF \"x\")\n \t\t\t (DI \"x\") (DF \"x\")])\n \n@@ -2172,7 +2207,12 @@\n \t\t\t (V8QI \"d\") (V4HI \"d\")\n \t\t\t (V4HF \"d\") (V4BF \"d\")\n \t\t\t (V2SI \"d\") (V2SF \"d\")\n-\t\t\t (DI \"d\") (DF \"d\")])\n+\t\t\t (DI \"d\") (DF \"d\")\n+\t\t\t (QI \"b\") (BF \"h\")\n+\t\t\t (V2HF \"s\") (HI \"h\")\n+\t\t\t (V4QI \"s\") (V2QI \"h\")\n+\t\t\t (V2HI \"s\") (V2BF \"s\")\n+\t\t\t (HF \"h\")])\n \n ;; Whether a double-width mode fits in D or Q registers (i.e. \"d\" for\n ;; 32-bit modes and \"q\" for 64-bit modes).\n@@ -2182,9 +2222,13 @@\n \t\t\t (V2SI \"q\") (V2SF \"q\")\n \t\t\t (DI \"q\") (DF \"q\")])\n \n-;; Scalar size of a sub-64-bit vector mode.\n-(define_mode_attr vstype [(V4QI \"s\") (V2QI \"h\")\n-\t\t\t (V2HI \"s\") (V2BF \"s\") (V2HF \"s\")])\n+;; Scalar size of a sub-128-bit vector or scalar mode.\n+(define_mode_attr vstype [(V8QI \"d\") (V4QI \"s\") (V2QI \"h\") (QI \"b\")\n+\t\t\t (V4HI \"d\") (V2HI \"s\") (HI \"h\")\n+\t\t\t (V2SI \"d\") (SI \"s\") (DI \"d\")\n+\t\t\t (V4BF \"d\") (V2BF \"s\") (BF \"h\")\n+\t\t\t (V4HF \"d\") (V2HF \"s\") (HF \"h\")\n+\t\t\t (V2SF \"d\") (SF \"s\") (DF \"d\")])\n \n ;; Define corresponding core/FP element mode for each vector mode.\n (define_mode_attr vw [(V8QI \"w\") (V16QI \"w\")\ndiff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c\nindex 95835aa2eb4..a6b4d50f34f 100644\n--- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c\n+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c\n@@ -96,9 +96,8 @@ CONS2_FN (4, float);\n \n /*\n ** cons2_8_float:\n-**\tdup\tv[0-9]+\\.2s, v[0-9]+\\.s\\[0\\]\n-**\tdup\tv[0-9]+\\.2s, v[0-9]+\\.s\\[0\\]\n-**\tzip1\tv([0-9]+)\\.4s, v[0-9]+\\.4s, v[0-9]+\\.4s\n+**\tuzp1\tv1\\.2s, v0\\.2s, v1\\.2s\n+**\tdup\tv([0-9]+)\\.2d, v1\\.d\\[0\\]\n **\tstp\tq\\1, q\\1, \\[x0\\]\n **\tstp\tq\\1, q\\1, \\[x0, #?32\\]\n **\tret\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\nindex 98e8ac3c785..2bb2c04fa20 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\n@@ -30,14 +30,13 @@ vec_slp_##TYPE (TYPE *restrict a, TYPE b, TYPE c, int n)\t\\\n TEST_ALL (VEC_PERM)\n \n /* We should use one DUP for each of the 8-, 16- and 32-bit types,\n- (for now, insert both elements with umov + ins for _Float16). We should use two\n+ (for now, insert both elements with ins for _Float16). We should use two\n DUPs for each of the three 64-bit types. */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.h, [hw]} 2 } } */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.s, [sw]} 3 } } */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.d, [dx]} 9 } } */\n-/* { dg-final { scan-assembler-times {\\tumov\\tw[0-9]+, v[0-9]+\\.h} 2 } } */\n-/* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[0\\], w[0-9]+} 1 } } */\n-/* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[1\\], w[0-9]+} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[0\\], v[0-9]+\\.h\\[0\\]} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[1\\], v[0-9]+\\.h\\[0\\]} 1 } } */\n /* { dg-final { scan-assembler-times {\\tzip1\\tz[0-9]+\\.d, z[0-9]+\\.d, z[0-9]+\\.d\\n} 3 } } */\n /* { dg-final { scan-assembler-not {\\tzip2\\t} } } */\n \ndiff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-18.c b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c\nindex ecb59fe510b..feeb181a0b5 100644\n--- a/gcc/testsuite/gcc.target/aarch64/vec-init-18.c\n+++ b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c\n@@ -15,6 +15,7 @@ int16x8_t foo2(int16_t x)\n return v;\n }\n \n-/* { dg-final { scan-assembler-times {\\tdup\\tv[0-9]+\\.4h, w[0-9]+} 3 } } */\n-/* { dg-final { scan-assembler {\\tmovi\\tv[0-9]+\\.4h, 0x1} } } */\n-/* { dg-final { scan-assembler-times {\\tzip1\\tv[0-9]+\\.8h, v[0-9]+\\.8h, v[0-9]+\\.8h} 2 } } */\n+/* { dg-final { scan-assembler-times {\\tdup\\tv[0-9]+\\.4s, w[0-9]+} 2 } } */\n+/* { dg-final { scan-assembler-times {\\tmov\\tw[0-9]+, 65537} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tbfi\\tw[0-9]+, w[0-9]+, 0, 16} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tbfi\\tw[0-9]+, w[0-9]+, 16, 16} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-23.c b/gcc/testsuite/gcc.target/aarch64/vec-init-23.c\nnew file mode 100644\nindex 00000000000..595470b29fb\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/vec-init-23.c\n@@ -0,0 +1,435 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8.2-a+fp16\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" } } */\n+\n+#include <arm_neon.h>\n+\n+/* Check vector initialization with a repeating sequence of elements. */\n+\n+#ifndef TESTCASE\n+#define TESTCASE(TYPE, ETYPE, T, SZ, NUM, MULT, ...)\\\n+ TYPE##SZ##MULT##_t test_##TYPE##SZ##_##NUM (ETYPE x0, ETYPE x1, ETYPE x2, ETYPE x3,\\\n+\t\t\t\t\t ETYPE x4, ETYPE x5, ETYPE x6, ETYPE x7)\\\n+ {\\\n+ return (TYPE##SZ##MULT##_t) {__VA_ARGS__};\\\n+ }\n+#endif\n+\n+#define TEST_8(TYPE, ETYPE, T)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 1, x16, x0, x0, x0, x0, x0, x0, x0, x0,\\\n+\t\t\t x0, x0, x0, x0, x0, x0, x0, x0)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 2, x16, x0, x1, x0, x1, x0, x1, x0, x1,\\\n+\t\t\t x0, x1, x0, x1, x0, x1, x0, x1)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 3, x16, x0, x1, x2, x3, x0, x1, x2, x3,\\\n+\t\t\t x0, x1, x2, x3, x0, x1, x2, x3)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 4, x16, x0, x1, x2, x3, x4, x5, x6, x7,\\\n+\t\t\t x0, x1, x2, x3, x4, x5, x6, x7)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 5, x16, x0, 0, x0, 0, x0, 0, x0, 0,\\\n+\t\t\t x0, 0, x0, 0, x0, 0, x0, 0)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 6, x16, 0, x0, 0, x0, 0, x0, 0, x0,\\\n+\t\t\t 0, x0, 0, x0, 0, x0, 0, x0)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 7, x16, x0, x1, 0, 1, x0, x1, 0, 1,\\\n+\t\t\t x0, x1, 0, 1, x0, x1, 0, 1)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 8, x16, 0, 1, x0, x1, 0, 1, x0, x1,\\\n+\t\t\t 0, 1, x0, x1, 0, 1, x0, x1)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 9, x16, x0, 0, x1, 1, x0, 0, x1, 1,\\\n+\t\t\t x0, 0, x1, 1, x0, 0, x1, 1)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 10, x16, x0, 0, x1, 1, x2, 2, x3, 3,\\\n+\t\t\t x0, 0, x1, 1, x2, 2, x3, 3)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 11, x16, 0, x0, 1, x1, 2, x2, 3, x3,\\\n+\t\t\t 0, x0, 1, x1, 2, x2, 3, x3)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 12, x16, x0, x1, 0, 1, x2, x3, 2, 3,\\\n+\t\t\t x0, x1, 0, 1, x2, x3, 2, 3)\\\n+ TESTCASE (TYPE, ETYPE, T, 8, 13, x16, 0, 1, x0, x1, 2, 3, x2, x3,\\\n+\t\t\t 0, 1, x0, x1, 2, 3, x2, x3)\n+\n+#define TEST_16(TYPE, ETYPE, T)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 1, x8, x0, x0, x0, x0, x0, x0, x0, x0)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 2, x8, x0, x1, x0, x1, x0, x1, x0, x1)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 3, x8, x0, x1, x2, x3, x0, x1, x2, x3)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 4, x8, x0, 0, x0, 0, x0, 0, x0, 0)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 5, x8, 0, x0, 0, x0, 0, x0, 0, x0)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 6, x8, x0, x1, 0, 1, x0, x1, 0, 1)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 7, x8, 0, 1, x0, x1, 0, 1, x0, x1)\\\n+ TESTCASE (TYPE, ETYPE, T, 16, 8, x8, 0, x0, 1, x1, 0, x0, 1, x1)\\\n+\n+#define TEST_32(TYPE, ETYPE, T)\\\n+ TESTCASE (TYPE, ETYPE, T, 32, 1, x4, x0, x0, x0, x0)\\\n+ TESTCASE (TYPE, ETYPE, T, 32, 2, x4, x0, x1, x0, x1)\\\n+ TESTCASE (TYPE, ETYPE, T, 32, 3, x4, x0, 0, x0, 0)\\\n+ TESTCASE (TYPE, ETYPE, T, 32, 4, x4, 0, x0, 0, x0)\n+\n+#define TEST_64(TYPE, ETYPE, T)\\\n+ TESTCASE (TYPE, ETYPE, T, 64, 1, x2, x0, x0)\n+\n+TEST_8(int, int8_t, s)\n+\n+TEST_16(float, float, f)\n+TEST_16(int, int16_t, s)\n+\n+TEST_32(float, float, f)\n+TEST_32(int, int32_t, s)\n+\n+TEST_64(float, double, f)\n+TEST_64(int, int64_t, s)\n+\n+/*\n+** test_int8_1:\n+**\tdup\tv0\\.16b, w0\n+**\tret\n+*/\n+\t\n+/*\n+** test_int8_2:\n+**\tbfi\tw0, w1, 8, 8\n+**\tdup\tv0\\.8h, w0\n+**\tret\n+*/\n+\n+/*\n+** test_int8_3:\n+**\tbfi\tw0, w1, 8, 8\n+**\tbfi\tw0, w2, 16, 8\n+**\tbfi\tw0, w3, 24, 8\n+**\tdup\tv0\\.4s, w0\n+**\tret\n+*/\n+\n+/*\n+** test_int8_4:\n+**\tbfi\tw0, w2, 8, 8\n+**\tbfi\tw1, w3, 8, 8\n+**\tbfi\tw0, w4, 16, 8\n+**\tbfi\tw1, w5, 16, 8\n+**\tbfi\tw0, w6, 24, 8\n+**\tbfi\tw1, w7, 24, 8\n+**\tdup\tv31\\.2s, w0\n+**\tdup\tv0\\.2s, w1\n+**\tzip1\tv0\\.16b, v31\\.16b, v0\\.16b\n+**\tret\n+*/\n+\n+/*\n+** test_int8_5:\n+**\tmov\tw1, 0\n+**\tbfi\tw1, w0, 0, 8\n+**\tdup\tv0\\.8h, w1\n+**\tret\n+*/\n+\n+/*\n+** test_int8_6:\n+**\tmov\tw1, 0\n+**\tbfi\tw1, w0, 8, 8\n+**\tdup\tv0\\.8h, w1\n+**\tret\n+*/\n+\n+/*\n+** test_int8_7:\n+**\tmov\tw2, 16777472\n+**\tbfi\tw2, w0, 0, 8\n+**\tbfi\tw2, w1, 8, 8\n+**\tdup\tv0\\.4s, w2\n+**\tret\n+*/\n+\n+/*\n+** test_int8_8:\n+**\tmov\tw2, 16777472\n+**\tbfi\tw2, w0, 16, 8\n+**\tbfi\tw2, w1, 24, 8\n+**\tdup\tv0\\.4s, w2\n+**\tret\n+*/\n+\n+/*\n+** test_int8_9:\n+**\tmov\tw2, 16842752\n+**\tbfi\tw2, w0, 0, 8\n+**\tbfi\tw2, w1, 16, 8\n+**\tdup\tv0\\.4s, w2\n+**\tret\n+*/\n+\n+/*\n+** test_int8_10:\n+**\tbfi\tw0, w1, 8, 8\n+**\tbfi\tw0, w2, 16, 8\n+**\tbfi\tw0, w3, 24, 8\n+**\tdup\tv31\\.2s, w0\n+**\tadrp\tx0, .LANCHOR[0-9]+\n+**\tldr\td0, \\[x0, #:lo12:.LANCHOR[0-9]+\\]\n+**\tzip1\tv0\\.16b, v31\\.16b, v0\\.16b\n+**\tret\n+*/\n+\n+/*\n+** test_int8_11:\n+**\tbfi\tw0, w1, 8, 8\n+**\tadrp\tx4, .LANCHOR[0-9]+\n+**\tbfi\tw0, w2, 16, 8\n+**\tldr\td0, \\[x4, #:lo12:\\.LANCHOR[0-9]+\\]\n+**\tbfi\tw0, w3, 24, 8\n+**\tdup\tv31\\.2s, w0\n+**\tzip1\tv0\\.16b, v0\\.16b, v31\\.16b\n+**\tret\n+*/\n+\n+/*\n+** test_int8_12:\n+**\tmov\tw4, 33685504\n+**\tbfi\tw4, w0, 0, 8\n+**\tmov\tw0, 257\n+**\tmovk\tw0, 0x303, lsl 16\n+**\tbfi\tw0, w1, 0, 8\n+**\tbfi\tw4, w2, 16, 8\n+**\tbfi\tw0, w3, 16, 8\n+**\tdup\tv31\\.2s, w4\n+**\tdup\tv0\\.2s, w0\n+**\tzip1\tv0\\.16b, v31\\.16b, v0\\.16b\n+**\tret\n+*/\n+\n+/*\n+** test_int8_13:\n+**\tmov\tw4, 33685504\n+**\tbfi\tw4, w0, 8, 8\n+**\tmov\tw0, 257\n+**\tmovk\tw0, 0x303, lsl 16\n+**\tbfi\tw0, w1, 8, 8\n+**\tbfi\tw4, w2, 24, 8\n+**\tbfi\tw0, w3, 24, 8\n+**\tdup\tv31\\.2s, w4\n+**\tdup\tv0\\.2s, w0\n+**\tzip1\tv0\\.16b, v31\\.16b, v0\\.16b\n+**\tret\n+*/\n+\n+/*\n+** test_float16_1:\n+**\tfcvt\th0, s0\n+**\tdup\tv0\\.8h, v0\\.h\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_float16_2:\n+**\tfcvt\th1, s1\n+**\tfcvt\th0, s0\n+**\tins\tv0\\.h\\[1\\], v1\\.h\\[0\\]\n+**\tdup\tv0\\.4s, v0\\.s\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_float16_3:\n+**\tuzp1\tv2\\.2s, v0\\.2s, v2\\.2s\n+**\tuzp1\tv3\\.2s, v1\\.2s, v3\\.2s\n+**\tzip1\tv3\\.4s, v2\\.4s, v3\\.4s\n+**\tfcvtn\tv0\\.4h, v3\\.4s\n+**\tuzp1\tv0\\.2d, v0\\.2d, v0\\.2d\n+**\tret\n+*/\n+\n+/*\n+** test_float16_4:\n+**\tfcvt\th0, s0\n+**\tmovi\tv31\\.2d, #0\n+**\tins\tv31\\.h\\[0\\], v0\\.h\\[0\\]\n+**\tdup\tv0\\.4s, v31\\.s\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_float16_5:\n+**\tfcvt\th0, s0\n+**\tmovi\tv31\\.2d, #0\n+**\tins\tv31\\.h\\[1\\], v0\\.h\\[0\\]\n+**\tdup\tv0\\.4s, v31\\.s\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_float16_6:\n+**\tfcvt\th1, s1\n+**\tfcvt\th0, s0\n+**\tmovi\tv31\\.2d, #0\n+**\tmov\tw0, 1006648320\n+**\tumov\tw1, v1\\.h\\[0\\]\n+**\tins\tv31\\.h\\[0\\], v0\\.h\\[0\\]\n+**\tbfi\tw0, w1, 0, 16\n+**\tdup\tv31\\.2s, v31\\.s\\[0\\]\n+**\tdup\tv0\\.2s, w0\n+**\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n+**\tret\n+*/\n+\n+/*\n+** test_float16_7:\n+**\tfcvt\th1, s1\n+**\tfcvt\th0, s0\n+**\tmovi\tv31\\.2d, #0\n+**\tmov\tw0, 1006648320\n+**\tumov\tw1, v1\\.h\\[0\\]\n+**\tins\tv31\\.h\\[1\\], v0\\.h\\[0\\]\n+**\tbfi\tw0, w1, 16, 16\n+**\tdup\tv31\\.2s, v31\\.s\\[0\\]\n+**\tdup\tv0\\.2s, w0\n+**\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n+**\tret\n+*/\n+\n+/*\n+** test_float16_8:\n+**\tfcvt\th1, s1\n+**\tfcvt\th0, s0\n+**\tmovi\tv31\\.2s, 0x3c, lsl 24\n+**\tins\tv0\\.h\\[1\\], v1\\.h\\[0\\]\n+**\tdup\tv0\\.2s, v0\\.s\\[0\\]\n+**\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n+**\tret\n+*/\n+\n+/*\n+** test_int16_1:\n+**\tdup\tv0\\.8h, w0\n+**\tret\n+*/\n+\n+/*\n+** test_int16_2:\n+**\tbfi\tw0, w1, 16, 16\n+**\tdup\tv0\\.4s, w0\n+**\tret\n+*/\n+\n+/*\n+** test_int16_3:\n+**\tbfi\tw0, w2, 16, 16\n+**\tbfi\tw1, w3, 16, 16\n+**\tdup\tv31\\.2s, w0\n+**\tdup\tv0\\.2s, w1\n+**\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n+**\tret\n+*/\n+\n+/*\n+** test_int16_4:\n+**\tmov\tw1, 0\n+**\tbfi\tw1, w0, 0, 16\n+**\tdup\tv0\\.4s, w1\n+**\tret\n+*/\n+\n+/*\n+** test_int16_5:\n+**\tmov\tw1, 0\n+**\tbfi\tw1, w0, 16, 16\n+**\tdup\tv0\\.4s, w1\n+**\tret\n+*/\n+\n+/*\n+** test_int16_6:\n+**\tmov\tw2, 0\n+**\tbfi\tw2, w0, 0, 16\n+**\tmov\tw0, 65537\n+**\tbfi\tw0, w1, 0, 16\n+**\tdup\tv31\\.2s, w2\n+**\tdup\tv0\\.2s, w0\n+**\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n+**\tret\n+*/\n+\n+/*\n+** test_int16_7:\n+**\tmov\tw2, 0\n+**\tbfi\tw2, w0, 16, 16\n+**\tmov\tw0, 65537\n+**\tbfi\tw0, w1, 16, 16\n+**\tdup\tv31\\.2s, w2\n+**\tdup\tv0\\.2s, w0\n+**\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n+**\tret\n+*/\n+\n+/*\n+** test_int16_8:\n+**\tbfi\tw0, w1, 16, 16\n+**\tmovi\tv0\\.2s, 0x1, lsl 16\n+**\tdup\tv31\\.2s, w0\n+**\tzip1\tv0\\.8h, v0\\.8h, v31\\.8h\n+**\tret\n+*/\n+\n+/*\n+** test_float32_1:\n+**\tdup\tv0\\.4s, v0\\.s\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_float32_2:\n+**\tuzp1\tv0\\.2s, v0\\.2s, v1\\.2s\n+**\tdup\tv0\\.2d, v0\\.d\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_float32_3:\n+**\tmovi\tv31\\.2s, 0\n+**\tdup\tv0\\.2s, v0\\.s\\[0\\]\n+**\tzip1\tv0\\.4s, v0\\.4s, v31\\.4s\n+**\tret\n+*/\n+\n+/*\n+** test_float32_4:\n+**\tmovi\tv31\\.2s, 0\n+**\tdup\tv0\\.2s, v0\\.s\\[0\\]\n+**\tzip1\tv0\\.4s, v31\\.4s, v0\\.4s\n+**\tret\n+*/\n+\n+/*\n+** test_int32_1:\n+**\tdup\tv0\\.4s, w0\n+**\tret\n+*/\n+\n+/*\n+** test_int32_2:\n+**\tfmov\ts0, w0\n+**\tins\tv0\\.s\\[1\\], w1\n+**\tdup\tv0\\.2d, v0\\.d\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_int32_3:\n+**\tdup\tv31\\.2s, w0\n+**\tmovi\tv0\\.2s, 0\n+**\tzip1\tv0\\.4s, v31\\.4s, v0\\.4s\n+**\tret\n+*/\n+\n+/*\n+** test_int32_4:\n+**\tdup\tv31\\.2s, w0\n+**\tmovi\tv0\\.2s, 0\n+**\tzip1\tv0\\.4s, v0\\.4s, v31\\.4s\n+**\tret\n+*/\n+\n+/*\n+** test_float64_1:\n+**\tdup\tv0\\.2d, v0\\.d\\[0\\]\n+**\tret\n+*/\n+\n+/*\n+** test_int64_1:\n+**\tdup\tv0\\.2d, x0\t\n+**\tret\n+*/\n", "prefixes": [ "2/4" ] }