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GET /api/patches/2228663/?format=api
{ "id": 2228663, "url": "http://patchwork.ozlabs.org/api/patches/2228663/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260427080642.371531-2-artemiy.volkov@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260427080642.371531-2-artemiy.volkov@arm.com>", "list_archive_url": null, "date": "2026-04-27T08:06:08", "name": "[1/4] aarch64: introduce partial AdvSIMD vector modes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "72ff394ae461dcafef55dc3fc8ad89aa521781c0", "submitter": { "id": 91911, "url": "http://patchwork.ozlabs.org/api/people/91911/?format=api", "name": "Artemiy Volkov", "email": "artemiy.volkov@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260427080642.371531-2-artemiy.volkov@arm.com/mbox/", "series": [ { "id": 501601, "url": "http://patchwork.ozlabs.org/api/series/501601/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501601", "date": "2026-04-27T08:06:07", "name": "aarch64: vector initialization improvements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501601/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228663/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=gPF71k11;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=gPF71k11;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Artemiy Volkov <artemiy.volkov@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<tamar.christina@arm.com>, <wilco.dijkstra@arm.com>,\n <andrew.pinski@oss.qualcomm.com>, <richard.earnshaw@arm.com>,\n <ktkachov@nvidia.com>, <alice.carlotti@arm.com>, <alex.coplan@arm.com>,\n Artemiy Volkov <artemiy.volkov@arm.com>", "Subject": "[PATCH 1/4] aarch64: introduce partial AdvSIMD vector modes", "Date": "Mon, 27 Apr 2026 08:06:08 +0000", "Message-ID": "<20260427080642.371531-2-artemiy.volkov@arm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427080642.371531-1-artemiy.volkov@arm.com>", "References": "<20260427080642.371531-1-artemiy.volkov@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n AM2PEPF0001C710:EE_|GV1PR08MB10533:EE_|AMS0EPF000001B5:EE_|PA4PR08MB6159:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6b5bc62f-206f-4ed6-2118-08dea4341daf", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|376014|36860700016|1800799024|82310400026|13003099007|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info-Original": "\n W/x0VIgDQOKvPhsY7NzEvuMFTMTZ+3uuJEgYXtEgmXJpxegDlEsX++PB0jIjstCWAj84sTSY+Cv2B/eqy/kCEFKaqwUEKEio3LWAGhldDqCauHItABeto13CkGOzg7x3dcr+IOUP2PZF/6Xz+C0OYGJJxem5jrp0p7dMiHCJMKJ7djflsAOUop+3Ynx445u/nR7a55KIn2Y9fJK7yOUKxh/7vROAP44C331Y05x/bVea5HHjl18bjPQ/Vp6MWaGeyQI3hc98wasPM5qLMC3482ZmHpfo/M+ABiz5jDtfBS8fBAP9IzGfH8rw048U074VM9FIT1m3eg0LTaZkMtIqXB5K0nfd3pFsZ1vzyGq/fZHEhKP9ixfqvd5/Lcx99fVuWPq9LG42aPNQ5EtOTHmNjjKtUco+jlK6D2TFBtm+s8NsH4KiGFgXaoPU7oPU//Szk/TSmFdUcgxGXdSdgX8Y4gTY4xNww8P2jGOJABlI+l+xspYgUft2Rqwtqx+34JR9F41RKT4mweA1q/tWq+NJKYvm6PyatNSaIjkj+1NPNgmP72AK07eXlrTbk1PT3gwTXN0JP46bseOHSlhe5m+/+N2FsiCg2klFy6xRa7Bw0Q5Q3KIA7vWHLCwXe0LDxJaVMsPL++xRue+KImyIZKGlLea3PEIwS79z0eGFy4X9SzjYdbpD6wkx0umuY71r8xgPk3cbeagDNHqpWZp1gqLzPU6fV/n9D7DwedCCCxzrqKo=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AMS0EPF000001B5.eurprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "In addition to V2HF that already exists, this patch adds 4 more partial\n(16- and 32-bit) AdvSIMD vector modes: V4QI, V2QI, V2HI, and V2BF. For\nnow, these are intended only for duplication into full-sized (32-, 64-,\nand 128-bit) registers. As a minimal closure required to bootstrap the\ncompiler, this also implements the \"mov\" expand and the \"aarch64_simd_mov\"\ninsn_and_split for the new modes (gathered under the VSUB64 iterator).\n\nThese modes are also added to aarch64_classify_vector_mode (), and are\nclassified as VEC_ADVSIMD | VEC_PARTIAL, a yet-untaken value that seems to\nfit the bill. This is then used in\naarch64_ira_change_pseudo_allocno_class () to instruct regalloc to prefer\nGENERAL_REGS to FP_REGS for the integer modes, i.e. V4QI, V2QI, and V2HI.\n\nSome existing testcases were adjusted where needed. (The _Float16\ntestcase in sve/slp_1.c temporarily expects GPRs to be used for V2HF,\nwhich is corrected to FPRs by the succeeding patch; and the half-float\ncomplex tests now recognize some of the patterns, but check that V2BF\nstill can't be used for vectorization.)\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-modes.def (VECTOR_MODE): Remove V2HF.\n\t(VECTOR_MODES): Define V2QI, V4QI, V2HI, V2HF, V2BF.\n\t* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): New\n\tdefine_insn_and_split pattern.\n\t(mov<mode>): Add sub-64-bit vector modes to the VALL_F16 expander.\n\tForego const vector expansion for those modes.\n\t* config/aarch64/aarch64.cc (aarch64_ira_change_pseudo_allocno_class):\n\tPrefer GPRs for 16- and 32-bit integral vector modes.\n\t(aarch64_classify_vector_mode): Handle 16- and 32-bit vector modes.\n\t(aarch64_advsimd_partial_mode_p): New predicate.\n\t(aarch64_vectorize_vec_perm_const): Refuse for partial vector modes.\n\t* config/aarch64/constraints.md (Da): New constraint.\n\t* config/aarch64/iterators.md (VSUB64): New iterator.\n\t(VALL_F16_SUB64): Likewise.\n\t(size): Define attribute for sub-64-bit vector modes.\n\t(VSC): New mode attribute.\n\t(vstype): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/vect/complex/bb-slp-complex-add-half-float.c: Adjust testcase.\n\t* gcc.dg/vect/complex/bb-slp-complex-mla-half-float.c: Likewise.\n\t* gcc.dg/vect/complex/bb-slp-complex-mul-half-float.c: Likewise.\n\t* gcc.target/aarch64/sve/slp_1.c: Likewise.\n---\n gcc/config/aarch64/aarch64-modes.def | 4 +-\n gcc/config/aarch64/aarch64-simd.md | 64 ++++++++++++-\n gcc/config/aarch64/aarch64.cc | 89 ++++++++++++-------\n gcc/config/aarch64/constraints.md | 5 ++\n gcc/config/aarch64/iterators.md | 19 +++-\n .../complex/bb-slp-complex-add-half-float.c | 2 +\n .../complex/bb-slp-complex-mla-half-float.c | 4 +-\n .../complex/bb-slp-complex-mul-half-float.c | 6 +-\n gcc/testsuite/gcc.target/aarch64/sve/slp_1.c | 11 +--\n 9 files changed, 157 insertions(+), 47 deletions(-)", "diff": "diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def\nindex d9bff61adec..d5a54689f7a 100644\n--- a/gcc/config/aarch64/aarch64-modes.def\n+++ b/gcc/config/aarch64/aarch64-modes.def\n@@ -79,8 +79,10 @@ VECTOR_MODES (FLOAT, 8); /* V2SF. */\n VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */\n VECTOR_MODE (INT, DI, 1); /* V1DI. */\n VECTOR_MODE (FLOAT, DF, 1); /* V1DF. */\n-VECTOR_MODE (FLOAT, HF, 2); /* V2HF. */\n \n+VECTOR_MODES (INT, 2); /* V2QI. */\n+VECTOR_MODES (INT, 4); /* V4QI V2HI. */\n+VECTOR_MODES (FLOAT, 4); /* V2BF V2HF. */\n \n /* Integer vector modes used to represent intermediate widened values in some\n instructions. Not intended to be moved to and from registers or memory. */\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex c314e85927d..855b1ba353c 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -49,8 +49,8 @@\n (define_subst_attr \"vczbe\" \"add_vec_concat_subst_be\" \"\" \"_vec_concatz_be\")\n \n (define_expand \"mov<mode>\"\n- [(set (match_operand:VALL_F16 0 \"nonimmediate_operand\")\n-\t(match_operand:VALL_F16 1 \"general_operand\"))]\n+ [(set (match_operand:VALL_F16_SUB64 0 \"nonimmediate_operand\")\n+\t(match_operand:VALL_F16_SUB64 1 \"general_operand\"))]\n \"TARGET_FLOAT\"\n \"\n /* Force the operand into a register if it is not an\n@@ -77,7 +77,8 @@\n \t aarch64_expand_vector_init (operands[0], operands[1]);\n \t DONE;\n \t}\n- else if (!aarch64_simd_imm_zero (operands[1], <MODE>mode)\n+ else if (known_ge (GET_MODE_SIZE (<MODE>mode), 8)\n+\t && !aarch64_simd_imm_zero (operands[1], <MODE>mode)\n \t && !aarch64_simd_special_constant_p (operands[1], <MODE>mode)\n \t && !aarch64_simd_valid_mov_imm (operands[1]))\n \t{\n@@ -241,6 +242,63 @@\n }\n )\n \n+(define_insn_and_split \"*aarch64_simd_mov<mode>\"\n+ [(set (match_operand:VSUB64 0 \"nonimmediate_operand\")\n+\t(match_operand:VSUB64 1 \"general_operand\"))]\n+ \"TARGET_FLOAT\n+ && (register_operand (operands[0], <MODE>mode)\n+ || aarch64_simd_reg_or_zero (operands[1], <MODE>mode)\n+ || CONST_VECTOR_P (operands[1]))\"\n+ {@ [cons: =0, 1; attrs: type, arch]\n+ [r , Dz ; mov_imm , * ] mov\\t%w0, 0\n+ [r , rZ ; mov_reg , * ] mov\\t%w0, %w1\n+ [r , Da ; mov_imm , * ] #\n+ [r , w ; mov_reg , simd ] #\n+ [r , m ; load_4 , * ] ldr<size>\\t%w0, %1\n+ [w , w ; neon_logic , simd ] mov\\t%0.8b, %1.8b\n+ [w , m ; neon_load1_1reg , simd ] ldr\\t%<vstype>0, %1\n+ [w , Dz ; f_mcr , * ] fmov\\t%<vstype>0, xzr\n+ [m , rZ ; store_4 , * ] str<size>\\t%w1, %0\n+ [m , w ; neon_store1_1reg , simd ] str\\t%<vstype>1, %0\n+ }\n+ \"&& reload_completed\n+ && REG_P (operands[0])\"\n+ [(const_int 0)]\n+ {\n+ if (CONST_VECTOR_P (operands[1]))\n+ {\n+ int elt_bitsize\n+\t = GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (operands[1])));\n+ int n_elts = CONST_VECTOR_NUNITS (operands[1]).to_constant ();\n+ int val = 0;\n+ bool int_vector_p = CONST_INT_P (CONST_VECTOR_ELT (operands[1], 0));\n+ unsigned HOST_WIDE_INT eltval;\n+ rtx elt;\n+ for (int i = 0; i < n_elts; i++)\n+\t {\n+\t elt = CONST_VECTOR_ELT (operands[1], BYTES_BIG_ENDIAN\n+\t\t\t\t\t\t ? i\n+\t\t\t\t\t\t : n_elts - 1 - i);\n+\t if (int_vector_p)\n+\t eltval = INTVAL (elt);\n+\t else\n+\t {\n+\t\tbool res = aarch64_reinterpret_float_as_int (elt, &eltval);\n+\t\tgcc_assert (res);\n+\t }\n+\n+\t val = (val << elt_bitsize) + (eltval & ((1 << elt_bitsize) - 1));\n+\t }\n+ emit_move_insn (gen_rtx_REG (SImode, REGNO (operands[0])),\n+\t\t GEN_INT (val));\n+ }\n+ else if (REG_P (operands[1]))\n+ aarch64_simd_emit_reg_reg_move (operands, <VSC>mode, 1);\n+ DONE;\n+ }\n+ [(set_attr \"type\" \"mov_reg\")]\n+)\n+\n ;; When storing lane zero we can use the normal STR and its more permissive\n ;; addressing modes.\n \ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 37c28c8f2f8..257c193fa64 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -1479,40 +1479,6 @@ pr_or_ffr_regnum_p (unsigned int regno)\n return PR_REGNUM_P (regno) || regno == FFR_REGNUM || regno == FFRT_REGNUM;\n }\n \n-/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.\n- The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and\n- GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much\n- higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS\n- and GENERAL_REGS is lower than the memory cost (in this case the best class\n- is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its\n- cost results in bad allocations with many redundant int<->FP moves which\n- are expensive on various cores.\n- To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but\n- force a decision between FP_REGS and GENERAL_REGS. We use the allocno class\n- if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't\n- POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.\n- The result of this is that it is no longer inefficient to have a higher\n- memory move cost than the register move cost.\n-*/\n-\n-static reg_class_t\n-aarch64_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,\n-\t\t\t\t\t reg_class_t best_class)\n-{\n- machine_mode mode;\n-\n- if (!reg_class_subset_p (GENERAL_REGS, allocno_class)\n- || !reg_class_subset_p (FP_REGS, allocno_class))\n- return allocno_class;\n-\n- if (!reg_class_subset_p (GENERAL_REGS, best_class)\n- || !reg_class_subset_p (FP_REGS, best_class))\n- return best_class;\n-\n- mode = PSEUDO_REGNO_MODE (regno);\n- return FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode) ? FP_REGS : GENERAL_REGS;\n-}\n-\n static unsigned int\n aarch64_min_divisions_for_recip_mul (machine_mode mode)\n {\n@@ -1777,6 +1743,14 @@ aarch64_classify_vector_mode (machine_mode mode, bool any_target_p = false)\n case E_V4x2DFmode:\n return (TARGET_FLOAT || any_target_p) ? VEC_ADVSIMD | VEC_STRUCT : 0;\n \n+ /* 16-bit Advanced SIMD vectors. */\n+ case E_V2QImode:\n+ /* 32-bit Advanced SIMD vectors. */\n+ case E_V2HFmode:\n+ case E_V2BFmode:\n+ case E_V2HImode:\n+ case E_V4QImode:\n+ return (TARGET_FLOAT || any_target_p) ? VEC_ADVSIMD | VEC_PARTIAL : 0;\n /* 64-bit Advanced SIMD vectors. */\n case E_V8QImode:\n case E_V4HImode:\n@@ -1855,6 +1829,13 @@ aarch64_advsimd_full_struct_mode_p (machine_mode mode)\n return (aarch64_classify_vector_mode (mode) == (VEC_ADVSIMD | VEC_STRUCT));\n }\n \n+/* Return true if MODE is a partial (sub-64-bit) Advanced SIMD mode. */\n+static bool\n+aarch64_advsimd_partial_mode_p (machine_mode mode)\n+{\n+ return (aarch64_classify_vector_mode (mode) == (VEC_ADVSIMD | VEC_PARTIAL));\n+}\n+\n /* Return true if MODE is any of the data vector modes, including\n structure modes. */\n static bool\n@@ -2126,6 +2107,43 @@ aarch64_coalesce_units (machine_mode vec_mode, unsigned int factor)\n return {};\n }\n \n+/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.\n+ The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and\n+ GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much\n+ higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS\n+ and GENERAL_REGS is lower than the memory cost (in this case the best class\n+ is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its\n+ cost results in bad allocations with many redundant int<->FP moves which\n+ are expensive on various cores.\n+ To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but\n+ force a decision between FP_REGS and GENERAL_REGS. We use the allocno class\n+ if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't\n+ POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.\n+ The result of this is that it is no longer inefficient to have a higher\n+ memory move cost than the register move cost.\n+*/\n+\n+static reg_class_t\n+aarch64_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,\n+\t\t\t\t\t reg_class_t best_class)\n+{\n+ machine_mode mode;\n+\n+ if (!reg_class_subset_p (GENERAL_REGS, allocno_class)\n+ || !reg_class_subset_p (FP_REGS, allocno_class))\n+ return allocno_class;\n+\n+ if (!reg_class_subset_p (GENERAL_REGS, best_class)\n+ || !reg_class_subset_p (FP_REGS, best_class))\n+ return best_class;\n+\n+ mode = PSEUDO_REGNO_MODE (regno);\n+ return FLOAT_MODE_P (mode) || (VECTOR_MODE_P (mode)\n+\t\t\t\t && (!INTEGRAL_MODE_P (mode)\n+\t\t\t\t || !aarch64_advsimd_partial_mode_p (mode)))\n+\t\t\t\t? FP_REGS : GENERAL_REGS;\n+}\n+\n /* Implement TARGET_VECTORIZE_RELATED_MODE. */\n \n static opt_machine_mode\n@@ -28202,6 +28220,9 @@ aarch64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode,\n {\n struct expand_vec_perm_d d;\n \n+ if (aarch64_advsimd_partial_mode_p (op_mode))\n+ return false;\n+\n /* Check whether the mask can be applied to a single vector. */\n if (sel.ninputs () == 1\n || (op0 && rtx_equal_p (op0, op1)))\ndiff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md\nindex 3d166fe3a17..77eadc89819 100644\n--- a/gcc/config/aarch64/constraints.md\n+++ b/gcc/config/aarch64/constraints.md\n@@ -524,6 +524,11 @@\n (and (match_code \"const_int\")\n (match_test \"aarch64_simd_scalar_immediate_valid_for_move (op,\n \t\t\t\t\t\t QImode)\")))\n+(define_constraint \"Da\"\n+ \"@internal\n+ A constraint that matches all sub-64-bit vectors.\"\n+ (and (match_code \"const_vector\")\n+ (match_test \"known_lt (GET_MODE_BITSIZE (mode), 64)\")))\n \n (define_constraint \"Dt\"\n \"@internal\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 39b1e84edcc..dfca3327f1f 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -227,10 +227,17 @@\n ;; All Advanced SIMD integer modes\n (define_mode_iterator VALLI [VDQ_BHSI V2DI])\n \n+;; All sub-64-bit vector modes.\n+(define_mode_iterator VSUB64 [V2QI V4QI V2HI V2HF V2BF])\n+\n ;; All Advanced SIMD modes suitable for moving, loading, and storing.\n (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI\n \t\t\t\tV4HF V8HF V4BF V8BF V2SF V4SF V2DF])\n \n+;; All Advanced SIMD modes suitable for moving, loading, and storing,\n+;; plus all sub-64-bit vector modes.\n+(define_mode_iterator VALL_F16_SUB64 [VALL_F16 VSUB64])\n+\n ;; The VALL_F16 modes except the 128-bit 2-element ones.\n (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI\n \t\t\t\tV4HF V8HF V2SF V4SF])\n@@ -1466,7 +1473,9 @@\n (define_mode_attr s [(HF \"h\") (SF \"s\") (DF \"d\") (SI \"s\") (DI \"d\")])\n \n ;; Give the length suffix letter for a sign- or zero-extension.\n-(define_mode_attr size [(QI \"b\") (HI \"h\") (SI \"w\")])\n+(define_mode_attr size [(QI \"b\") (HI \"h\") (SI \"w\") (HF \"\") (BF \"\") (SF \"\")\n+\t\t\t(V2QI \"h\") (V4QI \"\") (V2HI \"\")\n+\t\t\t(V2HF \"\") (V2BF \"\")])\n \n ;; Give the number of bits in the mode\n (define_mode_attr sizen [(QI \"8\") (HI \"16\") (SI \"32\") (DI \"64\")])\n@@ -1883,6 +1892,10 @@\n \t\t\t(VNx4SI \"v2si\") (VNx4SF \"v2sf\")\n \t\t\t(VNx2DI \"di\") (VNx2DF \"df\")])\n \n+;; Sub-64-bit vector mode to equivalent scalar mode.\n+(define_mode_attr VSC [(V4QI \"SI\") (V2QI \"HI\")\n+\t\t (V2HI \"SI\") (V2HF \"SF\") (V2BF \"SF\")])\n+\n (define_mode_attr vnx [(V4SI \"vnx4si\") (V2DI \"vnx2di\")])\n \n ;; 64-bit container modes the inner or scalar source mode.\n@@ -2169,6 +2182,10 @@\n \t\t\t (V2SI \"q\") (V2SF \"q\")\n \t\t\t (DI \"q\") (DF \"q\")])\n \n+;; Scalar size of a sub-64-bit vector mode.\n+(define_mode_attr vstype [(V4QI \"s\") (V2QI \"h\")\n+\t\t\t (V2HI \"s\") (V2BF \"s\") (V2HF \"s\")])\n+\n ;; Define corresponding core/FP element mode for each vector mode.\n (define_mode_attr vw [(V8QI \"w\") (V16QI \"w\")\n \t\t (V4HI \"w\") (V8HI \"w\")\ndiff --git a/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-add-half-float.c b/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-add-half-float.c\nindex 3f1cce56955..6234f8646fe 100644\n--- a/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-add-half-float.c\n+++ b/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-add-half-float.c\n@@ -12,3 +12,5 @@\n \n /* { dg-final { scan-tree-dump \"add new stmt: \\[^\\n\\r]*COMPLEX_ADD_ROT270\" \"slp1\" { xfail *-*-* } } } */\n /* { dg-final { scan-tree-dump \"add new stmt: \\[^\\n\\r]*COMPLEX_ADD_ROT90\" \"slp1\" { xfail *-*-* } } } */\n+/* { dg-final { scan-tree-dump \"Found COMPLEX_ADD_ROT90\" \"slp1\" } } */\n+/* { dg-final { scan-tree-dump \"Found COMPLEX_ADD_ROT270\" \"slp1\" } } */\ndiff --git a/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mla-half-float.c b/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mla-half-float.c\nindex 33e500f3f4c..831f84bc1c8 100644\n--- a/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mla-half-float.c\n+++ b/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mla-half-float.c\n@@ -9,4 +9,6 @@\n #include \"complex-mla-template.c\"\n \n /* { dg-final { scan-tree-dump \"Found COMPLEX_FMA_CONJ\" \"slp1\" { xfail *-*-* } } } */\n-/* { dg-final { scan-tree-dump \"Found COMPLEX_FMA\" \"slp1\" { xfail *-*-* } } } */\n+\n+/* { dg-final { scan-tree-dump-times \"add new stmt:\\[^\\n\\r]*COMPLEX_FMA\" 1 \"slp1\" { xfail *-*-* } } } */\n+/* { dg-final { scan-tree-dump \"Found COMPLEX_FMA\" \"slp1\" } } */\ndiff --git a/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mul-half-float.c b/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mul-half-float.c\nindex 259dd6b2e06..f74274ad034 100644\n--- a/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mul-half-float.c\n+++ b/gcc/testsuite/gcc.dg/vect/complex/bb-slp-complex-mul-half-float.c\n@@ -8,5 +8,7 @@\n #define N 16\n #include \"complex-mul-template.c\"\n \n-/* { dg-final { scan-tree-dump \"Found COMPLEX_MUL_CONJ\" \"slp1\" { xfail *-*-* } } } */\n-/* { dg-final { scan-tree-dump \"Found COMPLEX_MUL\" \"slp1\" { xfail *-*-* } } } */\n+/* { dg-final { scan-tree-dump-times \"add new stmt:\\[^\\n\\r]*COMPLEX_MUL_CONJ\" 1 \"slp1\" { xfail *-*-* } } } */\n+/* { dg-final { scan-tree-dump \"Found COMPLEX_MUL_CONJ\" \"slp1\" } } */\n+/* { dg-final { scan-tree-dump-times \"add new stmt:\\[^\\n\\r]*COMPLEX_MUL\" 1 \"slp1\" { xfail *-*-* } } } */\n+/* { dg-final { scan-tree-dump \"Found COMPLEX_MUL\" \"slp1\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\nindex 07d71a63414..98e8ac3c785 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\n@@ -30,12 +30,14 @@ vec_slp_##TYPE (TYPE *restrict a, TYPE b, TYPE c, int n)\t\\\n TEST_ALL (VEC_PERM)\n \n /* We should use one DUP for each of the 8-, 16- and 32-bit types,\n- although we currently use LD1RW for _Float16. We should use two\n+ (for now, insert both elements with umov + ins for _Float16). We should use two\n DUPs for each of the three 64-bit types. */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.h, [hw]} 2 } } */\n-/* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.s, [sw]} 2 } } */\n-/* { dg-final { scan-assembler-times {\\tld1rw\\tz[0-9]+\\.s, } 1 } } */\n+/* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.s, [sw]} 3 } } */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.d, [dx]} 9 } } */\n+/* { dg-final { scan-assembler-times {\\tumov\\tw[0-9]+, v[0-9]+\\.h} 2 } } */\n+/* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[0\\], w[0-9]+} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[1\\], w[0-9]+} 1 } } */\n /* { dg-final { scan-assembler-times {\\tzip1\\tz[0-9]+\\.d, z[0-9]+\\.d, z[0-9]+\\.d\\n} 3 } } */\n /* { dg-final { scan-assembler-not {\\tzip2\\t} } } */\n \n@@ -53,7 +55,6 @@ TEST_ALL (VEC_PERM)\n /* { dg-final { scan-assembler-times {\\twhilelo\\tp[0-7]\\.s} 6 } } */\n /* { dg-final { scan-assembler-times {\\twhilelo\\tp[0-7]\\.d} 6 } } */\n /* { dg-final { scan-assembler-not {\\tldr} } } */\n-/* { dg-final { scan-assembler-times {\\tstr} 2 } } */\n-/* { dg-final { scan-assembler-times {\\tstr\\th[0-9]+} 2 } } */\n+/* { dg-final { scan-assembler-not {\\tstr} } } */\n \n /* { dg-final { scan-assembler-not {\\tuqdec} } } */\n", "prefixes": [ "1/4" ] }