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GET /api/patches/2228023/?format=api
{ "id": 2228023, "url": "http://patchwork.ozlabs.org/api/patches/2228023/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260424201814.230071-1-sumitg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424201814.230071-1-sumitg@nvidia.com>", "list_archive_url": null, "date": "2026-04-24T20:18:14", "name": "[v2] cpufreq: CPPC: add autonomous mode boot parameter support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b79e3a4f5cc85e266fa2f5f326e4d396678dc383", "submitter": { "id": 69778, "url": "http://patchwork.ozlabs.org/api/people/69778/?format=api", "name": "Sumit Gupta", "email": "sumitg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260424201814.230071-1-sumitg@nvidia.com/mbox/", "series": [ { "id": 501403, "url": "http://patchwork.ozlabs.org/api/series/501403/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501403", "date": "2026-04-24T20:18:14", "name": "[v2] cpufreq: CPPC: add autonomous mode boot parameter support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501403/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228023/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228023/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13955-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=dIV8kYTb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Sumit Gupta <sumitg@nvidia.com>", "To": "<rafael@kernel.org>, <viresh.kumar@linaro.org>, <pierre.gondois@arm.com>,\n\t<ionela.voinescu@arm.com>, <zhenglifeng1@huawei.com>,\n\t<zhanjie9@hisilicon.com>, <corbet@lwn.net>, <skhan@linuxfoundation.org>,\n\t<rdunlap@infradead.org>, <mario.limonciello@amd.com>,\n\t<linux-pm@vger.kernel.org>, <linux-doc@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "<linux-tegra@vger.kernel.org>, <treding@nvidia.com>,\n\t<jonathanh@nvidia.com>, <vsethi@nvidia.com>, <ksitaraman@nvidia.com>,\n\t<sanjayc@nvidia.com>, <mochs@nvidia.com>, <bbasu@nvidia.com>,\n\t<sumitg@nvidia.com>", "Subject": "[PATCH v2] cpufreq: CPPC: add autonomous mode boot parameter support", "Date": "Sat, 25 Apr 2026 01:48:14 +0530", "Message-ID": "<20260424201814.230071-1-sumitg@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH2PEPF00000145:EE_|PH7PR12MB6857:EE_", "X-MS-Office365-Filtering-Correlation-Id": "257a86f5-ef2a-43a8-df11-08dea23ec633", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700016|921020|13003099007|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tM6nixraRb6+hfkrj5gzb9NogRPFrDQUsiIeyDJ5q0x3wCGz0au2DNVAtzQ+PIDquGyEg+B2XTX59dBiMTYL7XLcQXGntEX0amrNK4gSNVfNJkGoZErkGvyXeni1AL0iu/CNQgj4BqvRZkNsEnfjqzXPjtN4mnp8ujkQysCIMwOqWLMC5SM02vU04T2IN/3pvy3ahfhmxe3K6BwrVVe0L2EtiFHlLt4ww1coWLrZ4DpyrLM/recYHmQv+8TuH8XR2tql1qX/8raWACOgTVh8c375ACny9ZEx9Ri1JncFWsoe0Vcy1W5hLNR+kQpUt1V//klfTwXqxA6KNrVOoKMMiyV5j+LMSRhXHR3yECdWB8FTPZiY06rpOpZ04C65iar4ppvN/Hyq2tXlzMbBpIRKG5+/b6RIUNWh2Fw7YrG9ypUVfDu33R3HOibk6I7flKLZ+iQY2ZiJL6uw3lTPWhF86WWIJxNvxCW5K1zE5SCKvxD6j+gXHtZ9xs74yChl8DYY8CFv+2aA+qmgJx1RSUxFlqQZAczOhzHhY4nKyg44Q7u7dqtTLD7JtCI/ng+yt9WagPqpnia80SrA9PEXf6b70277fyRKfpd4p0kb4pdXQk6qsE6KxTdP/WZMfk0hSUftcNi3TWx/+fp6i7IQcWhaP0qKzDyGK3IXh9pc+Fj9fvR68Kh5ZJta3H8JxJslJfrm3oWOxLSTOxZSIiBWlVH/jGEa2U069LmmCl11J8xbwqjGyaXC0ICCzdidRY30yxHHFwBPiC2nTG7LhmFbf9FjP2avTeuy5sqNdPpzQ0Q+G3jR4+zReEJzZEp4FKhhB/sLu", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700016)(921020)(13003099007)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tlc8cLpEWDnaxK3t71iqLSTQ2N+HFGHWhRqq7U5oXRxXeJErlh+Kq6TIXyeLi6WwWYqtGePGtEmG0qpFquBSxpK1XGQfY/WurMba9NEcYeSqkPGH/Mv7fzx/aegMOzr49VzewVZ9tCTsg6eQJA8z2SXmCbNjY9LMOtpetPceGVQroVyTk54hQoxtKDe4J7q6DsLrQMxlqDHOIClvtGDQsJO9muXsZszx5w7rrrIT5OfxqQ7V98B3zya0vJZks9WXF1mfnts+IEUJRU0W6241B2M5Nz9Its9g2njczI6Qqhb/FnOZP4nif2Kq2LaYnqYNfr9Yv15FtUyQyVFLwnn8QSjg+ro4rU3JNJ2WEXJ9uT0lfBKNjXJZ5HlSAkvHsibzB7X9N8ay8ziIY2jfhZmkwr4w3GcEAfu7LuSeBmJlQPoL8+xyky1APGCEl885hE/GU", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Apr 2026 20:19:22.8578\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 257a86f5-ef2a-43a8-df11-08dea23ec633", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCH2PEPF00000145.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB6857" }, "content": "Add a kernel boot parameter 'cppc_cpufreq.auto_sel_mode' to enable\nCPPC autonomous performance selection on all CPUs at system startup.\nWhen autonomous mode is enabled, the hardware automatically adjusts\nCPU performance based on workload demands using Energy Performance\nPreference (EPP) hints.\n\nWhen auto_sel_mode=1:\n- Configure all CPUs for autonomous operation on first init\n- Set EPP to performance preference (0x0)\n- Use HW min/max_perf when available; otherwise initialize from caps\n- Clamp desired_perf to bounds before enabling autonomous mode\n- Hardware controls frequency instead of the OS governor\n\nThe boot parameter is applied only during first policy initialization.\nSkip applying it on CPU hotplug to preserve runtime sysfs configuration.\n\nThis patch depends on patch [2] (\"cpufreq: Set policy->min and max\nas real QoS constraints\") so that the policy->min/max set in\ncppc_cpufreq_cpu_init() are not overridden by cpufreq_set_policy()\nduring init.\n\nReviewed-by: Randy Dunlap <rdunlap@infradead.org> (Documentation)\nSigned-off-by: Sumit Gupta <sumitg@nvidia.com>\n---\nv[1] -> v2:\n- Call cppc_set_enable() unconditionally so CPPC is enabled for both\n OS-driven and autonomous modes.\n- Init min/max from caps instead of cppc_cpufreq_update_perf_limits()\n as policy->min/max aren't yet populated.\n\n[1] https://lore.kernel.org/lkml/20260317151053.2361475-1-sumitg@nvidia.com/\n[2] https://lore.kernel.org/lkml/20260423084731.1090384-2-pierre.gondois@arm.com/\n---\n .../admin-guide/kernel-parameters.txt | 13 +++\n drivers/cpufreq/cppc_cpufreq.c | 89 +++++++++++++++++--\n 2 files changed, 97 insertions(+), 5 deletions(-)", "diff": "diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt\nindex 0a1abed1b93c..751817b0573a 100644\n--- a/Documentation/admin-guide/kernel-parameters.txt\n+++ b/Documentation/admin-guide/kernel-parameters.txt\n@@ -1067,6 +1067,19 @@ Kernel parameters\n \t\t\tpolicy to use. This governor must be registered in the\n \t\t\tkernel before the cpufreq driver probes.\n \n+\tcppc_cpufreq.auto_sel_mode=\n+\t\t\t[CPU_FREQ] Enable ACPI CPPC autonomous performance\n+\t\t\tselection. When enabled, hardware automatically adjusts\n+\t\t\tCPU frequency on all CPUs based on workload demands.\n+\t\t\tIn Autonomous mode, Energy Performance Preference (EPP)\n+\t\t\thints guide hardware toward performance (0x0) or energy\n+\t\t\tefficiency (0xff).\n+\t\t\tRequires ACPI CPPC autonomous selection register support.\n+\t\t\tFormat: <bool>\n+\t\t\tDefault: 0 (disabled)\n+\t\t\t0: use cpufreq governors\n+\t\t\t1: enable if supported by hardware\n+\n \tcpu_init_udelay=N\n \t\t\t[X86,EARLY] Delay for N microsec between assert and de-assert\n \t\t\tof APIC INIT to start processors. This delay occurs\ndiff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c\nindex 02db03d03755..672fc3058190 100644\n--- a/drivers/cpufreq/cppc_cpufreq.c\n+++ b/drivers/cpufreq/cppc_cpufreq.c\n@@ -28,6 +28,9 @@\n \n static struct cpufreq_driver cppc_cpufreq_driver;\n \n+/* Autonomous Selection boot parameter */\n+static bool auto_sel_mode;\n+\n #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE\n static enum {\n \tFIE_UNSET = -1,\n@@ -656,6 +659,14 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)\n \tcaps = &cpu_data->perf_caps;\n \tpolicy->driver_data = cpu_data;\n \n+\t/*\n+\t * Enable CPPC for both OS-driven and autonomous modes.\n+\t * The Enable register is optional - some platforms may not support it\n+\t */\n+\tret = cppc_set_enable(cpu, true);\n+\tif (ret && ret != -EOPNOTSUPP)\n+\t\tpr_warn(\"Failed to enable CPPC for CPU%d (%d)\\n\", cpu, ret);\n+\n \tmin = cppc_perf_to_khz(caps, caps->lowest_nonlinear_perf);\n \tmax = cppc_perf_to_khz(caps, policy->boost_enabled ?\n \t\t\tcaps->highest_perf : caps->nominal_perf);\n@@ -711,11 +722,71 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)\n \tpolicy->cur = cppc_perf_to_khz(caps, caps->highest_perf);\n \tcpu_data->perf_ctrls.desired_perf = caps->highest_perf;\n \n-\tret = cppc_set_perf(cpu, &cpu_data->perf_ctrls);\n-\tif (ret) {\n-\t\tpr_debug(\"Err setting perf value:%d on CPU:%d. ret:%d\\n\",\n-\t\t\t caps->highest_perf, cpu, ret);\n-\t\tgoto out;\n+\t/*\n+\t * Enable autonomous mode on first init if boot param is set.\n+\t * Check last_governor to detect first init and skip if auto_sel\n+\t * is already enabled.\n+\t */\n+\tif (auto_sel_mode && policy->last_governor[0] == '\\0' &&\n+\t !cpu_data->perf_ctrls.auto_sel) {\n+\t\t/* Init min/max_perf from caps if not already set by HW. */\n+\t\tif (!cpu_data->perf_ctrls.min_perf)\n+\t\t\tcpu_data->perf_ctrls.min_perf = caps->lowest_nonlinear_perf;\n+\t\tif (!cpu_data->perf_ctrls.max_perf)\n+\t\t\tcpu_data->perf_ctrls.max_perf = policy->boost_enabled ?\n+\t\t\t\tcaps->highest_perf : caps->nominal_perf;\n+\n+\t\tcpu_data->perf_ctrls.desired_perf =\n+\t\t\tclamp_t(u32, cpu_data->perf_ctrls.desired_perf,\n+\t\t\t\tcpu_data->perf_ctrls.min_perf,\n+\t\t\t\tcpu_data->perf_ctrls.max_perf);\n+\n+\t\tpolicy->cur = cppc_perf_to_khz(caps,\n+\t\t\t\t\t cpu_data->perf_ctrls.desired_perf);\n+\n+\t\t/* EPP is optional - some platforms may not support it */\n+\t\tret = cppc_set_epp(cpu, CPPC_EPP_PERFORMANCE_PREF);\n+\t\tif (ret && ret != -EOPNOTSUPP)\n+\t\t\tpr_warn(\"Failed to set EPP for CPU%d (%d)\\n\", cpu, ret);\n+\t\telse if (!ret)\n+\t\t\tcpu_data->perf_ctrls.energy_perf = CPPC_EPP_PERFORMANCE_PREF;\n+\n+\t\t/* Program min/max/desired into CPPC regs before enabling auto_sel. */\n+\t\tret = cppc_set_perf(cpu, &cpu_data->perf_ctrls);\n+\t\tif (ret) {\n+\t\t\tpr_debug(\"Err setting perf for autonomous mode CPU:%d ret:%d\\n\",\n+\t\t\t\t cpu, ret);\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tret = cppc_set_auto_sel(cpu, true);\n+\t\tif (ret && ret != -EOPNOTSUPP) {\n+\t\t\tpr_warn(\"Failed autonomous config for CPU%d (%d)\\n\",\n+\t\t\t\tcpu, ret);\n+\t\t\tgoto out;\n+\t\t}\n+\t\tif (!ret)\n+\t\t\tcpu_data->perf_ctrls.auto_sel = true;\n+\t}\n+\n+\tif (cpu_data->perf_ctrls.auto_sel) {\n+\t\t/* Sync policy limits from HW when autonomous mode is active */\n+\t\tpolicy->min = cppc_perf_to_khz(caps,\n+\t\t\t\t\t cpu_data->perf_ctrls.min_perf ?:\n+\t\t\t\t\t caps->lowest_nonlinear_perf);\n+\t\tpolicy->max = cppc_perf_to_khz(caps,\n+\t\t\t\t\t cpu_data->perf_ctrls.max_perf ?:\n+\t\t\t\t\t (policy->boost_enabled ?\n+\t\t\t\t\t\tcaps->highest_perf :\n+\t\t\t\t\t\tcaps->nominal_perf));\n+\t} else {\n+\t\t/* Normal mode: governors control frequency */\n+\t\tret = cppc_set_perf(cpu, &cpu_data->perf_ctrls);\n+\t\tif (ret) {\n+\t\t\tpr_debug(\"Err setting perf value:%d on CPU:%d. ret:%d\\n\",\n+\t\t\t\t caps->highest_perf, cpu, ret);\n+\t\t\tgoto out;\n+\t\t}\n \t}\n \n \tcppc_cpufreq_cpu_fie_init(policy);\n@@ -1035,10 +1106,18 @@ static int __init cppc_cpufreq_init(void)\n \n static void __exit cppc_cpufreq_exit(void)\n {\n+\tunsigned int cpu;\n+\n+\tfor_each_present_cpu(cpu)\n+\t\tcppc_set_auto_sel(cpu, false);\n+\n \tcpufreq_unregister_driver(&cppc_cpufreq_driver);\n \tcppc_freq_invariance_exit();\n }\n \n+module_param(auto_sel_mode, bool, 0444);\n+MODULE_PARM_DESC(auto_sel_mode, \"Enable CPPC autonomous performance selection at boot\");\n+\n module_exit(cppc_cpufreq_exit);\n MODULE_AUTHOR(\"Ashwin Chaugule\");\n MODULE_DESCRIPTION(\"CPUFreq driver based on the ACPI CPPC v5.0+ spec\");\n", "prefixes": [ "v2" ] }