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GET /api/patches/2227976/?format=api
{ "id": 2227976, "url": "http://patchwork.ozlabs.org/api/patches/2227976/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424155646.533334-1-luc.michel@amd.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424155646.533334-1-luc.michel@amd.com>", "list_archive_url": null, "date": "2026-04-24T15:56:44", "name": "hw/core/register: add register_array_get_owner", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "617d0b437a6ee2172b339123669bb2dacd19184d", "submitter": { "id": 87387, "url": "http://patchwork.ozlabs.org/api/people/87387/?format=api", "name": "Luc Michel", "email": "luc.michel@amd.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424155646.533334-1-luc.michel@amd.com/mbox/", "series": [ { "id": 501389, "url": "http://patchwork.ozlabs.org/api/series/501389/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501389", "date": "2026-04-24T15:56:44", "name": "hw/core/register: add register_array_get_owner", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501389/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227976/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227976/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=xgY6bbv5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=satlexmb08.amd.com; pr=C", "None (SATLEXMB04.amd.com: luc.michel@amd.com does not designate\n permitted sender hosts)", "permerror client-ip=2a01:111:f403:c105::7;\n envelope-from=Luc.Michel@amd.com;\n helo=CH4PR04CU002.outbound.protection.outlook.com" ], "From": "Luc Michel <luc.michel@amd.com>", "To": "<qemu-devel@nongnu.org>", "CC": "Luc Michel <luc.michel@amd.com>, Thomas Huth <thuth@redhat.com>,\n \"Peter Maydell\" <peter.maydell@linaro.org>,\n Francisco Iglesias <francisco.iglesias@amd.com>,\n Frederic Konrad <frederic.konrad@amd.com>,\n \"Edgar E . Iglesias\" <edgar.iglesias@amd.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n \"Alistair Francis\" <alistair@alistair23.me>, <qemu-arm@nongnu.org>", "Subject": "[PATCH] hw/core/register: add register_array_get_owner", "Date": "Fri, 24 Apr 2026 17:56:44 +0200", "Message-ID": "<20260424155646.533334-1-luc.michel@amd.com>", "X-Mailer": "git-send-email 2.53.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A103:EE_|DS2PR12MB9752:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3dee10cd-84b4-4486-2b1e-08dea21a259b", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|82310400026|376014|36860700016|13003099007|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n hFwi0VOatTt17NNsWvm6V6iiwlIGKqlO0dDwqQ4vdRY43uAVAFIQ6SOkArkcWvtkxpN0Bfw5MiOorCqCIePNQY9bzy/JSL/k/mZUzm3Va1QwjR014mue/zaVuQafeR3ahTPFi6iuN9h74vF8L+AfrhgcpLPV1VGdP21UXdCjc9rAl2WRp3EtDZxV6c0uFOG6nSwx/gfA5C8Nq6dW6rEeIWOrPNpnWBLAmcbTRAbZvJQdA2J4UQv0x10Wji6mMK0LhJAGo5cYVXQTzi8CK7kWxl1FlGf8AHDt2cZ2580TyiQW8uMvno0WThXLELZmkbZRH1rLbMvYr5ckggkQStnB7DDI82+16RwQkRIZidLIXTUjvt3V2+TUGeRUnwkc5y0oSX+hXTeIW8rYLNqBcf7Wm3Qwik3NDTgMJW+S8pSwJ/AkzhrarMDScPfNPQEyHoEON528RLJI73BAXQnxPYkgd8jdxcMoUgKwDJqxR9T7bGi7J+Ok3Vs2z/9JrpZQHpTo4rDVhtxbLcKQqm5VGNGbS4TxHpcwYJDV1NNX6mPEMOimEZxSEjSnoJAgYYCYa56He+xD6OG3tL80SW85Yp0d0uo0CiBHKbXy9UiHZ/3l2CSGPEBRuFVcflAUopJg6WaNFiIEDxQAkSvQPS50C0pv9NG/PAT+fCYmhlLURZrKqT2U9L2Ex0AYwIkTqD5kc+PEtUSoB5kSn94VygY6QLsOQg93cFUgaCV5HUCXLdAYRFs=", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:satlexmb08.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(13003099007)(56012099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n yPTbFYFPlRZuEcMM9aF8fKlmCDklQ3b5jYBxc8+xw7RYN9rQnfsRTWe0EV1V6CS54kgo8yk+aGK9jyc1cq7Hwvt4ZoWD5Y+z54om0MgLNzhXiejb17oqAKOHVpdOUCVczOTSF0FpI8Up3cLRV6/cpZma3WSD69HLdOZvAnbesLbxcoeA/HOxIkJf6dokhITqeo76yKzKOq3H9mlXbwuSZ+sPz47pgvh3HzFUT1+gPyXEUT2WKo12AD1VkrXOZuNbYtQnnNU6zwqUnvGji+NFOLH6LATfcgaj/QduOhXXyKoGIl1IcBu0IGcwi/k7kvgukq2ucqpwNPAalWKQv7JG8PFlTYa7oT7xytgQC7xptXi6Q4ClJ2GxaD+NmbeHQpMa/gESgI6vJKZs5yWfJzaKxtKu875yw5YJEijI8vZdJ71mFV4WKCg72SMHlyo2Qa9d", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Apr 2026 15:57:11.6595 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3dee10cd-84b4-4486-2b1e-08dea21a259b", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[satlexmb08.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A103.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS2PR12MB9752", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add the register_array_get_owner function to the register API. This\nfunction can be used to retrieve the device owning the given\nRegisterInfoArray.\n\nThis was previously done inline by some devices.\n5c6367bc1c8850f74812eeaaf87cff9911be58de modified the way register\nblocks are created and parented to the device. Since this is an\nimplementation detail of the register API, it makes sense to have a\nfunction for this.\n\nUse it in the Versal OSPI and Versal/ZynqMP eFuse models instead of\ntinkering with the API internals.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3421\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3422\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3423\nSigned-off-by: Luc Michel <luc.michel@amd.com>\n---\n include/hw/core/register.h | 11 +++++++++++\n hw/core/register.c | 5 +++++\n hw/nvram/xlnx-versal-efuse-ctrl.c | 4 ++--\n hw/nvram/xlnx-zynqmp-efuse.c | 4 ++--\n hw/ssi/xlnx-versal-ospi.c | 10 +++-------\n 5 files changed, 23 insertions(+), 11 deletions(-)", "diff": "diff --git a/include/hw/core/register.h b/include/hw/core/register.h\nindex 1f265f4ed71..c6f648fe95e 100644\n--- a/include/hw/core/register.h\n+++ b/include/hw/core/register.h\n@@ -207,6 +207,17 @@ RegisterInfoArray *register_init_block64(DeviceState *owner,\n uint64_t *data,\n const MemoryRegionOps *ops,\n bool debug_enabled,\n uint64_t memory_size);\n \n+/**\n+ * register_array_get_owner\n+ *\n+ * Retrieve the device owning the register info array @reg_array.\n+ *\n+ * @reg_array The register info array to retrieve the owner from\n+ *\n+ * Returns: the device owning @reg_array\n+ */\n+DeviceState *register_array_get_owner(const RegisterInfoArray *reg_array);\n+\n #endif\ndiff --git a/hw/core/register.c b/hw/core/register.c\nindex c3f3c936e70..99ca5e17758 100644\n--- a/hw/core/register.c\n+++ b/hw/core/register.c\n@@ -320,10 +320,15 @@ static void register_array_finalize(Object *obj)\n RegisterInfoArray *r_array = REGISTER_ARRAY(obj);\n \n g_free(r_array->r);\n }\n \n+DeviceState *register_array_get_owner(const RegisterInfoArray *reg_array)\n+{\n+ return DEVICE(OBJECT(reg_array)->parent);\n+}\n+\n static const TypeInfo register_array_info = {\n .name = TYPE_REGISTER_ARRAY,\n .parent = TYPE_OBJECT,\n .instance_size = sizeof(RegisterInfoArray),\n .instance_finalize = register_array_finalize,\ndiff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c\nindex 69acdfa3047..f5d5587cb65 100644\n--- a/hw/nvram/xlnx-versal-efuse-ctrl.c\n+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c\n@@ -617,15 +617,15 @@ static const RegisterAccessInfo efuse_ctrl_regs_info[] = {\n static void efuse_ctrl_reg_write(void *opaque, hwaddr addr,\n uint64_t data, unsigned size)\n {\n RegisterInfoArray *reg_array = opaque;\n XlnxVersalEFuseCtrl *s;\n- Object *dev;\n+ DeviceState *dev;\n \n assert(reg_array != NULL);\n \n- dev = reg_array->mem.owner;\n+ dev = register_array_get_owner(reg_array);\n assert(dev);\n \n s = XLNX_VERSAL_EFUSE_CTRL(dev);\n \n if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {\ndiff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c\nindex e6bc54fc6bd..028120f824d 100644\n--- a/hw/nvram/xlnx-zynqmp-efuse.c\n+++ b/hw/nvram/xlnx-zynqmp-efuse.c\n@@ -722,15 +722,15 @@ static RegisterAccessInfo zynqmp_efuse_regs_info[] = {\n static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr,\n uint64_t data, unsigned size)\n {\n RegisterInfoArray *reg_array = opaque;\n XlnxZynqMPEFuse *s;\n- Object *dev;\n+ DeviceState *dev;\n \n assert(reg_array != NULL);\n \n- dev = reg_array->mem.owner;\n+ dev = register_array_get_owner(reg_array);\n assert(dev);\n \n s = XLNX_ZYNQMP_EFUSE(dev);\n \n if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {\ndiff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c\nindex 467f0ce7033..e25e4c26c2e 100644\n--- a/hw/ssi/xlnx-versal-ospi.c\n+++ b/hw/ssi/xlnx-versal-ospi.c\n@@ -1567,19 +1567,15 @@ static RegisterAccessInfo ospi_regs_info[] = {\n .ro = 0xffffffff,\n }\n };\n \n /* Return dev-obj from reg-region created by register_init_block32 */\n-static XlnxVersalOspi *xilinx_ospi_of_mr(void *mr_accessor)\n+static XlnxVersalOspi *xilinx_ospi_of_mr(void *opaque)\n {\n- RegisterInfoArray *reg_array = mr_accessor;\n- Object *dev;\n+ RegisterInfoArray *reg_array = REGISTER_ARRAY(opaque);\n \n- dev = reg_array->mem.owner;\n- assert(dev);\n-\n- return XILINX_VERSAL_OSPI(dev);\n+ return XILINX_VERSAL_OSPI(register_array_get_owner(reg_array));\n }\n \n static void ospi_write(void *opaque, hwaddr addr, uint64_t value,\n unsigned int size)\n {\n", "prefixes": [] }