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GET /api/patches/2227924/?format=api
{ "id": 2227924, "url": "http://patchwork.ozlabs.org/api/patches/2227924/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/edfc5087-184d-4eb8-a542-e7c60446f55a@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<edfc5087-184d-4eb8-a542-e7c60446f55a@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-24T13:40:18", "name": "[to-be-committed,RISC-V,PR,rtl-optimization/80770] Canonicalize extending byte loads for RISC-V", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f0868dc46ac5687b5f96306162b12836f29ceb35", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/edfc5087-184d-4eb8-a542-e7c60446f55a@oss.qualcomm.com/mbox/", "series": [ { "id": 501367, "url": "http://patchwork.ozlabs.org/api/series/501367/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501367", "date": "2026-04-24T13:40:18", "name": "[to-be-committed,RISC-V,PR,rtl-optimization/80770] Canonicalize extending byte loads for RISC-V", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501367/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227924/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227924/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Cw9+VN1N;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=bRnqQe38;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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boundary=\"------------uqM6f3XxBT27tjv0JAyY0lUV\"", "Message-ID": "<edfc5087-184d-4eb8-a542-e7c60446f55a@oss.qualcomm.com>", "Date": "Fri, 24 Apr 2026 07:40:18 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "Cc": "Shreya Munnangi <smunnang@qti.qualcomm.com>", "Subject": "[to-be-committed][RISC-V][PR rtl-optimization/80770] Canonicalize\n extending byte loads for RISC-V", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI0MDEzMSBTYWx0ZWRfXwycog2uRzfP0\n yeS5+6Bvd0P8tvxwzSjUknmnqYm4OKynEK/vaY/AzOGE1rFYJ3z6vCDk0gdrVE7Ypn5zq4K76/Z\n jTMwvpMH/hfoyrVV3xmcvAn2pkRLvhE8GKd753R5aSseWuC1B7dEtQrOyYDAT+a3h67e2KmLnhN\n z34yTAUi+1YSEO1dqkIi9LecBfwMa25Rlft/TOoR6W8y5adg4wDtUyZDFjE6ndb8nAat7ieyZPp\n KzwWnYZ1Z9M3mwsu/fZNt/4hz1A5yCwQeQbnRb0PLY9NQmeMYoi2bE5jiGPh0T//zmUMmLPovr1\n 1NiwQoC8TwYEK50tKHX0zH6A2BSK1Aaxop2R0hyVtLUlatbFn4keqwuEFo3lmAEQUrKTTAC6jol\n pD4ThWb3Ntk4SKZ+W0GiDrbqcwr5wiwywJhuS8V/bhI6bRZTuFCGKlNYi/8m3o9iMUUUlK7E8Yv\n jpSRatHhKZQitqVA7zw==", "X-Authority-Analysis": "v=2.4 cv=FPMrAeos c=1 sm=1 tr=0 ts=69eb72c5 cx=c_pps\n a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=sX-c-GXsyg2-v-arBi0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=D48PxN1h12nwWOO2MEAA:9 a=B2y7HmGcmWMA:10 a=6Ab_bkdmUrQuMsNx7PHu:22", "X-Proofpoint-GUID": "iaBTNM0q5PAkZRmQOmRvoVaP6hAdMTHP", "X-Proofpoint-ORIG-GUID": "iaBTNM0q5PAkZRmQOmRvoVaP6hAdMTHP", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-24_01,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 phishscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0\n adultscore=0 impostorscore=0 priorityscore=1501 spamscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604240131", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "In the process of debugging pr80770 with Shreya it became apparent that \na failure to CSE certain memory references was inhibiting Shreya's RTL \nsimplification from firing in all the cases we cared about as the \nsimplifier requires two operands to be the same pseudo.\n\nThe failure to CSE stems from having two QI loads which are sign \nextended to different sized destinations. As it turns out the code to \nfix that was something I already had in flight as it's a small piece of \neliminating a few define_insn_and_split patterns (or simplifying them \ndown to just a define_split).\n\nTo expose the missed CSE what we really want to do is extend the value \nout to word mode in a temporary, then use a lowpart extraction to set \nthe real destination. The key being we haven't changed the size of the \nload, just how widely it gets extended. Think of it as canonicalization \nfor the purposes of CSE.\n\nThis isn't the full set of changes I had in flight in that space, but \ndoes clean things up enough for QImode loads to get CSE'd better and is \nenough to trigger Shreya's pr80770 changes consistently for the \ntestcodes we have on RISC-V.\n\nThis has been spinning in my tester for a while. So it's clean on \nriscv64-elf, riscv32-elf as well as bootstrapped and regression tested \non the Pioneer and BPI-F3. I'll wait for the pre-commit tester to do \nits thing before pushing to the trunk.\n\nIn case it's not obvious, I'm focused on trickling RISC-V target \nimprovements right now so as not to potentially interfere with the \nrelease process. So this doesn't include Shreya's simplify-rtx.cc changes.\n\nJeff", "diff": "diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 3fe0ad0ccdf4..7e9205fb24bf 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -1916,7 +1916,25 @@ (define_expand \"zero_extendqi<SUPERQI:mode>2\"\n [(set (match_operand:SUPERQI 0 \"register_operand\")\n \t(zero_extend:SUPERQI\n \t (match_operand:QI 1 \"nonimmediate_operand\")))]\n- \"\")\n+ \"\"\n+{\n+ /* If the destination is not a full word, then do a zero extended\n+ load to a full word and a sub-word extraction to get at the\n+ appropriate low bits. This enables more CSE of memory references\n+ by having a canonical form. That in turn can help other optimizations\n+ as well. */\n+ if (<SUPERQI:MODE>mode != word_mode)\n+ {\n+ rtx tdest = gen_reg_rtx (word_mode);\n+ emit_move_insn (tdest, gen_rtx_ZERO_EXTEND (word_mode, operands[1]));\n+ tdest = gen_lowpart (<SUPERQI:MODE>mode, tdest);\n+ SUBREG_PROMOTED_VAR_P (tdest) = 1;\n+ SUBREG_PROMOTED_SET (tdest, SRP_UNSIGNED);\n+ emit_move_insn (operands[0], tdest);\n+ DONE;\n+ }\n+})\n+\n \n (define_insn \"*zero_extendqi<SUPERQI:mode>2_internal\"\n [(set (match_operand:SUPERQI 0 \"register_operand\" \"=r,r\")\n@@ -1966,7 +1984,24 @@ (define_insn \"*extendsidi2_internal\"\n (define_expand \"extend<SHORT:mode><SUPERQI:mode>2\"\n [(set (match_operand:SUPERQI 0 \"register_operand\")\n \t(sign_extend:SUPERQI (match_operand:SHORT 1 \"nonimmediate_operand\")))]\n- \"\")\n+ \"\"\n+{\n+ /* If the destination is not a full word, then do a sign extended\n+ load to a full word and a sub-word extraction to get at the\n+ appropriate low bits. This enables more CSE of memory references\n+ by having a canonical form. That in turn can help other optimizations\n+ as well. */\n+ if (<SUPERQI:MODE>mode != word_mode)\n+ {\n+ rtx tdest = gen_reg_rtx (word_mode);\n+ emit_move_insn (tdest, gen_rtx_SIGN_EXTEND (word_mode, operands[1]));\n+ tdest = gen_lowpart (<SUPERQI:MODE>mode, tdest);\n+ SUBREG_PROMOTED_VAR_P (tdest) = 1;\n+ SUBREG_PROMOTED_SET (tdest, SRP_SIGNED);\n+ emit_move_insn (operands[0], tdest);\n+ DONE;\n+ }\n+})\n \n (define_insn_and_split \"*extend<SHORT:mode><SUPERQI:mode>2\"\n [(set (match_operand:SUPERQI 0 \"register_operand\" \"=r,r\")\n", "prefixes": [ "to-be-committed", "RISC-V", "PR", "rtl-optimization/80770" ] }