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{
    "id": 2227825,
    "url": "http://patchwork.ozlabs.org/api/patches/2227825/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424102800.24022-5-frank.chang@sifive.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
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    "msgid": "<20260424102800.24022-5-frank.chang@sifive.com>",
    "list_archive_url": null,
    "date": "2026-04-24T10:28:00",
    "name": "[4/4] target/riscv: Expose Zicclsm extension as a CPU property",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "a303f0aff95fc4a1c16e4f315acb6429078410f9",
    "submitter": {
        "id": 79604,
        "url": "http://patchwork.ozlabs.org/api/people/79604/?format=api",
        "name": "Frank Chang",
        "email": "frank.chang@sifive.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424102800.24022-5-frank.chang@sifive.com/mbox/",
    "series": [
        {
            "id": 501338,
            "url": "http://patchwork.ozlabs.org/api/series/501338/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501338",
            "date": "2026-04-24T10:27:56",
            "name": "Support the true Zicclsm extension",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/501338/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2227825/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2227825/checks/",
    "tags": {},
    "related": [],
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        "From": "frank.chang@sifive.com",
        "To": "qemu-devel@nongnu.org",
        "Cc": "Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>,\n Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>,\n qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs),\n Frank Chang <frank.chang@sifive.com>, Max Chou <max.chou@sifive.com>",
        "Subject": "[PATCH 4/4] target/riscv: Expose Zicclsm extension as a CPU property",
        "Date": "Fri, 24 Apr 2026 18:28:00 +0800",
        "Message-ID": "<20260424102800.24022-5-frank.chang@sifive.com>",
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    },
    "content": "From: Frank Chang <frank.chang@sifive.com>\n\nExpose Zicclsm extension as a CPU property to allow user to turn on/off\nZicclsm extension.\n\nZicclsm is set to true by default to be backward compatible with the old\nRISC-V QEMU design.\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\nReviewed-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/cpu.c | 2 ++\n 1 file changed, 2 insertions(+)",
    "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex df56b64a736..7f5e06ef83d 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -1327,6 +1327,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {\n     MULTI_EXT_CFG_BOOL(\"zicbop\", ext_zicbop, true),\n     MULTI_EXT_CFG_BOOL(\"zicboz\", ext_zicboz, true),\n \n+    MULTI_EXT_CFG_BOOL(\"zicclsm\", ext_zicclsm, true),\n+\n     MULTI_EXT_CFG_BOOL(\"zmmul\", ext_zmmul, false),\n \n     MULTI_EXT_CFG_BOOL(\"zca\", ext_zca, false),\n",
    "prefixes": [
        "4/4"
    ]
}