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GET /api/patches/2227674/?format=api
{ "id": 2227674, "url": "http://patchwork.ozlabs.org/api/patches/2227674/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-30-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424043014.46305-30-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-24T04:30:03", "name": "[v2,29/40] target/arm: Implement F1CVT, F1CVTL, F2CVT, F2CVTL for SME", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "885d6bd32128929338a404ed2ae6d0b3adfbf1a4", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-30-richard.henderson@linaro.org/mbox/", "series": [ { "id": 501300, "url": "http://patchwork.ozlabs.org/api/series/501300/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300", "date": "2026-04-24T04:29:37", "name": "target/arm: Implement FEAT_FP8", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501300/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227674/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227674/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=KL+pV7E3;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20T61s2Qz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 24 Apr 2026 14:33:30 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wG8DO-0002R8-HM; Fri, 24 Apr 2026 00:32:30 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8DJ-00026p-BG\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:25 -0400", "from mail-oa1-x35.google.com ([2001:4860:4864:20::35])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8DH-0003Xu-Am\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:25 -0400", "by mail-oa1-x35.google.com with SMTP id\n 586e51a60fabf-42fe552aedeso528782fac.0\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 21:32:22 -0700 (PDT)", "from stoup.. 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helo=mail-oa1-x35.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 +\n target/arm/tcg/fp8_helper.c | 79 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-sme.c | 5 ++\n target/arm/tcg/sme.decode | 5 ++\n 4 files changed, 91 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 3021dafd44..b5dc2b7064 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -10,3 +10,5 @@ DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 32c7a82647..2b1955508d 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -264,6 +264,50 @@ void HELPER(sme2_bfcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n fp8_finish(env, &ctx);\n }\n \n+void HELPER(sme2_fcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0xf);\n+ uint8_t *n = vn;\n+ uint16_t *d0 = vd;\n+ uint16_t *d1 = vd + sizeof(ARMVectorReg);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ ARMVectorReg scratch;\n+\n+ if (vectors_overlap(vd, 2, vn, 1)) {\n+ n = memcpy(&scratch, vn, oprsz);\n+ }\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(i)];\n+ d0[H2(i)] = float8_e5m2_to_float16(e, ctx.scale, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(i) + nelem];\n+ d1[H2(i)] = float8_e5m2_to_float16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(i)];\n+ d0[H2(i)] = float8_e4m3_to_float16(e, ctx.scale, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(i) + nelem];\n+ d1[H2(i)] = float8_e4m3_to_float16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ float16_invalid_input(d0, nelem, &ctx.stat);\n+ memcpy(d1, d0, oprsz);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n void HELPER(sme2_bfcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n@@ -298,3 +342,38 @@ void HELPER(sme2_bfcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+void HELPER(sme2_fcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0xf);\n+ uint8_t *n = vn;\n+ uint16_t *d0 = vd;\n+ uint16_t *d1 = vd + sizeof(ARMVectorReg);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e0 = n[H1(2 * i + 0)];\n+ float8_e5m2 e1 = n[H1(2 * i + 1)];\n+ d0[H2(i)] = float8_e5m2_to_float16(e0, ctx.scale, &ctx.stat);\n+ d1[H2(i)] = float8_e5m2_to_float16(e1, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e0 = n[H1(2 * i + 0)];\n+ float8_e4m3 e1 = n[H1(2 * i + 1)];\n+ d0[H2(i)] = float8_e4m3_to_float16(e0, ctx.scale, &ctx.stat);\n+ d1[H2(i)] = float8_e4m3_to_float16(e1, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ float16_invalid_input(d0, nelem, &ctx.stat);\n+ memcpy(d1, d0, oprsz);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 3e1da83535..29d116a57a 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -1545,6 +1545,11 @@ static bool do_f8cvt(DisasContext *s, arg_zz_n *a,\n return true;\n }\n \n+TRANS_FEAT(F1CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvt_hb, 0)\n+TRANS_FEAT(F2CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvt_hb, 1)\n+TRANS_FEAT(F1CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvtl_hb, 0)\n+TRANS_FEAT(F2CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvtl_hb, 1)\n+\n TRANS_FEAT(BF1CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 0)\n TRANS_FEAT(BF2CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 1)\n TRANS_FEAT(BF1CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 0)\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex df9586c1a5..d6192eb59d 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -853,6 +853,11 @@ UUNPK_4bh 11000001 011 10101 111000 ....0 ...01 @zz_4x2_n1\n UUNPK_4hs 11000001 101 10101 111000 ....0 ...01 @zz_4x2_n1\n UUNPK_4sd 11000001 111 10101 111000 ....0 ...01 @zz_4x2_n1\n \n+F1CVT 11000001 001 00110 111000 ..... ....0 @zz_2x1\n+F2CVT 11000001 101 00110 111000 ..... ....0 @zz_2x1\n+F1CVTL 11000001 001 00110 111000 ..... ....1 @zz_2x1\n+F2CVTL 11000001 101 00110 111000 ..... ....1 @zz_2x1\n+\n BF1CVT 11000001 011 00110 111000 ..... ....0 @zz_2x1\n BF2CVT 11000001 111 00110 111000 ..... ....0 @zz_2x1\n BF1CVTL 11000001 011 00110 111000 ..... ....1 @zz_2x1\n", "prefixes": [ "v2", "29/40" ] }