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GET /api/patches/2227657/?format=api
{ "id": 2227657, "url": "http://patchwork.ozlabs.org/api/patches/2227657/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424042946.3875690-3-frank.chang@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424042946.3875690-3-frank.chang@sifive.com>", "list_archive_url": null, "date": "2026-04-24T04:29:46", "name": "[v3,2/2] target/riscv: Add standard B extension implied rule", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "60c45d44a2e17ca85d8420156c235500cfd2f12c", "submitter": { "id": 79604, "url": "http://patchwork.ozlabs.org/api/people/79604/?format=api", "name": "Frank Chang", "email": "frank.chang@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424042946.3875690-3-frank.chang@sifive.com/mbox/", "series": [ { "id": 501299, "url": "http://patchwork.ozlabs.org/api/series/501299/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501299", "date": "2026-04-24T04:29:44", "name": "Add the implied rules for G and B extensions", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501299/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227657/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=NhClxl0s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x42d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Frank Chang <frank.chang@sifive.com>\n\nAdd the missing implied rule for standard B extension.\nStandard B extension implies Zba, Zbb, Zbs extensions.\nWe can also remove the auto-enables in riscv_cpu_validate_b()\nas Zba, Zbb, Zbs extensions can be enabled by the implied rule.\n\nRISC-V B spec: https://github.com/riscv/riscv-b\n\nReviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>\nReviewed-by: Jim Shu <jim.shu@sifive.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\n---\n target/riscv/cpu.c | 14 +++++++++++++-\n target/riscv/tcg/tcg-cpu.c | 18 +++---------------\n 2 files changed, 16 insertions(+), 16 deletions(-)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex f806d0536a0..e87d1b6cd9a 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2260,6 +2260,17 @@ static RISCVCPUImpliedExtsRule RVG_IMPLIED = {\n },\n };\n \n+static RISCVCPUImpliedExtsRule RVB_IMPLIED = {\n+ .is_misa = true,\n+ .ext = RVB,\n+ .implied_multi_exts = {\n+ CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),\n+ CPU_CFG_OFFSET(ext_zbs),\n+\n+ RISCV_IMPLIED_EXTS_RULE_END\n+ },\n+};\n+\n static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {\n .ext = CPU_CFG_OFFSET(ext_zcb),\n .implied_multi_exts = {\n@@ -2647,7 +2658,8 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {\n \n RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {\n &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,\n- &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL\n+ &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,\n+ &RVB_IMPLIED, NULL\n };\n \n RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 8247cf1b4c9..91751439752 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -564,27 +564,15 @@ static void riscv_cpu_validate_b(RISCVCPU *cpu)\n const char *warn_msg = \"RVB mandates disabled extension %s\";\n \n if (!cpu->cfg.ext_zba) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) {\n- cpu->cfg.ext_zba = true;\n- } else {\n- warn_report(warn_msg, \"zba\");\n- }\n+ warn_report(warn_msg, \"zba\");\n }\n \n if (!cpu->cfg.ext_zbb) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) {\n- cpu->cfg.ext_zbb = true;\n- } else {\n- warn_report(warn_msg, \"zbb\");\n- }\n+ warn_report(warn_msg, \"zbb\");\n }\n \n if (!cpu->cfg.ext_zbs) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) {\n- cpu->cfg.ext_zbs = true;\n- } else {\n- warn_report(warn_msg, \"zbs\");\n- }\n+ warn_report(warn_msg, \"zbs\");\n }\n }\n \n", "prefixes": [ "v3", "2/2" ] }