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GET /api/patches/2227640/?format=api
{ "id": 2227640, "url": "http://patchwork.ozlabs.org/api/patches/2227640/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/6fd41b32-bfd1-4fc0-a25f-fce4d898cbbe@yahoo.co.jp/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<6fd41b32-bfd1-4fc0-a25f-fce4d898cbbe@yahoo.co.jp>", "list_archive_url": null, "date": "2026-04-24T03:02:21", "name": "[1/4] xtensa: Implement \"__force_l32\" named address space", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "acd56e9dcf4671d99b5f64246367406c24c43a01", "submitter": { "id": 83997, "url": "http://patchwork.ozlabs.org/api/people/83997/?format=api", "name": "Takayuki 'January June' Suwa", "email": "jjsuwa_sys3175@yahoo.co.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/6fd41b32-bfd1-4fc0-a25f-fce4d898cbbe@yahoo.co.jp/mbox/", "series": [ { "id": 501290, "url": "http://patchwork.ozlabs.org/api/series/501290/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501290", "date": "2026-04-24T03:07:46", "name": "[1/4] xtensa: Implement \"__force_l32\" named address space", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501290/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227640/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227640/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=yahoo.co.jp header.i=@yahoo.co.jp header.a=rsa-sha256\n header.s=yahoocojp-202506 header.b=loXo/NlH;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1776999741;\n s=yahoocojp-202506; d=yahoo.co.jp;\n h=References:Content-Transfer-Encoding:Content-Type:Subject:From:Cc:To:MIME-Version:Date:Message-ID;\n bh=ef/Bz16jIYCzshRmjtzq18tgZl5KLRkTp1QScG3pt8o=;\n b=loXo/NlHLH1sa/L/rAv19HlxcSFNNu06tewMTb3ESMJpwcZlLRC64o9EAh2RJRe+\n 7r8L0bcRxvcTueod/YD3bElTYKTMY9PIzZ1BCUKWynSUEp8pN1hqJC/uMRpIyevZO7N\n ifnglIqPVS2UOgcR6lsBmTxWOi/VNogfTfh+AlLUHJU2QLBdT3Ri6C3OxhSC2WnMn8c\n u8U9E+K+2w2LfqnXAxaCDqzWTG1TriHCuLtJ0uDS5B2C3wh+MTOD8jQnuWDdXGTl2cL\n +RzLpGrsEfvJRxIdj7yTt5w1JnziG962uxCclSX0UFSlL6qcnkkqQhcxqKlczjkojef\n c9ZCEonvhg==", "Message-ID": "<6fd41b32-bfd1-4fc0-a25f-fce4d898cbbe@yahoo.co.jp>", "Date": "Fri, 24 Apr 2026 12:02:21 +0900", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "To": "gcc-patches@gcc.gnu.org", "Cc": "Max Filippov <jcmvbkbc@gmail.com>", "From": "Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>", "Subject": "[PATCH 1/4] xtensa: Implement \"__force_l32\" named address space", "Content-Type": "text/plain; charset=UTF-8; format=flowed", "Content-Transfer-Encoding": "7bit", "References": "<6fd41b32-bfd1-4fc0-a25f-fce4d898cbbe.ref@yahoo.co.jp>", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "In the Xtensa ISA, unless the memory regions for placing machine instructions\nare configured as \"unified,\" instructions other than specific 32-bit width\nload/store ones are not defined to be able to access data in such regions.\n\nIn such cases, data residing in the same memory area as the instructions,\neg., pre-configured constant tables or string literals, cannot be read using\nthe usual sub-word memory load instructions when reading them in units of\n1- or 2-bytes. Instead, a series of alternative instructions are needed to\nextract the desired sub-word bit by bit from the result of loading an aligned\nfull-word.\n\nThis patch introduces a new target-specific named address space \"__force_l32\"\nwhich indicates that such considerations are necessary when loading sub-words\nfrom memory.\n\n /* example #1 */\n struct foo {\n short a, b, c, d;\n };\n int test(void) {\n extern __force_l32 struct foo *p;\n return p->a * p->d;\n }\n\n ;; result #1 (-O2 -mlittle-endian)\n \t.literal_position\n \t.literal .LC0, p\n test:\n \tentry\tsp, 32\n \tl32r\ta9, .LC0\t;; the address of p\n \tmovi.n\ta8, -4\t\t;; consolidated by fwprop/CSE\n \tl32i.n\ta9, a9, 0\t;; the value of p\n \taddi.n\ta10, a9, 6\n \tand\ta2, a9, a8\t;; p->a : align to SImode\n \tand\ta8, a10, a8\t;; p->d : align to SImode\n \tl32i.n\ta2, a2, 0\t;; p->a : load:SI\n \tl32i.n\ta8, a8, 0\t;; p->d : load:SI\n \tssa8l\ta9\t\t;; p->a : shift to bit position 0\n \tsrl\ta2, a2\n \tssa8l\ta10\t\t;; p->d : shift to bit position 0\n \tsrl\ta8, a8\n \tmul16s\ta2, a2, a8\t;; mulhisi3\n \tretw.n\n\n /* example #2 */\n char *strcpy_irom(char *dst, __force_l32 const char *src) {\n char *p = dst;\n while (*p = *src)\n ++p, ++src;\n return dst;\n }\n\n ;; result #2 (-Os -mbig-endian)\n strcpy_irom:\n \tentry\tsp, 32\n \tmov.n\ta9, a2\n \tmovi.n\ta10, -4\t\t;; hoisted out\n \tj\t.L2\n .L3:\n \taddi.n\ta9, a9, 1\n \taddi.n\ta3, a3, 1\n .L2:\n \tand\ta8, a3, a10\t;; *src : align to SImode\n \tl32i.n\ta8, a8, 0\t;; *src : load:SI\n \tssa8b\ta3\t\t;; *src : shift to bit position 0\n \tsll\ta8, a8\n \textui\ta8, a8, 24, 8\t;; *src : zero_extract:QI\n \ts8i\ta8, a9, 0\t;; *p : store:QI\n \tbnez.n\ta8, .L3\n \tretw.n\n\ngcc/ChangeLog:\n\n\t* config/xtensa/xtensa-protos.h\n\t(xtensa_expand_load_force_l32): New function prototype.\n\t* config/xtensa/xtensa.cc (#include): Add \"expmed.h\".\n\t(TARGET_LEGITIMATE_ADDRESS_P):\n\tChange a whitespace delimiter from HTAB to SPACE.\n\t(TARGET_ADDR_SPACE_SUBSET_P, TARGET_ADDR_SPACE_CONVERT,\n\tTARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P):\n\tNew macro definitions for named address space.\n\t(xtensa_addr_space_subset_p, xtensa_addr_space_convert,\n\txtensa_addr_space_legitimate_address_p):\n\tNew hook function prototypes and definitions required for\n\timplementing the named address space.\n\t(xtensa_expand_load_force_l32): New function that generates RTXes\n\tthat perform loads from memory belonging to the named address\n\tspace.\n\t* config/xtensa/xtensa.h (ADDR_SPACE_FORCE_L32):\n\tNew macro for the ID# of the named address space.\n\t(REGISTER_TARGET_PRAGMAS): New hook for registering C language\n\tidentifier for the named address space.\n\t* config/xtensa/xtensa.md\n\t(zero_extend<mode>si2_internal): Rename from zero_extend<mode>si2.\n\t(zero_extend<mode>si2): New RTL generation pattern that calls\n\txtensa_expand_load_force_l32().\n\t(extendhisi2, extendqisi2, movhi, movqi):\n\tChange to call xtensa_expand_load_force_l32() first.\n---\n gcc/config/xtensa/xtensa-protos.h | 2 +\n gcc/config/xtensa/xtensa.cc | 138 +++++++++++++++++++++++++++++-\n gcc/config/xtensa/xtensa.h | 7 ++\n gcc/config/xtensa/xtensa.md | 26 +++++-\n 4 files changed, 169 insertions(+), 4 deletions(-)", "diff": "diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h\nindex 034549b61e0..71323354e79 100644\n--- a/gcc/config/xtensa/xtensa-protos.h\n+++ b/gcc/config/xtensa/xtensa-protos.h\n@@ -60,6 +60,8 @@ extern bool xtensa_tls_referenced_p (rtx);\n extern enum rtx_code xtensa_shlrd_which_direction (rtx, rtx);\n extern bool xtensa_postreload_completed_p (void);\n extern char *xtensa_bswapsi2_output (rtx_insn *, const char *);\n+extern bool xtensa_expand_load_force_l32 (rtx *, machine_mode, machine_mode,\n+\t\t\t\t\t int);\n \n #ifdef TREE_CODE\n extern void init_cumulative_args (CUMULATIVE_ARGS *, int);\ndiff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc\nindex 0dc878086a5..c3f7ebc7171 100644\n--- a/gcc/config/xtensa/xtensa.cc\n+++ b/gcc/config/xtensa/xtensa.cc\n@@ -48,6 +48,7 @@ along with GCC; see the file COPYING3. If not see\n #include \"varasm.h\"\n #include \"alias.h\"\n #include \"explow.h\"\n+#include \"expmed.h\"\n #include \"expr.h\"\n #include \"langhooks.h\"\n #include \"gimplify.h\"\n@@ -201,6 +202,10 @@ static rtx_insn *xtensa_md_asm_adjust (vec<rtx> &, vec<rtx> &,\n \t\t\t\t vec<machine_mode> &, vec<const char *> &,\n \t\t\t\t vec<rtx> &, vec<rtx> &, HARD_REG_SET &,\n \t\t\t\t location_t);\n+static bool xtensa_addr_space_subset_p (addr_space_t, addr_space_t);\n+static rtx xtensa_addr_space_convert (rtx, tree, tree);\n+static bool xtensa_addr_space_legitimate_address_p (machine_mode, rtx, bool,\n+\t\t\t\t\t\t addr_space_t, code_helper);\n \n \f\n \n@@ -292,7 +297,7 @@ static rtx_insn *xtensa_md_asm_adjust (vec<rtx> &, vec<rtx> &,\n #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem\n \n #undef TARGET_LEGITIMATE_ADDRESS_P\n-#define TARGET_LEGITIMATE_ADDRESS_P\txtensa_legitimate_address_p\n+#define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p\n \n #undef TARGET_FRAME_POINTER_REQUIRED\n #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required\n@@ -375,6 +380,16 @@ static rtx_insn *xtensa_md_asm_adjust (vec<rtx> &, vec<rtx> &,\n #undef TARGET_MD_ASM_ADJUST\n #define TARGET_MD_ASM_ADJUST xtensa_md_asm_adjust\n \n+#undef TARGET_ADDR_SPACE_SUBSET_P\n+#define TARGET_ADDR_SPACE_SUBSET_P xtensa_addr_space_subset_p\n+\n+#undef TARGET_ADDR_SPACE_CONVERT\n+#define TARGET_ADDR_SPACE_CONVERT xtensa_addr_space_convert\n+\n+#undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P\n+#define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P\t\\\n+\txtensa_addr_space_legitimate_address_p\n+\n struct gcc_target targetm = TARGET_INITIALIZER;\n \n \f\n@@ -2597,6 +2612,65 @@ xtensa_emit_add_imm (rtx dst, rtx src, HOST_WIDE_INT imm, rtx scratch,\n }\n \n \n+/* Expand a 1- or 2-byte width memory load into an aligned 4-byte width\n+ load with bit-extraction of the required bytes. */\n+\n+bool\n+xtensa_expand_load_force_l32 (rtx *operands, machine_mode dest_mode,\n+\t\t\t machine_mode src_mode, int unsignedp)\n+{\n+ rtx dest, src, addr, temp, x;\n+\n+ gcc_assert (src_mode == QImode || src_mode == HImode);\n+\n+ /* Reject sub-word store to memory within the __force_l32 address space. */\n+ if (mem_operand (dest = operands[0], dest_mode)\n+ && MEM_ADDR_SPACE (dest) == ADDR_SPACE_FORCE_L32)\n+ {\n+ error (\"Storing 1- and 2-byte quantities to memory within the \"\n+\t \"%<__force_l32%> address space is not supported\");\n+ return false;\n+ }\n+\n+ /* Exclude insns that do not load memory. */\n+ if (! register_operand (dest, dest_mode)\n+ || ! mem_operand (src = operands[1], src_mode))\n+ return false;\n+\n+ /* Exclude insns that do not perform memory loading with \"force_l32\". */\n+ if (MEM_ADDR_SPACE (src) != ADDR_SPACE_FORCE_L32)\n+ return false;\n+\n+ /* Addressing in the __force_l32 address space is only valid with a base\n+ register without offset. */\n+ addr = XEXP (src, 0);\n+ gcc_assert (REG_P (addr));\n+\n+ /* First, Load the aligned SImode memory containing the desired [HQ]Imode\n+ value. */\n+ emit_insn (gen_andsi3 (temp = gen_reg_rtx (Pmode),\n+\t\t\t addr, force_reg (SImode, GEN_INT (-4))));\n+ x = gen_rtx_MEM (SImode, temp);\n+ MEM_VOLATILE_P (x) = MEM_VOLATILE_P (src);\n+ emit_insn (gen_rtx_SET (temp, x));\n+\n+ /* Then, shift the bit-image of the desired [HQ]Imode value to bit-\n+ position 0, ie., the least significant side for little-endian, the\n+ most significant side for big-endian. */\n+ x = gen_rtx_ASHIFT (SImode, addr, GEN_INT (3));\n+ x = BITS_BIG_ENDIAN ? gen_rtx_ASHIFT (SImode, temp, x)\n+\t\t : gen_rtx_LSHIFTRT (SImode, temp, x);\n+ emit_insn (gen_rtx_SET (temp, x));\n+\n+ /* Finally, extract the necessary part from the shifted result. */\n+ x = extract_bit_field (temp, GET_MODE_BITSIZE (src_mode), 0, unsignedp,\n+\t\t\t NULL_RTX, dest_mode, dest_mode, false, NULL);\n+ emit_insn (gen_rtx_SET (dest, x));\n+\n+ return true;\n+}\n+\n+\n /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */\n \n static bool\n@@ -5506,6 +5580,68 @@ xtensa_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED,\n return NULL;\n }\n \n+/* Implement TARGET_ADDR_SPACE_SUBSET_P. */\n+\n+static bool\n+xtensa_addr_space_subset_p (addr_space_t subset, addr_space_t superset)\n+{\n+ /* Just obvious. */\n+ if (subset == superset)\n+ return true;\n+\n+ /* A __force_l32 pointer can point to any location in the generic\n+ address space, though its efficiency is another matter. */\n+ if (superset == ADDR_SPACE_FORCE_L32 && subset == ADDR_SPACE_GENERIC)\n+ return true;\n+\n+ return false;\n+}\n+\n+/* Implement TARGET_ADDR_SPACE_CONVERT. */\n+\n+static rtx\n+xtensa_addr_space_convert (rtx op, tree from_type, tree to_type)\n+{\n+ addr_space_t from_as = TYPE_ADDR_SPACE (TREE_TYPE (from_type));\n+ addr_space_t to_as = TYPE_ADDR_SPACE (TREE_TYPE (to_type));\n+\n+ /* A __force_l32 pointer can point to any location in the generic\n+ address space, though its efficiency is another matter. */\n+ if (to_as == ADDR_SPACE_FORCE_L32 && from_as == ADDR_SPACE_GENERIC)\n+ ;\n+ /* However, the reverse conversion carries risks. */\n+ else if (to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_FORCE_L32)\n+ warning (0, \"converting from the %<__force_l32%> address space to the \"\n+\t\t\"generic one is generally not safe\");\n+ /* Unimplemented conversions are of course not supported. */\n+ else\n+ error (\"conversion between those address spaces is not supported\");\n+\n+ return op;\n+}\n+\n+/* Implement TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P. */\n+\n+static bool\n+xtensa_addr_space_legitimate_address_p (machine_mode mode, rtx addr,\n+\t\t\t\t\tbool strict, addr_space_t as,\n+\t\t\t\t\tcode_helper ch)\n+{\n+ switch (as)\n+ {\n+ case ADDR_SPACE_FORCE_L32:\n+ /* The __force_l32 address space. */\n+\n+ while (SUBREG_P (addr))\n+\taddr = SUBREG_REG (addr);\n+\n+ /* Only valid with a base register without offset. */\n+ return REG_P (addr) && BASE_REG_P (addr, strict);\n+ }\n+\n+ return xtensa_legitimate_address_p (mode, addr, strict, ch);\n+}\n+\n /* Machine-specific pass in order to replace all assignments of large\n integer constants (i.e., that do not fit into the immediate field which\n can hold signed 12 bits) with other legitimate forms, specifically,\ndiff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h\nindex f8a4c3a209b..1072b7042f2 100644\n--- a/gcc/config/xtensa/xtensa.h\n+++ b/gcc/config/xtensa/xtensa.h\n@@ -327,6 +327,13 @@ along with GCC; see the file COPYING3. If not see\n call an address kept in a register. */\n #define NO_FUNCTION_CSE 1\n \n+/* Named address spaces. */\n+#define ADDR_SPACE_FORCE_L32 1\n+#define REGISTER_TARGET_PRAGMAS()\t\t\t\t\t\\\n+ do {\t\t\t\t\t\t\t\t\t\\\n+ c_register_addr_space (\"__force_l32\", ADDR_SPACE_FORCE_L32);\t\\\n+ } while (0)\n+\n /* Xtensa processors have \"register windows\". GCC does not currently\n take advantage of the possibility for variable-sized windows; instead,\n we use a fixed window size of 8. */\ndiff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md\nindex a96ea6feb60..89c536f1b24 100644\n--- a/gcc/config/xtensa/xtensa.md\n+++ b/gcc/config/xtensa/xtensa.md\n@@ -919,7 +919,19 @@\n \f\n ;; Zero-extend instructions.\n \n-(define_insn \"zero_extend<mode>si2\"\n+(define_expand \"zero_extend<mode>si2\"\n+ [(set (match_operand:SI 0 \"register_operand\")\n+\t(zero_extend:SI (match_operand:HQI 1 \"nonimmed_operand\")))]\n+ \"\"\n+{\n+ if (xtensa_expand_load_force_l32 (operands, SImode, <MODE>mode, true))\n+ ;\n+ else\n+ emit_insn (gen_zero_extend<mode>si2_internal (operands[0], operands[1]));\n+ DONE;\n+})\n+\n+(define_insn \"zero_extend<mode>si2_internal\"\n [(set (match_operand:SI 0 \"register_operand\")\n \t(zero_extend:SI (match_operand:HQI 1 \"nonimmed_operand\")))]\n \"\"\n@@ -937,7 +949,9 @@\n \t(sign_extend:SI (match_operand:HI 1 \"register_operand\" \"\")))]\n \"\"\n {\n- if (sext_operand (operands[1], HImode))\n+ if (xtensa_expand_load_force_l32 (operands, SImode, HImode, false))\n+ ;\n+ else if (sext_operand (operands[1], HImode))\n emit_insn (gen_extendhisi2_internal (operands[0], operands[1]));\n else\n xtensa_extend_reg (operands[0], operands[1]);\n@@ -959,7 +973,9 @@\n \t(sign_extend:SI (match_operand:QI 1 \"register_operand\" \"\")))]\n \"\"\n {\n- if (TARGET_SEXT)\n+ if (xtensa_expand_load_force_l32 (operands, SImode, QImode, false))\n+ ;\n+ else if (TARGET_SEXT)\n emit_insn (gen_extendqisi2_internal (operands[0], operands[1]));\n else\n xtensa_extend_reg (operands[0], operands[1]);\n@@ -1302,6 +1318,8 @@\n \t(match_operand:HI 1 \"general_operand\" \"\"))]\n \"\"\n {\n+ if (xtensa_expand_load_force_l32 (operands, HImode, HImode, true))\n+ DONE;\n if (xtensa_emit_move_sequence (operands, HImode))\n DONE;\n })\n@@ -1331,6 +1349,8 @@\n \t(match_operand:QI 1 \"general_operand\" \"\"))]\n \"\"\n {\n+ if (xtensa_expand_load_force_l32 (operands, QImode, QImode, true))\n+ DONE;\n if (xtensa_emit_move_sequence (operands, QImode))\n DONE;\n })\n", "prefixes": [ "1/4" ] }