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{ "id": 2227638, "url": "http://patchwork.ozlabs.org/api/patches/2227638/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/61595351-9b50-430c-8191-12de55588d45@yahoo.co.jp/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<61595351-9b50-430c-8191-12de55588d45@yahoo.co.jp>", "list_archive_url": null, "date": "2026-04-24T03:04:01", "name": "[2/4] xtensa: Implement \"force_l32\" target-specific attribute", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fc0a8ec3bec8b573ab4e521cad41c8f61a671cdb", "submitter": { "id": 83997, "url": "http://patchwork.ozlabs.org/api/people/83997/?format=api", "name": "Takayuki 'January June' Suwa", "email": "jjsuwa_sys3175@yahoo.co.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/61595351-9b50-430c-8191-12de55588d45@yahoo.co.jp/mbox/", "series": [ { "id": 501290, "url": "http://patchwork.ozlabs.org/api/series/501290/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501290", "date": "2026-04-24T03:07:46", "name": "[1/4] xtensa: Implement \"__force_l32\" named address space", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501290/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227638/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227638/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=yahoo.co.jp header.i=@yahoo.co.jp header.a=rsa-sha256\n header.s=yahoocojp-202506 header.b=X5HBN/2+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1776999841;\n s=yahoocojp-202506; d=yahoo.co.jp;\n h=References:Content-Transfer-Encoding:Content-Type:Subject:From:Cc:To:MIME-Version:Date:Message-ID;\n bh=S/ZB6IgLtW1XXQCfsu/YND0cz2+b5BF5ZWCt6/gS0Y0=;\n b=X5HBN/2+YmkCiimG7OtvL3YgR7NmbMUq5IhxEmBhKjBGlS5nr7pOt5s1X1UMqblJ\n TQcrS8j/XysLLnfhtAqPms9K6873MQtzCyC1ulIQora9fDuXGY+egbwl7D7EbaSPdX8\n 4fc9pgX5thSL3zq4GgiTxGdO7iA2YY4NEhaIOpuiEeJYZYnqSaLApQx4xwd/X5CBo7+\n VgwWRYitVP0Z6bQJ5PfiH3gJNHRND4BrEU+lzLGEyNvBRCN6HGjghA62SekFTeVr5LW\n xYoEcUYjT7Fi1Mc/SHNZeSt+CxNI2YsR8dHo9HjF49rOTpLVJ1lNWZZkZKT/Niftazg\n 1d9p3Mno7g==", "Message-ID": "<61595351-9b50-430c-8191-12de55588d45@yahoo.co.jp>", "Date": "Fri, 24 Apr 2026 12:04:01 +0900", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "To": "gcc-patches@gcc.gnu.org", "Cc": "Max Filippov <jcmvbkbc@gmail.com>", "From": "Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>", "Subject": "[PATCH 2/4] xtensa: Implement \"force_l32\" target-specific attribute", "Content-Type": "text/plain; charset=UTF-8; format=flowed", "Content-Transfer-Encoding": "7bit", "References": "<61595351-9b50-430c-8191-12de55588d45.ref@yahoo.co.jp>", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "The previous patch introduced the target-specific named address space\n\"__force_l32\", but this reserved identifier can only be used from C.\n\nTherefore, this patch introduces a new target-specific attribute\n\"force_l32,\" which is very similar to the named address space \"__force_l32,\"\nmaking that feature usable not only in C but also in other languages.\n\n /* example */\n extern \"C\" {\n unsigned int test(const char *p) {\n for (const char __attribute__((force_l32)) *q = p; ; ++q)\n if (!*q)\n return q - p;\n }\n }\n\n ;; result (-Os -mlittle-endian)\n test:\n \tentry\tsp, 32\n \tmov.n\ta8, a2\n \tmovi.n\ta10, -4\n .L3:\n \tand\ta9, a8, a10\t;; *q : align to SImode\n \tl32i.n\ta9, a9, 0\t;; *q : load:SI\n \tssa8l\ta8\t\t;; *q : shift to bit position 0\n \tsrl\ta9, a9\n \textui\ta9, a9, 0, 8\t:: *q : zero_extract:QI\n \tbeqz.n\ta9, .L5\n \taddi.n\ta8, a8, 1\n \tj\t.L3\n .L5:\n \tsub\ta2, a8, a2\n \tretw.n\n\ngcc/ChangeLog:\n\n\t* config/xtensa/xtensa.cc (xtensa_attribute_table,\n\tTARGET_ATTRIBUTE_TABLE):\n\tNew definitions for target-specific attributes.\n\t(xtensa_expand_load_force_l32_1): New sub-function for inspecting\n\tthe attribute from the specified MEM rtx.\n\t(xtensa_expand_load_force_l32): Add handlings for for addresses\n with offsets.\n\t(xtensa_handle_force_l32_attribute_1,\n\txtensa_handle_force_l32_attribute):\n\tNew functions for handling the attribute.\n---\n gcc/config/xtensa/xtensa.cc | 140 +++++++++++++++++++++++++++++++++---\n 1 file changed, 129 insertions(+), 11 deletions(-)", "diff": "diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc\nindex c3f7ebc7171..783cc6bbaf6 100644\n--- a/gcc/config/xtensa/xtensa.cc\n+++ b/gcc/config/xtensa/xtensa.cc\n@@ -206,6 +206,7 @@ static bool xtensa_addr_space_subset_p (addr_space_t, addr_space_t);\n static rtx xtensa_addr_space_convert (rtx, tree, tree);\n static bool xtensa_addr_space_legitimate_address_p (machine_mode, rtx, bool,\n \t\t\t\t\t\t addr_space_t, code_helper);\n+static tree xtensa_handle_force_l32_attribute (tree *, tree, tree, int, bool *);\n \n \f\n \n@@ -390,6 +391,17 @@ static bool xtensa_addr_space_legitimate_address_p (machine_mode, rtx, bool,\n #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P\t\\\n \txtensa_addr_space_legitimate_address_p\n \n+TARGET_GNU_ATTRIBUTES (xtensa_attribute_table,\n+{\n+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req,\n+ affects_type_identity, handler, exclude } */\n+ { \"force_l32\", 0, 0, true, false, false,\n+ false, xtensa_handle_force_l32_attribute, NULL }\n+});\n+\n+#undef TARGET_ATTRIBUTE_TABLE\n+#define TARGET_ATTRIBUTE_TABLE xtensa_attribute_table\n+\n struct gcc_target targetm = TARGET_INITIALIZER;\n \n \f\n@@ -2615,6 +2627,17 @@ xtensa_emit_add_imm (rtx dst, rtx src, HOST_WIDE_INT imm, rtx scratch,\n /* Expand a 1- or 2-byte width memory load into an aligned 4-byte width\n load with bit-extraction of the required bytes. */\n \n+static bool\n+xtensa_expand_load_force_l32_1 (rtx mem)\n+{\n+ tree type = TREE_TYPE (MEM_EXPR (mem));\n+\n+ /* If the \"force_l32\" attribute is found in the tree associated with\n+ mem RTX, return true. */\n+ return type && TREE_CODE (type) == INTEGER_TYPE\n+\t && lookup_attribute (\"force_l32\", TYPE_ATTRIBUTES (type));\n+}\n+\n bool\n xtensa_expand_load_force_l32 (rtx *operands, machine_mode dest_mode,\n \t\t\t machine_mode src_mode, int unsignedp)\n@@ -2623,13 +2646,20 @@ xtensa_expand_load_force_l32 (rtx *operands, machine_mode dest_mode,\n \n gcc_assert (src_mode == QImode || src_mode == HImode);\n \n- /* Reject sub-word store to memory within the __force_l32 address space. */\n- if (mem_operand (dest = operands[0], dest_mode)\n- && MEM_ADDR_SPACE (dest) == ADDR_SPACE_FORCE_L32)\n+ /* Reject sub-word store to memory with \"force_l32\". */\n+ if (mem_operand (dest = operands[0], dest_mode))\n {\n- error (\"Storing 1- and 2-byte quantities to memory within the \"\n-\t \"%<__force_l32%> address space is not supported\");\n- return false;\n+ if (MEM_ADDR_SPACE (dest) == ADDR_SPACE_FORCE_L32)\n+\t{\n+\t error (\"Storing 1- and 2-byte quantities to memory within the \"\n+\t\t \"%<__force_l32%> address space is not supported\");\n+\t return false;\n+\t}\n+ if (xtensa_expand_load_force_l32_1 (dest))\n+\twarning (OPT_Wattributes,\n+\t\t \"Storing 1- and 2-byte quantities to memory with the \"\n+\t\t \"%<force_l32%> attribute is not supported and the attribute \"\n+\t\t \"ignored\");\n }\n \n /* Exclude insns that do not load memory. */\n@@ -2638,13 +2668,31 @@ xtensa_expand_load_force_l32 (rtx *operands, machine_mode dest_mode,\n return false;\n \n /* Exclude insns that do not perform memory loading with \"force_l32\". */\n- if (MEM_ADDR_SPACE (src) != ADDR_SPACE_FORCE_L32)\n+ if (MEM_ADDR_SPACE (src) != ADDR_SPACE_FORCE_L32\n+ && ! xtensa_expand_load_force_l32_1 (src))\n return false;\n \n- /* Addressing in the __force_l32 address space is only valid with a base\n- register without offset. */\n- addr = XEXP (src, 0);\n- gcc_assert (REG_P (addr));\n+ /* As a preprocessing, handle cases where addr is (PLUS (REG, OFFSET))\n+ form. */\n+ if (REG_P (addr = XEXP (src, 0)))\n+ ;\n+ else if (GET_CODE (addr) == PLUS)\n+ {\n+ rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);\n+ HOST_WIDE_INT v;\n+\n+ if (! CONST_INT_P (op1))\n+\tstd::swap (op0, op1);\n+ if (! REG_P (op0) || ! CONST_INT_P (op1))\n+\treturn false;\n+ if ((v = INTVAL (op1)) == 0)\n+\taddr = op0;\n+ else\n+\txtensa_emit_add_imm (addr = gen_reg_rtx (Pmode),\n+\t\t\t op0, v, NULL_RTX, false);\n+ }\n+ else\n+ return false;\n \n /* First, Load the aligned SImode memory containing the desired [HQ]Imode\n value. */\n@@ -5642,6 +5690,76 @@ xtensa_addr_space_legitimate_address_p (machine_mode mode, rtx addr,\n return xtensa_legitimate_address_p (mode, addr, strict, ch);\n }\n \n+/* Implement machine-specific attribute \"force_l32\" handler. */\n+\n+static bool\n+xtensa_handle_force_l32_attribute_1 (tree *type)\n+{\n+ /* If the type has definitions for fields, then recursively process each\n+ of those types, and return true if any of the processes return true. */\n+ if (RECORD_OR_UNION_TYPE_P (*type))\n+ {\n+ bool f = false;\n+\n+ for (tree field = TYPE_FIELDS (*type);\n+\t field; field = DECL_CHAIN (field))\n+\tf |= xtensa_handle_force_l32_attribute_1 (&TREE_TYPE (field));\n+\n+ return f;\n+ }\n+\n+ /* If the type has an underlying type, it recursively processes that type\n+ and returns the result. */\n+ if (TREE_TYPE (*type))\n+ return xtensa_handle_force_l32_attribute_1 (&TREE_TYPE (*type));\n+\n+ /* If the type is INTEGER and its machine mode is [HQ]I, add the\n+ \"force_l32\" attribute to that type and return true. */\n+ if (TREE_CODE (*type) == INTEGER_TYPE\n+\t && (TYPE_MODE_RAW (*type) == QImode\n+\t || TYPE_MODE_RAW (*type) == HImode))\n+ {\n+ tree attrs = tree_cons (get_identifier (\"force_l32\"),\n+\t\t\t NULL, TYPE_ATTRIBUTES (*type));\n+\n+ *type = build_type_attribute_variant (*type, attrs);\n+\n+ return true;\n+ }\n+\n+ /* If none of the above apply, simply return false. */\n+ return false;\n+}\n+\n+static tree\n+xtensa_handle_force_l32_attribute (tree *node, tree name,\n+\t\t\t\t tree args ATTRIBUTE_UNUSED,\n+\t\t\t\t int flags ATTRIBUTE_UNUSED,\n+\t\t\t\t bool *no_add_attrs)\n+{\n+ if (DECL_P (*node))\n+ {\n+ if (TREE_CODE (*node) != TYPE_DECL && TREE_CODE (*node) != VAR_DECL\n+\t && TREE_CODE (*node) != PARM_DECL)\n+\t{\n+\t warning (OPT_Wattributes,\n+\t\t \"%qE attribute only applies to declarations of variables, \"\n+\t\t \"function parameters, or types\", name);\n+\t *no_add_attrs = true;\n+\t}\n+ /* Traverse all [HQ]Imode INTEGER types nested within the underlying\n+\t type of that declaration and attempt to apply the \"force_l32\"\n+\t attribute to them. */\n+ else if (! xtensa_handle_force_l32_attribute_1 (&TREE_TYPE (*node)))\n+\t{\n+\t warning (OPT_Wattributes, \"%qE attribute ignored\", name);\n+\t *no_add_attrs = true;\n+\t}\n+ }\n+\n+ return NULL_TREE;\n+}\n+\n /* Machine-specific pass in order to replace all assignments of large\n integer constants (i.e., that do not fit into the immediate field which\n can hold signed 12 bits) with other legitimate forms, specifically,\n", "prefixes": [ "2/4" ] }