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GET /api/patches/2227605/?format=api
{ "id": 2227605, "url": "http://patchwork.ozlabs.org/api/patches/2227605/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424023606.2556830-10-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424023606.2556830-10-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-24T02:36:06", "name": "[PULL,9/9] target/hexagon: Change DisasContext packet type", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "58a3bff7e038c63063933dd1c5b44a7262a6ef8c", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424023606.2556830-10-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 501280, "url": "http://patchwork.ozlabs.org/api/series/501280/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501280", "date": "2026-04-24T02:36:05", "name": "[PULL,1/9] Hexagon (target/hexagon) Properly handle Hexagon CPU version", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501280/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227605/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227605/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=QpSjck2b;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=aQBLCqPm;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-ORIG-GUID": "0vAjtC4CI8mIFDjZmBEBJyvRr4aOP8g1", "X-Authority-Analysis": "v=2.4 cv=QLhYgALL c=1 sm=1 tr=0 ts=69ead72a cx=c_pps\n a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22\n a=EUspDBNiAAAA:8 a=9JcS4vm5jFv34pll-oUA:9 a=QEXdDO2ut3YA:10\n a=vBUdepa8ALXHeOFLBtFW:22", "X-Proofpoint-GUID": "0vAjtC4CI8mIFDjZmBEBJyvRr4aOP8g1", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI0MDAyMCBTYWx0ZWRfX89/rAh1fDK5q\n qYQqihRBbQ75uoH14j6HvXS+dffm1FWFbXiu+KQjckEjGP9oRXGBvczQFQdfN3YyYhSS7TiYBLD\n sO+yQ+0Cu/b1E2yCbsmim4FydZCsPjEq4eylD/8Sl7a0fOK2gW5FsJZpJVkc4S1XN8PZ7hmTGcB\n ncjElatXIMZJ87COnrosyA92sL5GamNCA8l7ZlVOwny14cFSuMhnjPwriF8Z+2jEZqkmdVJjdGL\n 0q9vb8Za9ZTsWu/YHlkmJIJfhHEd4BxC+gtXUpLH0Ln/a9mSs2AzUG23GdSzTqeVvJzajFmeiwz\n gLlKXzDOi3x4Bfu1NLarVbod758PbWyOPdyq+g6qm12TaY4q3m3B31N0EKtNdE/UgcHiCxca/d8\n iPhHQ1AoFcVidhkIaVHAZ1r/S5rFMhi59Q+uKzbykf6H+tl+iO5lENyK1MOeAofLy0Igi9H/xCB\n S7a9PYX6E5bVn5arAHw==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0\n lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015\n priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604240020", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Marco Liebel <marco.liebel@oss.qualcomm.com>\n\nThe pkt variable inside DisasContext is of type Packet * and gets\nassigned to a local variable in decode_and_translate_packet. Right now\nthere seems to be no problem with it but future changes to e.g.\nhexagon_tr_transalte_packet are potentially dangerous if pkt is accessed\nafter the local variable goes out of scope.\n\nSince packets are being translated one at a time, the type of pkt can be\nchanged to just Packet to avoid risk of having a dangling pointer.\n\nSigned-off-by: Marco Liebel <marco.liebel@oss.qualcomm.com>\nReviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/gen_tcg.h | 2 +-\n target/hexagon/macros.h | 6 +-\n target/hexagon/translate.h | 2 +-\n target/hexagon/decode.c | 8 +--\n target/hexagon/genptr.c | 14 ++--\n target/hexagon/translate.c | 113 ++++++++++++++------------------\n target/hexagon/gen_tcg_funcs.py | 2 +-\n target/hexagon/hex_common.py | 4 +-\n 8 files changed, 66 insertions(+), 85 deletions(-)", "diff": "diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h\nindex 1e0cc3b29a8..0159e5c2d5f 100644\n--- a/target/hexagon/gen_tcg.h\n+++ b/target/hexagon/gen_tcg.h\n@@ -1343,7 +1343,7 @@\n #define fGEN_TCG_J2_trap0(SHORTCODE) \\\n do { \\\n uiV = uiV; \\\n- tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \\\n+ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt.pc); \\\n TCGv excp = tcg_constant_tl(HEX_EVENT_TRAP0); \\\n gen_helper_raise_exception(tcg_env, excp); \\\n } while (0)\ndiff --git a/target/hexagon/macros.h b/target/hexagon/macros.h\nindex 6c2862a2320..eebfe1e5ed9 100644\n--- a/target/hexagon/macros.h\n+++ b/target/hexagon/macros.h\n@@ -83,7 +83,7 @@\n */\n #define CHECK_NOSHUF(VA, SIZE) \\\n do { \\\n- if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \\\n+ if (insn->slot == 0 && ctx->pkt.pkt_has_scalar_store_s1) { \\\n probe_noshuf_load(VA, SIZE, ctx->mem_idx); \\\n process_store(ctx, 1); \\\n } \\\n@@ -94,11 +94,11 @@\n TCGLabel *noshuf_label = gen_new_label(); \\\n tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \\\n GET_EA; \\\n- if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \\\n+ if (insn->slot == 0 && ctx->pkt.pkt_has_scalar_store_s1) { \\\n probe_noshuf_load(EA, SIZE, ctx->mem_idx); \\\n } \\\n gen_set_label(noshuf_label); \\\n- if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \\\n+ if (insn->slot == 0 && ctx->pkt.pkt_has_scalar_store_s1) { \\\n process_store(ctx, 1); \\\n } \\\n } while (0)\ndiff --git a/target/hexagon/translate.h b/target/hexagon/translate.h\nindex 9cdcbd64164..1fc185e3edd 100644\n--- a/target/hexagon/translate.h\n+++ b/target/hexagon/translate.h\n@@ -28,7 +28,7 @@\n \n typedef struct DisasContext {\n DisasContextBase base;\n- Packet *pkt;\n+ Packet pkt;\n Insn *insn;\n const HexagonCPUDef *hex_def;\n uint32_t next_PC;\ndiff --git a/target/hexagon/decode.c b/target/hexagon/decode.c\nindex c4cf430e5a2..15954518b83 100644\n--- a/target/hexagon/decode.c\n+++ b/target/hexagon/decode.c\n@@ -834,15 +834,13 @@ int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,\n .hex_version = HEX_VER_ANY, /* Allow decode to accept anything */\n };\n DisasContext ctx;\n- Packet pkt;\n \n memset(&ctx, 0, sizeof(DisasContext));\n ctx.hex_def = &any_def;\n- ctx.pkt = &pkt;\n \n- if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) {\n- snprint_a_pkt_disas(buf, &pkt, words, pc, hex_def);\n- return pkt.encod_pkt_size_in_bytes;\n+ if (decode_packet(&ctx, nwords, words, &ctx.pkt, true) > 0) {\n+ snprint_a_pkt_disas(buf, &ctx.pkt, words, pc, hex_def);\n+ return ctx.pkt.encod_pkt_size_in_bytes;\n } else {\n for (int i = 0; i < nwords; i++) {\n g_string_append_printf(buf, \"0x\" TARGET_FMT_lx \"\\t\", words[i]);\ndiff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c\nindex c7b9436c8d4..5d5adace4b3 100644\n--- a/target/hexagon/genptr.c\n+++ b/target/hexagon/genptr.c\n@@ -382,7 +382,7 @@ static inline void gen_store_conditional8(DisasContext *ctx,\n static TCGv gen_slotval(DisasContext *ctx)\n {\n int slotval =\n- (ctx->pkt->pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);\n+ (ctx->pkt.pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);\n return tcg_constant_tl(slotval);\n }\n #endif\n@@ -458,7 +458,7 @@ static void gen_write_new_pc_addr(DisasContext *ctx, TCGv addr,\n tcg_gen_brcondi_tl(cond, pred, 1, pred_false);\n }\n \n- if (ctx->pkt->pkt_has_multi_cof) {\n+ if (ctx->pkt.pkt_has_multi_cof) {\n /* If there are multiple branches in a packet, ignore the second one */\n tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC],\n ctx->branch_taken, tcg_constant_tl(0),\n@@ -476,8 +476,8 @@ static void gen_write_new_pc_addr(DisasContext *ctx, TCGv addr,\n static void gen_write_new_pc_pcrel(DisasContext *ctx, int pc_off,\n TCGCond cond, TCGv pred)\n {\n- target_ulong dest = ctx->pkt->pc + pc_off;\n- if (ctx->pkt->pkt_has_multi_cof) {\n+ target_ulong dest = ctx->pkt.pc + pc_off;\n+ if (ctx->pkt.pkt_has_multi_cof) {\n gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred);\n } else {\n /* Defer this jump to the end of the TB */\n@@ -528,7 +528,7 @@ static inline void gen_loop0r(DisasContext *ctx, TCGv RsV, int riV)\n fIMMEXT(riV);\n fPCALIGN(riV);\n tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);\n- tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV);\n+ tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt.pc + riV);\n gen_set_usr_fieldi(ctx, USR_LPCFG, 0);\n }\n \n@@ -542,7 +542,7 @@ static inline void gen_loop1r(DisasContext *ctx, TCGv RsV, int riV)\n fIMMEXT(riV);\n fPCALIGN(riV);\n tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC1), RsV);\n- tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA1), ctx->pkt->pc + riV);\n+ tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA1), ctx->pkt.pc + riV);\n }\n \n static void gen_loop1i(DisasContext *ctx, int count, int riV)\n@@ -555,7 +555,7 @@ static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV)\n fIMMEXT(riV);\n fPCALIGN(riV);\n tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);\n- tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV);\n+ tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt.pc + riV);\n gen_set_usr_fieldi(ctx, USR_LPCFG, N);\n gen_pred_write(ctx, 3, tcg_constant_tl(0));\n }\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex 12c82fd6c5a..f26281e6711 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -156,8 +156,6 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,\n \n static void gen_end_tb(DisasContext *ctx)\n {\n- Packet *pkt = ctx->pkt;\n-\n gen_exec_counters(ctx);\n \n if (ctx->branch_cond != TCG_COND_NEVER) {\n@@ -171,7 +169,7 @@ static void gen_end_tb(DisasContext *ctx)\n gen_goto_tb(ctx, 0, ctx->branch_dest, true);\n }\n } else if (ctx->is_tight_loop &&\n- pkt->insn[pkt->num_insns - 1].opcode == J2_endloop0) {\n+ ctx->pkt.insn[ctx->pkt.num_insns - 1].opcode == J2_endloop0) {\n /*\n * When we're in a tight loop, we defer the endloop0 processing\n * to take advantage of direct block chaining\n@@ -266,11 +264,9 @@ static bool need_slot_cancelled(Packet *pkt)\n \n static bool need_next_PC(DisasContext *ctx)\n {\n- Packet *pkt = ctx->pkt;\n-\n /* Check for conditional control flow or HW loop end */\n- for (int i = 0; i < pkt->num_insns; i++) {\n- uint16_t opcode = pkt->insn[i].opcode;\n+ for (int i = 0; i < ctx->pkt.num_insns; i++) {\n+ uint16_t opcode = ctx->pkt.insn[i].opcode;\n if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) {\n return true;\n }\n@@ -353,8 +349,6 @@ static bool pkt_raises_exception(Packet *pkt)\n \n static bool need_commit(DisasContext *ctx)\n {\n- Packet *pkt = ctx->pkt;\n-\n /*\n * If the short-circuit property is set to false, we'll always do the commit\n */\n@@ -362,7 +356,7 @@ static bool need_commit(DisasContext *ctx)\n return true;\n }\n \n- if (pkt_raises_exception(pkt)) {\n+ if (pkt_raises_exception(&ctx->pkt)) {\n return true;\n }\n \n@@ -409,11 +403,10 @@ static void mark_implicit_writes(DisasContext *ctx)\n \n static void analyze_packet(DisasContext *ctx)\n {\n- Packet *pkt = ctx->pkt;\n ctx->read_after_write = false;\n ctx->has_hvx_overlap = false;\n- for (int i = 0; i < pkt->num_insns; i++) {\n- Insn *insn = &pkt->insn[i];\n+ for (int i = 0; i < ctx->pkt.num_insns; i++) {\n+ Insn *insn = &ctx->pkt.insn[i];\n ctx->insn = insn;\n if (opcode_analyze[insn->opcode]) {\n opcode_analyze[insn->opcode](ctx);\n@@ -425,8 +418,7 @@ static void analyze_packet(DisasContext *ctx)\n \n static void gen_start_packet(DisasContext *ctx)\n {\n- Packet *pkt = ctx->pkt;\n- target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes;\n+ target_ulong next_PC = ctx->base.pc_next + ctx->pkt.encod_pkt_size_in_bytes;\n int i;\n \n /* Clear out the disassembly context */\n@@ -468,13 +460,13 @@ static void gen_start_packet(DisasContext *ctx)\n bitmap_zero(ctx->pregs_written, NUM_PREGS);\n \n /* Initialize the runtime state for packet semantics */\n- if (need_slot_cancelled(pkt)) {\n+ if (need_slot_cancelled(&ctx->pkt)) {\n tcg_gen_movi_tl(hex_slot_cancelled, 0);\n }\n ctx->branch_taken = NULL;\n- if (pkt->pkt_has_cof) {\n+ if (ctx->pkt.pkt_has_cof) {\n ctx->branch_taken = tcg_temp_new();\n- if (pkt->pkt_has_multi_cof) {\n+ if (ctx->pkt.pkt_has_multi_cof) {\n tcg_gen_movi_tl(ctx->branch_taken, 0);\n }\n if (need_next_PC(ctx)) {\n@@ -503,7 +495,7 @@ static void gen_start_packet(DisasContext *ctx)\n * Preload the predicated pred registers into ctx->new_pred_value[pred_num]\n * Only endloop instructions conditionally write to pred registers\n */\n- if (ctx->need_commit && pkt->pkt_has_endloop) {\n+ if (ctx->need_commit && ctx->pkt.pkt_has_endloop) {\n for (i = 0; i < ctx->preg_log_idx; i++) {\n int pred_num = ctx->preg_log[i];\n ctx->new_pred_value[pred_num] = tcg_temp_new();\n@@ -542,13 +534,11 @@ static void gen_start_packet(DisasContext *ctx)\n \n bool is_gather_store_insn(DisasContext *ctx)\n {\n- Packet *pkt = ctx->pkt;\n- Insn *insn = ctx->insn;\n- if (GET_ATTRIB(insn->opcode, A_CVI_NEW) &&\n- insn->new_value_producer_slot == 1) {\n+ if (GET_ATTRIB(ctx->insn->opcode, A_CVI_NEW) &&\n+ ctx->insn->new_value_producer_slot == 1) {\n /* Look for gather instruction */\n- for (int i = 0; i < pkt->num_insns; i++) {\n- Insn *in = &pkt->insn[i];\n+ for (int i = 0; i < ctx->pkt.num_insns; i++) {\n+ Insn *in = &ctx->pkt.insn[i];\n if (GET_ATTRIB(in->opcode, A_CVI_GATHER) && in->slot == 1) {\n return true;\n }\n@@ -651,7 +641,7 @@ static bool slot_is_predicated(Packet *pkt, int slot_num)\n \n void process_store(DisasContext *ctx, int slot_num)\n {\n- bool is_predicated = slot_is_predicated(ctx->pkt, slot_num);\n+ bool is_predicated = slot_is_predicated(&ctx->pkt, slot_num);\n TCGLabel *label_end = NULL;\n \n /*\n@@ -728,13 +718,12 @@ static void process_store_log(DisasContext *ctx)\n * slot 1 and then slot 0. This will be important when\n * the memory accesses overlap.\n */\n- Packet *pkt = ctx->pkt;\n- if (pkt->pkt_has_scalar_store_s1) {\n- g_assert(!pkt->pkt_has_dczeroa);\n+ if (ctx->pkt.pkt_has_scalar_store_s1) {\n+ g_assert(!ctx->pkt.pkt_has_dczeroa);\n process_store(ctx, 1);\n }\n- if (pkt->pkt_has_scalar_store_s0) {\n- g_assert(!pkt->pkt_has_dczeroa);\n+ if (ctx->pkt.pkt_has_scalar_store_s0) {\n+ g_assert(!ctx->pkt.pkt_has_dczeroa);\n process_store(ctx, 0);\n }\n }\n@@ -742,7 +731,7 @@ static void process_store_log(DisasContext *ctx)\n /* Zero out a 32-bit cache line */\n static void process_dczeroa(DisasContext *ctx)\n {\n- if (ctx->pkt->pkt_has_dczeroa) {\n+ if (ctx->pkt.pkt_has_dczeroa) {\n /* Store 32 bytes of zero starting at (addr & ~0x1f) */\n TCGv addr = tcg_temp_new();\n TCGv_i64 zero = tcg_constant_i64(0);\n@@ -776,7 +765,7 @@ static void gen_commit_hvx(DisasContext *ctx)\n \n /* Early exit if not needed */\n if (!ctx->need_commit) {\n- g_assert(!pkt_has_hvx_store(ctx->pkt));\n+ g_assert(!pkt_has_hvx_store(&ctx->pkt));\n return;\n }\n \n@@ -810,25 +799,23 @@ static void gen_commit_hvx(DisasContext *ctx)\n tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);\n }\n \n- if (pkt_has_hvx_store(ctx->pkt)) {\n+ if (pkt_has_hvx_store(&ctx->pkt)) {\n gen_helper_commit_hvx_stores(tcg_env);\n }\n }\n \n static void update_exec_counters(DisasContext *ctx)\n {\n- Packet *pkt = ctx->pkt;\n- int num_insns = pkt->num_insns;\n int num_real_insns = 0;\n int num_hvx_insns = 0;\n \n- for (int i = 0; i < num_insns; i++) {\n- if (!pkt->insn[i].is_endloop &&\n- !pkt->insn[i].part1 &&\n- !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) {\n+ for (int i = 0; i < ctx->pkt.num_insns; i++) {\n+ if (!ctx->pkt.insn[i].is_endloop &&\n+ !ctx->pkt.insn[i].part1 &&\n+ !GET_ATTRIB(ctx->pkt.insn[i].opcode, A_IT_NOP)) {\n num_real_insns++;\n }\n- if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) {\n+ if (GET_ATTRIB(ctx->pkt.insn[i].opcode, A_CVI)) {\n num_hvx_insns++;\n }\n }\n@@ -857,12 +844,11 @@ static void gen_commit_packet(DisasContext *ctx)\n * store. Therefore, we call process_store_log before anything else\n * involved in committing the packet.\n */\n- Packet *pkt = ctx->pkt;\n- bool has_store_s0 = pkt->pkt_has_scalar_store_s0;\n+ bool has_store_s0 = ctx->pkt.pkt_has_scalar_store_s0;\n bool has_store_s1 =\n- (pkt->pkt_has_scalar_store_s1 && !ctx->s1_store_processed);\n- bool has_hvx_store = pkt_has_hvx_store(pkt);\n- if (pkt->pkt_has_dczeroa) {\n+ (ctx->pkt.pkt_has_scalar_store_s1 && !ctx->s1_store_processed);\n+ bool has_hvx_store = pkt_has_hvx_store(&ctx->pkt);\n+ if (ctx->pkt.pkt_has_dczeroa) {\n /*\n * The dczeroa will be the store in slot 0, check that we don't have\n * a store in slot 1 or an HVX store.\n@@ -889,12 +875,11 @@ static void gen_commit_packet(DisasContext *ctx)\n FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,\n HAS_HVX_STORES, 1);\n }\n- if (has_store_s0 && slot_is_predicated(pkt, 0)) {\n- mask =\n- FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,\n- S0_IS_PRED, 1);\n+ if (has_store_s0 && slot_is_predicated(&ctx->pkt, 0)) {\n+ mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED,\n+ 1);\n }\n- if (has_store_s1 && slot_is_predicated(pkt, 1)) {\n+ if (has_store_s1 && slot_is_predicated(&ctx->pkt, 1)) {\n mask =\n FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,\n S1_IS_PRED, 1);\n@@ -912,7 +897,7 @@ static void gen_commit_packet(DisasContext *ctx)\n int args = 0;\n args =\n FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, ctx->mem_idx);\n- if (slot_is_predicated(pkt, 0)) {\n+ if (slot_is_predicated(&ctx->pkt, 0)) {\n args =\n FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1);\n }\n@@ -924,18 +909,18 @@ static void gen_commit_packet(DisasContext *ctx)\n \n gen_reg_writes(ctx);\n gen_pred_writes(ctx);\n- if (pkt->pkt_has_hvx) {\n+ if (ctx->pkt.pkt_has_hvx) {\n gen_commit_hvx(ctx);\n }\n update_exec_counters(ctx);\n \n- if (pkt->vhist_insn != NULL) {\n+ if (ctx->pkt.vhist_insn != NULL) {\n ctx->pre_commit = false;\n- ctx->insn = pkt->vhist_insn;\n- pkt->vhist_insn->generate(ctx);\n+ ctx->insn = ctx->pkt.vhist_insn;\n+ ctx->pkt.vhist_insn->generate(ctx);\n }\n \n- if (pkt->pkt_has_cof) {\n+ if (ctx->pkt.pkt_has_cof) {\n gen_end_tb(ctx);\n }\n }\n@@ -944,7 +929,6 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)\n {\n uint32_t words[PACKET_WORDS_MAX];\n int nwords, words_read;\n- Packet pkt;\n int i;\n \n nwords = read_packet_words(env, ctx, words);\n@@ -953,22 +937,21 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)\n return;\n }\n \n- ctx->pkt = &pkt;\n- words_read = decode_packet(ctx, nwords, words, &pkt, false);\n+ words_read = decode_packet(ctx, nwords, words, &ctx->pkt, false);\n if (words_read > 0) {\n- pkt.pc = ctx->base.pc_next;\n- if (pkt.pkt_has_write_conflict) {\n+ ctx->pkt.pc = ctx->base.pc_next;\n+ if (ctx->pkt.pkt_has_write_conflict) {\n gen_exception_decode_fail(ctx, words_read,\n HEX_CAUSE_REG_WRITE_CONFLICT);\n return;\n }\n gen_start_packet(ctx);\n- for (i = 0; i < pkt.num_insns; i++) {\n- ctx->insn = &pkt.insn[i];\n+ for (i = 0; i < ctx->pkt.num_insns; i++) {\n+ ctx->insn = &ctx->pkt.insn[i];\n gen_insn(ctx);\n }\n gen_commit_packet(ctx);\n- ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;\n+ ctx->base.pc_next += ctx->pkt.encod_pkt_size_in_bytes;\n } else {\n gen_exception_decode_fail(ctx, nwords, HEX_CAUSE_INVALID_PACKET);\n }\ndiff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py\nindex 87b7f10d7fd..e7f90a0da11 100755\n--- a/target/hexagon/gen_tcg_funcs.py\n+++ b/target/hexagon/gen_tcg_funcs.py\n@@ -72,7 +72,7 @@ def gen_tcg_func(f, tag, regs, imms):\n for immlett, bits, immshift in imms:\n declared.append(hex_common.imm_name(immlett))\n \n- arguments = \", \".join([\"ctx\", \"ctx->insn\", \"ctx->pkt\"] + declared)\n+ arguments = \", \".join([\"ctx\", \"ctx->insn\", \"&ctx->pkt\"] + declared)\n f.write(f\" emit_{tag}({arguments});\\n\")\n \n elif hex_common.skip_qemu_helper(tag):\ndiff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\nindex c0e9f26aebe..e37d5a514f0 100755\n--- a/target/hexagon/hex_common.py\n+++ b/target/hexagon/hex_common.py\n@@ -1144,7 +1144,7 @@ def helper_args(tag, regs, imms):\n if need_pkt_has_multi_cof(tag):\n args.append(HelperArg(\n \"i32\",\n- \"tcg_constant_tl(ctx->pkt->pkt_has_multi_cof)\",\n+ \"tcg_constant_tl(ctx->pkt.pkt_has_multi_cof)\",\n \"uint32_t pkt_has_multi_cof\"\n ))\n if need_pkt_need_commit(tag):\n@@ -1156,7 +1156,7 @@ def helper_args(tag, regs, imms):\n if need_PC(tag):\n args.append(HelperArg(\n \"i32\",\n- \"tcg_constant_tl(ctx->pkt->pc)\",\n+ \"tcg_constant_tl(ctx->pkt.pc)\",\n \"target_ulong PC\"\n ))\n if need_next_PC(tag):\n", "prefixes": [ "PULL", "9/9" ] }