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GET /api/patches/2227583/?format=api
{ "id": 2227583, "url": "http://patchwork.ozlabs.org/api/patches/2227583/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/81c3b9a7-79fd-473a-880a-a40afa1e4a3e@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<81c3b9a7-79fd-473a-880a-a40afa1e4a3e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-24T00:58:25", "name": "[to-be-committed,RISC-V,V2] Improve subset of constant permutes for RISC-V", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1e322b81c65b5195a27cc68d3d6959a5cc24df36", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/81c3b9a7-79fd-473a-880a-a40afa1e4a3e@oss.qualcomm.com/mbox/", "series": [ { "id": 501269, "url": "http://patchwork.ozlabs.org/api/series/501269/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501269", "date": "2026-04-24T00:58:25", "name": "[to-be-committed,RISC-V,V2] Improve subset of constant permutes for RISC-V", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501269/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227583/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227583/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=negOgdGh;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Q7NSGZRd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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boundary=\"------------89jOg5i1cX0Bbp9oUcDXCiCu\"", "Message-ID": "<81c3b9a7-79fd-473a-880a-a40afa1e4a3e@oss.qualcomm.com>", "Date": "Thu, 23 Apr 2026 18:58:25 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "Cc": "Raphael Zinsly <rzinsly@qti.qualcomm.com>", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "Subject": "[to-be-committed][RISC-V][V2] Improve subset of constant permutes for\n RISC-V", "X-Authority-Analysis": "v=2.4 cv=Iocutr/g c=1 sm=1 tr=0 ts=69eac035 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=5XUFF1XORqm8zt8BrSAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=fHmpazp0yUBa7iD6960A:9 a=B2y7HmGcmWMA:10 a=scEy_gLbYbu1JhEsrz4S:22", "X-Proofpoint-ORIG-GUID": "umffXIu7bzCMkhrxmnLOQ80vsdOmgrXj", "X-Proofpoint-GUID": "umffXIu7bzCMkhrxmnLOQ80vsdOmgrXj", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI0MDAwNSBTYWx0ZWRfX6OX0HubMglsW\n 4GyijFYQRTw00Fh4+G/WCN08ZqaeR5U/o1PrClEbieJ0+B/JqZt+rNZNb0xvBRke0MUT1HjorDQ\n oA5rhWvir3GVbhvLFDJQMFpHzCYhHXfsdPdEHaJlc3SrIFVyDUEeudReoJZkkA6wZJYhNDKP4Qr\n VYxSufROvsbi4JKRlE8TbJm7e9dBRqPOELrofS7j3frGY0fZb+ZaiqpnD6SPLwIvDcXkgVp4mJ2\n NyoXlI2Q2YBix3BrI3heWfa6gBcr9gidwfNT/1QEVr0+mWlS2ICIc4AkqUeu8zn/JX1y1SH0NKh\n sM8E7ZRNclUY/lvOlbka6CfHSBEgwUJZ72pzPl++HQ61eNg4AmYLSj0sIEggnJbGuDi1UdrWdbn\n /7TYOoET33hjXLirIEBzUO4hXMsSPPIuYis52GHBoD+WE4a6Ho99ne3mbu7nmP6VadUgncKITgK\n 2AJXwORETLENwAy0fZg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0\n suspectscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015\n impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604240005", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "V2 of Raphael's patch that I posted on his behalf earlier today.\n\nThe pre-commit tester flagged one real issue and one non-issue. The \nnon-issue is the flags thing for ieee.exp that's currently getting \nsorted out.\n\nThe real issue it flagged was that the test failed to compile for rv32 \nbecause it has rv64 flags. We need to adjust the test to use the right \nset of flags for rv64 and rv32 respectively. That's the only change \nI've made relative to the patch from this morning. My tester didn't \nflag it because mine only looks for regressions. A failure in a new \ntest is ignored (though I've been thinking real hard about reverting \nthat behavior, at least for most targets).\n\nAnyway, new version attached and waiting on pre-commit CI to do its thing.\n\njeff\nThere's a set of constant permutes that are currently implemented\n via vslideup+vcompress which requires a mask (and setup of the\n mask), but which can be implemented via vslideup+vslidedown.\n\n This has been tested on riscv{32,64}-elf as well as in a BPI-F3 which\n is configured to use V by default.\n\n PR target/123839\n gcc/\n * config/riscv/riscv-v.cc (shuffle_slide_patterns): Use a\n vslideup+vslidedown pair rather than a vcompressed based\n sequence.\n\n gcc/testsuite\n * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Adjust\n expected output.\n * gcc.target/riscv/rvv/autovec/pr123839.c: New test.", "diff": "diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc\nindex 82313356a80..bc0a45f0ada 100644\n--- a/gcc/config/riscv/riscv-v.cc\n+++ b/gcc/config/riscv/riscv-v.cc\n@@ -3863,6 +3863,7 @@ shuffle_slide_patterns (struct expand_vec_perm_d *d)\n is the first element of OP0. */\n bool slideup = false;\n bool slidedown = false;\n+ bool need_slideup_p = false;\n \n /* For a slideup the permutation must start at OP0's first element. */\n if (known_eq (d->perm[0], 0))\n@@ -3872,8 +3873,21 @@ shuffle_slide_patterns (struct expand_vec_perm_d *d)\n if (known_eq (d->perm[vlen - 1], 2 * vlen - 1))\n slidedown = true;\n \n+ int slideup_cnt = 0;\n if (!slideup && !slidedown)\n- return false;\n+ {\n+ /* Check if the permutation starts with the end of OP0 followed by the\n+\t beginning of OP1. In this case we can do a slideup followed by a\n+\t slidedown. */\n+ slideup_cnt = vlen - (d->perm[vlen - 1].to_constant () % vlen) - 1;\n+ if (known_eq (d->perm[slideup_cnt], vlen) && known_eq (d->perm[slideup_cnt - 1], vlen - 1))\n+\t{\n+\t slidedown = true;\n+\t need_slideup_p = true;\n+\t}\n+ else\n+\treturn false;\n+ }\n \n /* Check for a monotonic sequence with one or two pivots. */\n int pivot = -1;\n@@ -3939,8 +3953,17 @@ shuffle_slide_patterns (struct expand_vec_perm_d *d)\n }\n else\n {\n+ rtx op1 = d->op1;\n+ if (need_slideup_p)\n+\t{\n+\t op1 = gen_reg_rtx (vmode);\n+\t rtx ops[] = {op1, d->op1, gen_int_mode (slideup_cnt, Pmode)};\n+\t insn_code icode = code_for_pred_slide (UNSPEC_VSLIDEUP, vmode);\n+\t emit_vlmax_insn (icode, BINARY_OP, ops);\n+\t}\n+\n len = pivot;\n- rtx ops[] = {d->target, d->op1, d->op0,\n+ rtx ops[] = {d->target, op1, d->op0,\n \t\t gen_int_mode (slide_cnt, Pmode)};\n icode = code_for_pred_slide (UNSPEC_VSLIDEDOWN, vmode);\n emit_nonvlmax_insn (icode, BINARY_OP_TUMA, ops,\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c\nindex 98e53b38f09..de86e904f93 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c\n@@ -11,12 +11,11 @@ struct s sss[MAX];\n /*\n ** build_linked_list:\n ** ...\n-** vsetivli\\s+zero,\\s*8,\\s*e64,\\s*m1,\\s*tu,\\s*ma\n+** vslideup\\.vi\\s+v[0-9]+,\\s*v[0-9]+,\\s*1\n ** ...\n-** vcompress\\.vm\\s+v[0-9]+,\\s*v[0-9]+,\\s*v0\n+** vslidedown\\.vi\\s+v[0-9]+,\\s*v[0-9]+,\\s*7\n ** ...\n-** vcompress\\.vm\\s+v[0-9]+,\\s*v[0-9]+,\\s*v0\n-** vsetivli\\s+zero,\\s*2,\\s*e64,\\s*m1,\\s*ta,\\s*ma\n+** vslidedown\\.vi\\s+v[0-9]+,\\s*v[0-9]+,\\s*7\n ** ...\n */\n void\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123839.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123839.c\nnew file mode 100644\nindex 00000000000..9abb4e33fee\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123839.c\n@@ -0,0 +1,15 @@\n+/* { dg-do compile { target { ! riscv_abi_e } } } */\n+/* { dg-options \"-O3 -march=rv64gcv -mrvv-max-lmul=m8 -Wno-overflow -mabi=lp64d\" { target { rv64 } } } */\n+/* { dg-options \"-O3 -march=rv32gcv -mrvv-max-lmul=m8 -Wno-overflow -mabi=ilp32\" { target { rv32 } } } */\n+\n+typedef int vnx4i __attribute__ ((vector_size (16)));\n+\n+vnx4i\n+test (vnx4i x, vnx4i y)\n+{\n+ return __builtin_shufflevector (x, y, 2, 3, 4, 5);\n+}\n+\n+/* { dg-final { scan-assembler-times \"vslideup\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vslidedown\" 1 } } */\n+/* { dg-final { scan-assembler-not \"vcompress\" } } */\n", "prefixes": [ "to-be-committed", "RISC-V", "V2" ] }