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GET /api/patches/2227361/?format=api
{ "id": 2227361, "url": "http://patchwork.ozlabs.org/api/patches/2227361/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-12-0296bccb9f4e@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423-glymur-v2-12-0296bccb9f4e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T13:29:41", "name": "[v2,12/13] media: iris: Add platform data for glymur", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "844e3d0ca714426ff95d80fcb9284e24126e280a", "submitter": { "id": 93161, "url": "http://patchwork.ozlabs.org/api/people/93161/?format=api", "name": "Vishnu Reddy", "email": "busanna.reddy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-12-0296bccb9f4e@oss.qualcomm.com/mbox/", "series": [ { "id": 501197, "url": "http://patchwork.ozlabs.org/api/series/501197/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197", "date": "2026-04-23T13:29:29", "name": "media: iris: Add support for glymur platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501197/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227361/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227361/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13929-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=PX2EyF/Y;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=cWT9vl9U;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260423-glymur-v2-12-0296bccb9f4e@oss.qualcomm.com>", "References": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "In-Reply-To": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "To": "Bryan O'Donoghue <bod@kernel.org>,\n Vikash Garodia <vikash.garodia@oss.qualcomm.com>,\n Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,\n Abhinav Kumar <abhinav.kumar@linux.dev>,\n Mauro Carvalho Chehab <mchehab@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joerg Roedel <joro@8bytes.org>,\n Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Stefan Schmidt <stefan.schmidt@linaro.org>,\n Hans Verkuil <hverkuil@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n \"Rafael J. Wysocki\" <rafael@kernel.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Thierry Reding <thierry.reding@kernel.org>,\n Mikko Perttunen <mperttunen@nvidia.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Jonathan Hunter <jonathanh@nvidia.com>", "Cc": "linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy <busanna.reddy@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776950985; l=11396;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=IpKGagBtaKo+T7hDhMwWB/G/phGQIlwytr+yRoflFcc=;\n b=RAxNFsn0oM6btTQpSMOyV1izkkgutjTgKTb69aqE5Vl1IUWaWYuLOYk88Otl6AC7tCRH2jkMR\n L6e/GWPYk83AEBqzXuidea632kn+l4rO4kL5DxAZBG+nodY+3tVSZd1", "X-Developer-Key": "i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=", "X-Proofpoint-ORIG-GUID": "NbdCGxPn05Sop3JjQcpfv6fc9Zlnayfi", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfXx20L3/z7kV0A\n /hImpqgojv1pJQOVHBcImcNGns6QRDs1THhu4TDR3x75rncLnmH8SmZTArKPa7mm0XheZSyCNsZ\n M7rjdNHcwJiSep+ZNSb1tWQRyqf2qdMSpP6ShnPWZYQ5iM3yi9b9qFoIq8k6vi+DP84j1CwLt9F\n 0ReWxgRgPJb2CpDBEDsvk0Mkml6lc9T3Y90LYFDXcrMoxwXTtJjg09R0jH5DjAOXKH9KRquUPQ2\n Gsz9/SDe9n9vGDbqP96lp60nXVM9i/F6XqOcrW2HwadoNMuZBCiK/ASXw8i8csaxSwv7Twr4ft+\n dkHmivfhSGEhd2wtswDblIQ5azIIQOs3MiENgEaS4xLHzzxS+lU1YklowHiHtlqSx3sRBaSGLlf\n yU2YS30lhluKY8CHNb904Bq1fzYjwy9/JYjB3ABfCAgZFT6CHeF3IWWnB8dcs0XcVDpiritc2mQ\n nZvMETfYIHwRkxOIzjw==", "X-Authority-Analysis": "v=2.4 cv=AvbeGu9P c=1 sm=1 tr=0 ts=69ea1f44 cx=c_pps\n a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22\n a=EUspDBNiAAAA:8 a=syK4oCsQgbaUnHKzOKsA:9 a=QEXdDO2ut3YA:10\n a=uG9DUKGECoFWVXl0Dc02:22", "X-Proofpoint-GUID": "NbdCGxPn05Sop3JjQcpfv6fc9Zlnayfi", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0\n lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0\n adultscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604230134" }, "content": "Add glymur platform data by reusing most of the SM8550 definitions.\nMove configuration that differs in a per-SoC platform specific data.\n\nSigned-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n---\n drivers/media/platform/qcom/iris/Makefile | 1 +\n .../platform/qcom/iris/iris_platform_common.h | 5 ++\n .../media/platform/qcom/iris/iris_platform_gen2.c | 99 ++++++++++++++++++++++\n .../platform/qcom/iris/iris_platform_glymur.c | 97 +++++++++++++++++++++\n .../platform/qcom/iris/iris_platform_glymur.h | 17 ++++\n drivers/media/platform/qcom/iris/iris_probe.c | 4 +\n 6 files changed, 223 insertions(+)", "diff": "diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile\nindex 2abbd3aeb4af..2a50f3cafc38 100644\n--- a/drivers/media/platform/qcom/iris/Makefile\n+++ b/drivers/media/platform/qcom/iris/Makefile\n@@ -11,6 +11,7 @@ qcom-iris-objs += iris_buffer.o \\\n iris_hfi_gen2_response.o \\\n iris_hfi_queue.o \\\n iris_platform_gen2.o \\\n+ iris_platform_glymur.o \\\n iris_power.o \\\n iris_probe.o \\\n iris_resources.o \\\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h\nindex 502d7099085c..2003b7186480 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_common.h\n+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h\n@@ -30,6 +30,10 @@ struct iris_inst;\n #define DEFAULT_QP\t\t\t\t20\n #define BITRATE_DEFAULT\t\t\t20000000\n \n+#define VIDEO_REGION_SECURE_FW_REGION_ID\t0\n+#define VIDEO_REGION_VM0_SECURE_NP_ID\t\t1\n+#define VIDEO_REGION_VM0_NONSECURE_NP_ID\t5\n+\n enum stage_type {\n \tSTAGE_1 = 1,\n \tSTAGE_2 = 2,\n@@ -41,6 +45,7 @@ enum pipe_type {\n \tPIPE_4 = 4,\n };\n \n+extern const struct iris_platform_data glymur_data;\n extern const struct iris_platform_data qcs8300_data;\n extern const struct iris_platform_data sc7280_data;\n extern const struct iris_platform_data sm8250_data;\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c\nindex 5862c89a4971..d11c9d1ce6b1 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c\n+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c\n@@ -12,6 +12,7 @@\n #include \"iris_vpu_buffer.h\"\n #include \"iris_vpu_common.h\"\n \n+#include \"iris_platform_glymur.h\"\n #include \"iris_platform_qcs8300.h\"\n #include \"iris_platform_sm8650.h\"\n #include \"iris_platform_sm8750.h\"\n@@ -931,6 +932,104 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {\n \tBUF_SCRATCH_2,\n };\n \n+const struct iris_platform_data glymur_data = {\n+\t.get_instance = iris_hfi_gen2_get_instance,\n+\t.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,\n+\t.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,\n+\t.get_vpu_buffer_size = iris_vpu_buf_size,\n+\t.vpu_ops = &iris_vpu36_ops,\n+\t.set_preset_registers = iris_set_sm8550_preset_registers,\n+\t.init_cb_devs = iris_glymur_init_cb_devs,\n+\t.deinit_cb_devs = iris_glymur_deinit_cb_devs,\n+\t.icc_tbl = sm8550_icc_table,\n+\t.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),\n+\t.clk_rst_tbl = iris_glymur_clk_reset_table,\n+\t.clk_rst_tbl_size = ARRAY_SIZE(iris_glymur_clk_reset_table),\n+\t.bw_tbl_dec = sm8550_bw_table_dec,\n+\t.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),\n+\t.pmdomain_tbl = &iris_glymur_pmdomain_table,\n+\t.opp_pd_tbl = sm8550_opp_pd_table,\n+\t.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),\n+\t.clk_tbl = iris_glymur_clk_table,\n+\t.clk_tbl_size = ARRAY_SIZE(iris_glymur_clk_table),\n+\t.opp_clk_tbl = iris_glymur_opp_clk_table,\n+\t/* Upper bound of DMA address range */\n+\t.dma_mask = 0xffe00000 - 1,\n+\t.fwname = \"qcom/vpu/vpu36_p4_s7.mbn\",\n+\t.pas_id = IRIS_PAS_ID,\n+\t.dual_core = true,\n+\t.inst_iris_fmts = platform_fmts_sm8550_dec,\n+\t.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),\n+\t.inst_caps = &platform_inst_cap_sm8550,\n+\t.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,\n+\t.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),\n+\t.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,\n+\t.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),\n+\t.tz_cp_config_data = iris_glymur_tz_cp_config,\n+\t.tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config),\n+\t.core_arch = VIDEO_ARCH_LX,\n+\t.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,\n+\t.ubwc_config = &ubwc_config_sm8550,\n+\t.num_vpp_pipe = 4,\n+\t.max_session_count = 16,\n+\t.max_core_mbpf = NUM_MBS_8K * 2,\n+\t.max_core_mbps = ((8192 * 4320) / 256) * 60,\n+\t.dec_input_config_params_default =\n+\t\tsm8550_vdec_input_config_params_default,\n+\t.dec_input_config_params_default_size =\n+\t\tARRAY_SIZE(sm8550_vdec_input_config_params_default),\n+\t.dec_input_config_params_hevc =\n+\t\tsm8550_vdec_input_config_param_hevc,\n+\t.dec_input_config_params_hevc_size =\n+\t\tARRAY_SIZE(sm8550_vdec_input_config_param_hevc),\n+\t.dec_input_config_params_vp9 =\n+\t\tsm8550_vdec_input_config_param_vp9,\n+\t.dec_input_config_params_vp9_size =\n+\t\tARRAY_SIZE(sm8550_vdec_input_config_param_vp9),\n+\t.dec_input_config_params_av1 =\n+\t\tsm8550_vdec_input_config_param_av1,\n+\t.dec_input_config_params_av1_size =\n+\t\tARRAY_SIZE(sm8550_vdec_input_config_param_av1),\n+\t.dec_output_config_params =\n+\t\tsm8550_vdec_output_config_params,\n+\t.dec_output_config_params_size =\n+\t\tARRAY_SIZE(sm8550_vdec_output_config_params),\n+\n+\t.enc_input_config_params =\n+\t\tsm8550_venc_input_config_params,\n+\t.enc_input_config_params_size =\n+\t\tARRAY_SIZE(sm8550_venc_input_config_params),\n+\t.enc_output_config_params =\n+\t\tsm8550_venc_output_config_params,\n+\t.enc_output_config_params_size =\n+\t\tARRAY_SIZE(sm8550_venc_output_config_params),\n+\n+\t.dec_input_prop = sm8550_vdec_subscribe_input_properties,\n+\t.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),\n+\t.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,\n+\t.dec_output_prop_avc_size =\n+\t\tARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),\n+\t.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,\n+\t.dec_output_prop_hevc_size =\n+\t\tARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),\n+\t.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,\n+\t.dec_output_prop_vp9_size =\n+\t\tARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),\n+\t.dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,\n+\t.dec_output_prop_av1_size =\n+\t\tARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),\n+\n+\t.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,\n+\t.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),\n+\t.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,\n+\t.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),\n+\n+\t.enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,\n+\t.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),\n+\t.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,\n+\t.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),\n+};\n+\n const struct iris_platform_data sm8550_data = {\n \t.get_instance = iris_hfi_gen2_get_instance,\n \t.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c\nnew file mode 100644\nindex 000000000000..59fa752916a4\n--- /dev/null\n+++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c\n@@ -0,0 +1,97 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+#include <dt-bindings/media/qcom,glymur-iris.h>\n+#include <linux/dma_context_bus.h>\n+#include \"iris_core.h\"\n+#include \"iris_platform_common.h\"\n+#include \"iris_platform_glymur.h\"\n+\n+const struct platform_clk_data iris_glymur_clk_table[] = {\n+\t{IRIS_AXI_VCODEC_CLK,\t\t\"iface\"\t\t\t},\n+\t{IRIS_CTRL_CLK,\t\t\t\"core\"\t\t\t},\n+\t{IRIS_VCODEC_CLK,\t\t\"vcodec0_core\"\t\t},\n+\t{IRIS_AXI_CTRL_CLK,\t\t\"iface1\"\t\t},\n+\t{IRIS_CTRL_FREERUN_CLK,\t\t\"core_freerun\"\t\t},\n+\t{IRIS_VCODEC_FREERUN_CLK,\t\"vcodec0_core_freerun\"\t},\n+\t{IRIS_AXI_VCODEC1_CLK,\t\t\"iface2\"\t\t},\n+\t{IRIS_VCODEC1_CLK,\t\t\"vcodec1_core\"\t\t},\n+\t{IRIS_VCODEC1_FREERUN_CLK,\t\"vcodec1_core_freerun\"\t},\n+};\n+\n+const char * const iris_glymur_clk_reset_table[] = {\n+\t\"bus0\",\n+\t\"bus1\",\n+\t\"core\",\n+\t\"vcodec0_core\",\n+\t\"bus2\",\n+\t\"vcodec1_core\",\n+};\n+\n+const char * const iris_glymur_opp_clk_table[] = {\n+\t\"vcodec0_core\",\n+\t\"vcodec1_core\",\n+\t\"core\",\n+\tNULL,\n+};\n+\n+const struct platform_pd_data iris_glymur_pmdomain_table = {\n+\t.pd_types = (enum platform_pm_domain_type []) {\n+\t\tIRIS_CTRL_POWER_DOMAIN,\n+\t\tIRIS_VCODEC_POWER_DOMAIN,\n+\t\tIRIS_VCODEC1_POWER_DOMAIN,\n+\t},\n+\t.pd_names = (const char *[]) {\n+\t\t\"venus\",\n+\t\t\"vcodec0\",\n+\t\t\"vcodec1\",\n+\t},\n+\t.pd_count = 3,\n+};\n+\n+const struct tz_cp_config iris_glymur_tz_cp_config[] = {\n+\t{\n+\t\t.cp_start = VIDEO_REGION_SECURE_FW_REGION_ID,\n+\t\t.cp_size = 0,\n+\t\t.cp_nonpixel_start = 0,\n+\t\t.cp_nonpixel_size = 0x1000000,\n+\t},\n+\t{\n+\t\t.cp_start = VIDEO_REGION_VM0_SECURE_NP_ID,\n+\t\t.cp_size = 0,\n+\t\t.cp_nonpixel_start = 0x1000000,\n+\t\t.cp_nonpixel_size = 0x24800000,\n+\t},\n+\t{\n+\t\t.cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID,\n+\t\t.cp_size = 0,\n+\t\t.cp_nonpixel_start = 0x25800000,\n+\t\t.cp_nonpixel_size = 0xda600000,\n+\t},\n+};\n+\n+int iris_glymur_init_cb_devs(struct iris_core *core)\n+{\n+\tu64 dma_mask = core->iris_platform_data->dma_mask;\n+\tconst u32 f_id = IOMMU_FID_IRIS_FIRMWARE;\n+\tstruct device *dev;\n+\n+\tdev = create_dma_context_bus_device(core->dev, NULL, dma_mask, &f_id);\n+\tif (IS_ERR(dev))\n+\t\treturn PTR_ERR(dev);\n+\n+\tif (device_iommu_mapped(dev))\n+\t\tcore->fw_dev = dev;\n+\telse\n+\t\tdevice_unregister(dev);\n+\n+\treturn 0;\n+}\n+\n+void iris_glymur_deinit_cb_devs(struct iris_core *core)\n+{\n+\tif (core->fw_dev)\n+\t\tdevice_unregister(core->fw_dev);\n+}\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h\nnew file mode 100644\nindex 000000000000..e0d07ccf658c\n--- /dev/null\n+++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+#ifndef __IRIS_PLATFORM_GLYMUR_H__\n+#define __IRIS_PLATFORM_GLYMUR_H__\n+\n+extern const struct platform_clk_data iris_glymur_clk_table[9];\n+extern const char * const iris_glymur_clk_reset_table[6];\n+extern const char * const iris_glymur_opp_clk_table[4];\n+extern const struct platform_pd_data iris_glymur_pmdomain_table;\n+extern const struct tz_cp_config iris_glymur_tz_cp_config[3];\n+int iris_glymur_init_cb_devs(struct iris_core *core);\n+void iris_glymur_deinit_cb_devs(struct iris_core *core);\n+\n+#endif /* __IRIS_PLATFORM_GLYMUR_H__ */\ndiff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c\nindex 34c981be9bc1..78e3627557e9 100644\n--- a/drivers/media/platform/qcom/iris/iris_probe.c\n+++ b/drivers/media/platform/qcom/iris/iris_probe.c\n@@ -369,6 +369,10 @@ static const struct dev_pm_ops iris_pm_ops = {\n };\n \n static const struct of_device_id iris_dt_match[] = {\n+\t{\n+\t\t.compatible = \"qcom,glymur-iris\",\n+\t\t.data = &glymur_data,\n+\t},\n \t{\n \t\t.compatible = \"qcom,qcs8300-iris\",\n \t\t.data = &qcs8300_data,\n", "prefixes": [ "v2", "12/13" ] }