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GET /api/patches/2227359/?format=api
{ "id": 2227359, "url": "http://patchwork.ozlabs.org/api/patches/2227359/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-13-0296bccb9f4e@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423-glymur-v2-13-0296bccb9f4e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T13:29:42", "name": "[v2,13/13] arm64: dts: qcom: glymur: Add iris video node", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c787567454e0a8e18a29a1738d2902b272d1bdc2", "submitter": { "id": 93161, "url": "http://patchwork.ozlabs.org/api/people/93161/?format=api", "name": "Vishnu Reddy", "email": "busanna.reddy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-13-0296bccb9f4e@oss.qualcomm.com/mbox/", "series": [ { "id": 501197, "url": "http://patchwork.ozlabs.org/api/series/501197/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197", "date": "2026-04-23T13:29:29", "name": "media: iris: Add support for glymur platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501197/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227359/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227359/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13930-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=hRV084kD;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=j419/WKG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260423-glymur-v2-13-0296bccb9f4e@oss.qualcomm.com>", "References": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "In-Reply-To": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "To": "Bryan O'Donoghue <bod@kernel.org>,\n Vikash Garodia <vikash.garodia@oss.qualcomm.com>,\n Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,\n Abhinav Kumar <abhinav.kumar@linux.dev>,\n Mauro Carvalho Chehab <mchehab@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joerg Roedel <joro@8bytes.org>,\n Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Stefan Schmidt <stefan.schmidt@linaro.org>,\n Hans Verkuil <hverkuil@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n \"Rafael J. Wysocki\" <rafael@kernel.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Thierry Reding <thierry.reding@kernel.org>,\n Mikko Perttunen <mperttunen@nvidia.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Jonathan Hunter <jonathanh@nvidia.com>", "Cc": "linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy <busanna.reddy@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776950985; l=5015;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=AXNNMUqpUBkT37jqrWXRRraxt0+yVQz0nuc5i48FDy0=;\n b=58IIjTBkuro7ooQIqHd8rr+cIx2L6Qfg+MBWKSjyofmOnqBfOWoWDP6sWuTHFW4fv3rgaFy25\n 7AjrheiHUn0AtDglqLzBB1eaCIXV8cS+5nxXGa6iHZFn8/zeMMRA7d1", "X-Developer-Key": "i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=", "X-Proofpoint-ORIG-GUID": "OXkk3gE5UFFyFGQys9m2h3XCSBBp9HVl", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfX2Wr5/mKjBuOk\n KRrDPh584+Et/kPdLdg48mcgoAq5AqygVg/RWU5RJ4pnEfopxMc80+fRBJrEACjA5awsSGP2jPc\n F988dUlQv/uewaCfWeSFmvXAncCGH438x6jIDZl9DMw8GSYHDoojM50sWC3xFQHqW5rEFKPlnG3\n e+QtR010VlMeLGxDjL/UGAt21Hz4PTOtpBtHA2sY1Tp6Wrkn7O0TIzeXM0gOFgZ0CwjE5MTvTSD\n H6XOWY2Mhm56iuGPKVvtw7mBOjiiYnaoaMB4FCVLKip7QI29V6DoFU9xiqU28roHkdsNBFGyOin\n dXbovCsJWzZtvi0UF5ikaE52LxrAx+a4D0MkRaTDgrXJAhaW592j8+unfX0X/qFZVdilFGjhg9b\n ax3tcROxAk4qG1IpBfQiK/YpOyBIArILoyHXLNeLskt1tRUpUQ4KGuDzTzzI8Bea7jOuiElOVL+\n YCF38QtTavF5mGF0GwQ==", "X-Authority-Analysis": "v=2.4 cv=AvbeGu9P c=1 sm=1 tr=0 ts=69ea1f4e cx=c_pps\n a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22\n a=EUspDBNiAAAA:8 a=VYrRtalYO0MCCBblpesA:9 a=QEXdDO2ut3YA:10\n a=GvdueXVYPmCkWapjIL-Q:22", "X-Proofpoint-GUID": "OXkk3gE5UFFyFGQys9m2h3XCSBBp9HVl", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0\n lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0\n adultscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604230134" }, "content": "Add iris video codec to glymur SoC, which comes with significantly\ndifferent powering up sequence than previous platforms, thus different\nclocks and resets.\n\nSigned-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n---\n arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 ++\n arch/arm64/boot/dts/qcom/glymur.dtsi | 118 ++++++++++++++++++++++++++++++++\n 2 files changed, 122 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts\nindex 35aaf09e4e2b..cbc9856956ff 100644\n--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts\n+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts\n@@ -255,6 +255,10 @@ &mdss_dp3_phy {\n \tstatus = \"okay\";\n };\n \n+&iris {\n+\tstatus = \"okay\";\n+};\n+\n &pmh0110_f_e0_gpios {\n \tmisc_3p3_reg_en: misc-3p3-reg-en-state {\n \t\tpins = \"gpio6\";\ndiff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi\nindex f23cf81ddb77..c47443174f97 100644\n--- a/arch/arm64/boot/dts/qcom/glymur.dtsi\n+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi\n@@ -13,6 +13,7 @@\n #include <dt-bindings/interconnect/qcom,glymur-rpmh.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n #include <dt-bindings/mailbox/qcom-ipcc.h>\n+#include <dt-bindings/media/qcom,glymur-iris.h>\n #include <dt-bindings/phy/phy-qcom-qmp.h>\n #include <dt-bindings/power/qcom,rpmhpd.h>\n #include <dt-bindings/power/qcom-rpmpd.h>\n@@ -4163,6 +4164,123 @@ usb_mp: usb@a400000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tiris: video-codec@aa00000 {\n+\t\t\tcompatible = \"qcom,glymur-iris\";\n+\t\t\treg = <0x0 0xaa00000 0x0 0xf0000>;\n+\n+\t\t\tclocks = <&gcc GCC_VIDEO_AXI0_CLK>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS0C_CLK>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS0_CLK>,\n+\t\t\t\t <&gcc GCC_VIDEO_AXI0C_CLK>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS0_FREERUN_CLK>,\n+\t\t\t\t <&gcc GCC_VIDEO_AXI1_CLK>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS1_CLK>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS1_FREERUN_CLK>;\n+\t\t\tclock-names = \"iface\",\n+\t\t\t\t \"core\",\n+\t\t\t\t \"vcodec0_core\",\n+\t\t\t\t \"iface1\",\n+\t\t\t\t \"core_freerun\",\n+\t\t\t\t \"vcodec0_core_freerun\",\n+\t\t\t\t \"iface2\",\n+\t\t\t\t \"vcodec1_core\",\n+\t\t\t\t \"vcodec1_core_freerun\";\n+\n+\t\t\tdma-coherent;\n+\n+\t\t\tinterconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY\n+\t\t\t\t\t &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,\n+\t\t\t\t\t<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS\n+\t\t\t\t\t &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;\n+\t\t\tinterconnect-names = \"cpu-cfg\",\n+\t\t\t\t\t \"video-mem\";\n+\n+\t\t\tinterrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\t\tiommus = <&apps_smmu 0x1940 0x0>,\n+\t\t\t\t <&apps_smmu 0x1943 0x0>,\n+\t\t\t\t <&apps_smmu 0x1944 0x0>,\n+\t\t\t\t <&apps_smmu 0x19e0 0x0>;\n+\n+\t\t\tiommu-map = <IOMMU_FID_IRIS_FIRMWARE &apps_smmu 0x19e2 0x1>;\n+\n+\t\t\tmemory-region = <&video_mem>;\n+\n+\t\t\toperating-points-v2 = <&iris_opp_table>;\n+\n+\t\t\tpower-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,\n+\t\t\t\t\t<&videocc VIDEO_CC_MVS0_GDSC>,\n+\t\t\t\t\t<&rpmhpd RPMHPD_MXC>,\n+\t\t\t\t\t<&rpmhpd RPMHPD_MMCX>,\n+\t\t\t\t\t<&videocc VIDEO_CC_MVS1_GDSC>;\n+\t\t\tpower-domain-names = \"venus\",\n+\t\t\t\t\t \"vcodec0\",\n+\t\t\t\t\t \"mxc\",\n+\t\t\t\t\t \"mmcx\",\n+\t\t\t\t\t \"vcodec1\";\n+\n+\t\t\tresets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,\n+\t\t\t\t <&gcc GCC_VIDEO_AXI0C_CLK_ARES>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>,\n+\t\t\t\t <&gcc GCC_VIDEO_AXI1_CLK_ARES>,\n+\t\t\t\t <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>;\n+\t\t\treset-names = \"bus0\",\n+\t\t\t\t \"bus1\",\n+\t\t\t\t \"core\",\n+\t\t\t\t \"vcodec0_core\",\n+\t\t\t\t \"bus2\",\n+\t\t\t\t \"vcodec1_core\";\n+\n+\t\t\t/*\n+\t\t\t * IRIS firmware is signed by vendors, only\n+\t\t\t * enable on boards where the proper signed firmware\n+\t\t\t * is available.\n+\t\t\t */\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tiris_opp_table: opp-table {\n+\t\t\t\tcompatible = \"operating-points-v2\";\n+\n+\t\t\t\topp-240000000 {\n+\t\t\t\t\topp-hz = /bits/ 64 <240000000 240000000 360000000>;\n+\t\t\t\t\trequired-opps = <&rpmhpd_opp_svs>,\n+\t\t\t\t\t\t\t<&rpmhpd_opp_low_svs>;\n+\t\t\t\t};\n+\n+\t\t\t\topp-338000000 {\n+\t\t\t\t\topp-hz = /bits/ 64 <338000000 338000000 507000000>;\n+\t\t\t\t\trequired-opps = <&rpmhpd_opp_svs>,\n+\t\t\t\t\t\t\t<&rpmhpd_opp_svs>;\n+\t\t\t\t};\n+\n+\t\t\t\topp-366000000 {\n+\t\t\t\t\topp-hz = /bits/ 64 <366000000 366000000 549000000>;\n+\t\t\t\t\trequired-opps = <&rpmhpd_opp_svs_l1>,\n+\t\t\t\t\t\t\t<&rpmhpd_opp_svs_l1>;\n+\t\t\t\t};\n+\n+\t\t\t\topp-444000000 {\n+\t\t\t\t\topp-hz = /bits/ 64 <444000000 444000000 666000000>;\n+\t\t\t\t\trequired-opps = <&rpmhpd_opp_svs_l1>,\n+\t\t\t\t\t\t\t<&rpmhpd_opp_nom>;\n+\t\t\t\t};\n+\n+\t\t\t\topp-533333334 {\n+\t\t\t\t\topp-hz = /bits/ 64 <533333334 533333334 800000000>;\n+\t\t\t\t\trequired-opps = <&rpmhpd_opp_svs_l1>,\n+\t\t\t\t\t\t\t<&rpmhpd_opp_turbo>;\n+\t\t\t\t};\n+\n+\t\t\t\topp-655000000 {\n+\t\t\t\t\topp-hz = /bits/ 64 <655000000 655000000 982000000>;\n+\t\t\t\t\trequired-opps = <&rpmhpd_opp_nom>,\n+\t\t\t\t\t\t\t<&rpmhpd_opp_turbo_l1>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n \t\tmdss: display-subsystem@ae00000 {\n \t\t\tcompatible = \"qcom,glymur-mdss\";\n \t\t\treg = <0x0 0x0ae00000 0x0 0x1000>;\n", "prefixes": [ "v2", "13/13" ] }