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GET /api/patches/2227358/?format=api
{ "id": 2227358, "url": "http://patchwork.ozlabs.org/api/patches/2227358/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-9-0296bccb9f4e@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423-glymur-v2-9-0296bccb9f4e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T13:29:38", "name": "[v2,09/13] media: iris: Add power sequence for Glymur", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f7e10be556d2e0542fcdaac14f463cf0bff292b2", "submitter": { "id": 93161, "url": "http://patchwork.ozlabs.org/api/people/93161/?format=api", "name": "Vishnu Reddy", "email": "busanna.reddy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-9-0296bccb9f4e@oss.qualcomm.com/mbox/", "series": [ { "id": 501197, "url": "http://patchwork.ozlabs.org/api/series/501197/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197", "date": "2026-04-23T13:29:29", "name": "media: iris: Add support for glymur platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501197/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227358/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227358/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13926-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=OEV6R9wW;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=abDw+TcZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260423-glymur-v2-9-0296bccb9f4e@oss.qualcomm.com>", "References": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "In-Reply-To": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "To": "Bryan O'Donoghue <bod@kernel.org>,\n Vikash Garodia <vikash.garodia@oss.qualcomm.com>,\n Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,\n Abhinav Kumar <abhinav.kumar@linux.dev>,\n Mauro Carvalho Chehab <mchehab@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joerg Roedel <joro@8bytes.org>,\n Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Stefan Schmidt <stefan.schmidt@linaro.org>,\n Hans Verkuil <hverkuil@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n \"Rafael J. Wysocki\" <rafael@kernel.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Thierry Reding <thierry.reding@kernel.org>,\n Mikko Perttunen <mperttunen@nvidia.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Jonathan Hunter <jonathanh@nvidia.com>", "Cc": "linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy <busanna.reddy@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776950985; l=8487;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=LCMjOJtIxtHep2v0soQ3sUv2MXiTZMrsIoi3l55k2cY=;\n b=7X/KgTns18PVEGW+JrZHBV69wODcTX7hJ2smtGg1g7f1oG/DnqCmvhadmTbY/a4SUjPS/a2+w\n 69rqAkfhfBwCWSwyuhuGWmWYYSCS7QeYMV5zBevR560DXNeInl5+Klh", "X-Developer-Key": "i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=", "X-Authority-Analysis": "v=2.4 cv=f4Z4wuyM c=1 sm=1 tr=0 ts=69ea1f28 cx=c_pps\n a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22\n a=EUspDBNiAAAA:8 a=Js87xDwMZ--NYW6i2EgA:9 a=QEXdDO2ut3YA:10\n a=1OuFwYUASf3TG4hYMiVC:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfX+8Kg1HPuYvrA\n z34Bsjb3m6sTsMcyUxoF+ejompsn2piG2lx34tnFQXjR9yc+zVEBqS1QEUG3ZJjnv/8Q3vb203T\n csv4BVZeHFFT/3C9fNP1jkltAynkdoypp1uPYnSLI8fIqBd5guJR4QCxw3Ug4C0Dzn1MwsvmKF2\n BxB7b7xUsGt3ZAEIOf5dyvFga3QqvThqESTkrhl+Emxh80kdOAwjpdh1NH0kcko0KaHRytXBYA6\n nbGS2wVs0zY2zUpCN89YDccw0wRMIaxJeyj7VdFAYHRKMIz8UfybAE03lUuaJBj5fFvYtOnKADp\n 09rhWTR6vKauHKfRnDR11c/KGHIVx9CnQwSTFV7BHSsmHQIYwmJKO3nem5MtGp9mirL6g70z5Mp\n l1TDExf0Ij4lZtMn/j1EiofBHGvjS/K0J/3VgJlgfcHoSDNAxTe3qf2eK0oHZ0DwUjimbDPoIQk\n V6zBknF3TftSppJjNmw==", "X-Proofpoint-GUID": "22zQ3ZhED6uX4D7Vi-HFjwW8uUnUJXNx", "X-Proofpoint-ORIG-GUID": "22zQ3ZhED6uX4D7Vi-HFjwW8uUnUJXNx", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 clxscore=1015\n spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230134" }, "content": "Glymur has a secondary video codec core (vcodec1), equivalent to the\nprimary core (vcodec0), but with independent power domains, clocks,\nand reset lines. Reuse the existing code wherever possible and add\npower sequence for vcodec1.\n\nSigned-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n---\n .../platform/qcom/iris/iris_platform_common.h | 4 +\n drivers/media/platform/qcom/iris/iris_vpu3x.c | 122 +++++++++++++++++++++\n drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +\n .../platform/qcom/iris/iris_vpu_register_defines.h | 7 ++\n 4 files changed, 134 insertions(+)", "diff": "diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h\nindex 7d59e6364e9d..8995136ad29e 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_common.h\n+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h\n@@ -61,6 +61,9 @@ enum platform_clk_type {\n \tIRIS_VPP0_HW_CLK,\n \tIRIS_VPP1_HW_CLK,\n \tIRIS_APV_HW_CLK,\n+\tIRIS_AXI_VCODEC1_CLK,\n+\tIRIS_VCODEC1_CLK,\n+\tIRIS_VCODEC1_FREERUN_CLK,\n };\n \n struct platform_clk_data {\n@@ -210,6 +213,7 @@ enum platform_pm_domain_type {\n \tIRIS_VPP0_HW_POWER_DOMAIN,\n \tIRIS_VPP1_HW_POWER_DOMAIN,\n \tIRIS_APV_HW_POWER_DOMAIN,\n+\tIRIS_VCODEC1_POWER_DOMAIN,\n };\n \n struct platform_pd_data {\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c\nindex a9f43dbfc695..bd70d1c0ea76 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c\n+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c\n@@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)\n \treturn pwr_status ? false : true;\n }\n \n+static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core)\n+{\n+\tu32 value, pwr_status;\n+\n+\tvalue = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS);\n+\tpwr_status = value & BIT(4);\n+\n+\treturn !pwr_status;\n+}\n+\n static void iris_vpu3_power_off_hardware(struct iris_core *core)\n {\n \tu32 reg_val = 0, value, i;\n@@ -260,6 +270,110 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)\n \tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n }\n \n+static int iris_vpu36_power_on_hw1(struct iris_core *core)\n+{\n+\tint ret;\n+\n+\tret = iris_enable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK);\n+\tif (ret)\n+\t\tgoto err_disable_hw1_power;\n+\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK);\n+\tif (ret)\n+\t\tgoto err_disable_axi1_clk;\n+\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK);\n+\tif (ret)\n+\t\tgoto err_disable_hw1_free_clk;\n+\n+\tret = iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, true);\n+\tif (ret)\n+\t\tgoto err_disable_hw1_clk;\n+\n+\treturn 0;\n+\n+err_disable_hw1_clk:\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK);\n+err_disable_hw1_free_clk:\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK);\n+err_disable_axi1_clk:\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK);\n+err_disable_hw1_power:\n+\tiris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN);\n+\n+\treturn ret;\n+}\n+\n+static int iris_vpu36_power_on_hw(struct iris_core *core)\n+{\n+\tint ret;\n+\n+\tret = iris_vpu35_power_on_hw(core);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = iris_vpu36_power_on_hw1(core);\n+\tif (ret)\n+\t\tgoto err_power_off_hw;\n+\n+\treturn 0;\n+\n+err_power_off_hw:\n+\tiris_vpu35_power_off_hw(core);\n+\n+\treturn ret;\n+}\n+\n+static void iris_vpu36_power_off_hw1(struct iris_core *core)\n+{\n+\tu32 value, i;\n+\tint ret;\n+\n+\tif (iris_vpu36_hw1_power_collapsed(core))\n+\t\tgoto disable_power;\n+\n+\tvalue = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);\n+\tif (value)\n+\t\twritel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);\n+\n+\tfor (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {\n+\t\tret = readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 * i,\n+\t\t\t\t\t value, value & DMA_NOC_IDLE, 2000, 20000);\n+\t\tif (ret)\n+\t\t\tgoto disable_power;\n+\t}\n+\n+\twritel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);\n+\tret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,\n+\t\t\t\t value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000);\n+\tif (ret)\n+\t\tgoto disable_power;\n+\n+\twritel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);\n+\n+\twritel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base +\n+\t CPU_CS_AHB_BRIDGE_SYNC_RESET);\n+\twritel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);\n+\twritel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);\n+\n+disable_power:\n+\tiris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, false);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK);\n+\tiris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN);\n+}\n+\n+static void iris_vpu36_power_off_hw(struct iris_core *core)\n+{\n+\tiris_vpu35_power_off_hw(core);\n+\tiris_vpu36_power_off_hw1(core);\n+}\n+\n const struct vpu_ops iris_vpu3_ops = {\n \t.power_off_hw = iris_vpu3_power_off_hardware,\n \t.power_on_hw = iris_vpu_power_on_hw,\n@@ -284,3 +398,11 @@ const struct vpu_ops iris_vpu35_ops = {\n \t.program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,\n \t.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,\n };\n+\n+const struct vpu_ops iris_vpu36_ops = {\n+\t.power_off_hw = iris_vpu36_power_off_hw,\n+\t.power_on_hw = iris_vpu36_power_on_hw,\n+\t.power_off_controller = iris_vpu35_vpu4x_power_off_controller,\n+\t.power_on_controller = iris_vpu35_vpu4x_power_on_controller,\n+\t.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,\n+};\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h\nindex f6dffc613b82..99e75fb4b10d 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h\n+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h\n@@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops;\n extern const struct vpu_ops iris_vpu3_ops;\n extern const struct vpu_ops iris_vpu33_ops;\n extern const struct vpu_ops iris_vpu35_ops;\n+extern const struct vpu_ops iris_vpu36_ops;\n extern const struct vpu_ops iris_vpu4x_ops;\n \n struct vpu_ops {\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h\nindex 72168b9ffa73..37f234484f1b 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h\n+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h\n@@ -7,6 +7,7 @@\n #define __IRIS_VPU_REGISTER_DEFINES_H__\n \n #define VCODEC_BASE_OFFS\t\t\t0x00000000\n+#define VCODEC1_BASE_OFFS\t\t\t0x00040000\n #define AON_MVP_NOC_RESET\t\t\t0x0001F000\n #define CPU_BASE_OFFS\t\t\t\t0x000A0000\n #define WRAPPER_BASE_OFFS\t\t\t0x000B0000\n@@ -14,6 +15,8 @@\n #define AON_BASE_OFFS\t\t\t\t0x000E0000\n \n #define VCODEC_SS_IDLE_STATUSN\t\t\t(VCODEC_BASE_OFFS + 0x70)\n+#define VCODEC1_SS_IDLE_STATUSN\t\t\t(VCODEC1_BASE_OFFS + 0x70)\n+#define DMA_NOC_IDLE\t\t\t\tBIT(22)\n \n #define AON_WRAPPER_MVP_NOC_RESET_REQ\t\t(AON_MVP_NOC_RESET + 0x000)\n #define VIDEO_NOC_RESET_REQ\t\t\t(BIT(0) | BIT(1))\n@@ -35,6 +38,8 @@\n #define CPU_CS_AHB_BRIDGE_SYNC_RESET\t\t(CPU_CS_BASE_OFFS + 0x160)\n #define CORE_BRIDGE_SW_RESET\t\t\tBIT(0)\n #define CORE_BRIDGE_HW_RESET_DISABLE\t\tBIT(1)\n+#define VCODEC1_BRIDGE_SW_RESET\t\t\tBIT(2)\n+#define VCODEC1_BRIDGE_HW_RESET_DISABLE\t\tBIT(3)\n \n #define CPU_CS_X2RPMH\t\t\t\t(CPU_CS_BASE_OFFS + 0x168)\n #define MSK_SIGNAL_FROM_TENSILICA\t\tBIT(0)\n@@ -52,11 +57,13 @@\n #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS\t\t(WRAPPER_BASE_OFFS + 0x58)\n #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL\t(WRAPPER_BASE_OFFS + 0x5C)\n #define REQ_POWER_DOWN_PREP\t\t\tBIT(0)\n+#define REQ_VCODEC1_POWER_DOWN_PREP\t\tBIT(1)\n \n #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS\t\t(WRAPPER_BASE_OFFS + 0x60)\n #define NOC_LPI_STATUS_DONE\t\t\tBIT(0) /* Indicates the NOC handshake is complete */\n #define NOC_LPI_STATUS_DENY\t\t\tBIT(1) /* Indicates the NOC handshake is denied */\n #define NOC_LPI_STATUS_ACTIVE\t\t\tBIT(2) /* Indicates the NOC is active */\n+#define NOC_LPI_VCODEC1_STATUS_DONE\t\tBIT(8)\n \n #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0\t(WRAPPER_BASE_OFFS + 0x78)\n #define WRAPPER_CORE_POWER_STATUS\t\t(WRAPPER_BASE_OFFS + 0x80)\n", "prefixes": [ "v2", "09/13" ] }