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GET /api/patches/2227354/?format=api
{ "id": 2227354, "url": "http://patchwork.ozlabs.org/api/patches/2227354/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-4-0296bccb9f4e@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423-glymur-v2-4-0296bccb9f4e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T13:29:33", "name": "[v2,04/13] dt-bindings: media: qcom,glymur-iris: Add glymur video codec", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "26be4c82f15d136e0b0641d389dd7c8c249aa146", "submitter": { "id": 93161, "url": "http://patchwork.ozlabs.org/api/people/93161/?format=api", "name": "Vishnu Reddy", "email": "busanna.reddy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-4-0296bccb9f4e@oss.qualcomm.com/mbox/", "series": [ { "id": 501197, "url": "http://patchwork.ozlabs.org/api/series/501197/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197", "date": "2026-04-23T13:29:29", "name": "media: iris: Add support for glymur platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501197/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227354/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227354/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13921-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=WkLmNkn7;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=TGPc+hNb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260423-glymur-v2-4-0296bccb9f4e@oss.qualcomm.com>", "References": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "In-Reply-To": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "To": "Bryan O'Donoghue <bod@kernel.org>,\n Vikash Garodia <vikash.garodia@oss.qualcomm.com>,\n Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,\n Abhinav Kumar <abhinav.kumar@linux.dev>,\n Mauro Carvalho Chehab <mchehab@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joerg Roedel <joro@8bytes.org>,\n Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Stefan Schmidt <stefan.schmidt@linaro.org>,\n Hans Verkuil <hverkuil@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n \"Rafael J. Wysocki\" <rafael@kernel.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Thierry Reding <thierry.reding@kernel.org>,\n Mikko Perttunen <mperttunen@nvidia.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Jonathan Hunter <jonathanh@nvidia.com>", "Cc": "linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy <busanna.reddy@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776950985; l=7570;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=EqdrZDhwbeUXkKMJ4KC0f5Nf+jlPc2iG/3BjVoOnKh0=;\n b=DWWeTu5sHeIIPoCMxxKeKnUf2R7cu3pGbQ+jYfdVZkIXigbOi/ygY3cFzpTJKwEs98YuT397d\n 803RuZl0G89C1d1JcfrPcKhpHAcQX1cQd6AXFddmyDniHzZlnyXOdzi", "X-Developer-Key": "i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfX/M8IokTfsPYQ\n qFiamp/CiIm/kURvkeYglg3Iso/VvclALfhVUdzNl3oIf8DVki/n2LIbiBp15Cq8Aikw/hPr5oJ\n X0dSn5K9ZInqYTiMsY2TUp/wBh4lnQ/WwFsw6uXLwyMvj0fr1a4vh+vX3RMAM6nbNYeh6YywRiX\n n2uIYzo2Y3B2SNhofUzMVMT2SZ8opK6v83ESio6sKrU0E1P+vDp8TwfTlcJFpR8UFym0ohIbtbh\n 3tI90rZPfw9Zq5l5ACtBsPy7MvZSpon7YXJel5Ny7h7jjhVYyHk3TkPp8dEhJQNCMfI4MwXDBVP\n zGpO60z+xD+ESKQXJNisDvWnAeXjkrqnbufljefDxTyVGgmzRojS8ZDouY/HoN3z+xmZKzXMryK\n XdOed6nMfcvbSbxPDdubnlTIVa7g+dOZ9Fj0EWHuSW2pd23dB6qfckPpFaM8uuDqB4MR5oNn26f\n B7Vm3yEjjlakjGRNBVA==", "X-Proofpoint-ORIG-GUID": "kBn1PwxP3RAargtUr67DnDv4jh3T5a7A", "X-Proofpoint-GUID": "kBn1PwxP3RAargtUr67DnDv4jh3T5a7A", "X-Authority-Analysis": "v=2.4 cv=f5J4wuyM c=1 sm=1 tr=0 ts=69ea1efa cx=c_pps\n a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22\n a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=17OVpTNTOV0qq6DYWkQA:9 a=QEXdDO2ut3YA:10\n a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 malwarescore=0\n spamscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230134" }, "content": "Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur\nis a new generation of video IP that introduces a dual-core architecture.\nThe second core brings its own power domain, clocks, and reset lines,\nrequiring additional power domains and clocks in the power sequence.\n\nSigned-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n---\n .../bindings/media/qcom,glymur-iris.yaml | 220 +++++++++++++++++++++\n include/dt-bindings/media/qcom,glymur-iris.h | 11 ++\n 2 files changed, 231 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml\nnew file mode 100644\nindex 000000000000..0fd8a8db01af\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml\n@@ -0,0 +1,220 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Glymur SoC Iris video encoder and decoder\n+\n+maintainers:\n+ - Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n+\n+description:\n+ The Iris video processing unit on Qualcomm Glymur SoC is a video encode and\n+ decode accelerator.\n+\n+properties:\n+ compatible:\n+ const: qcom,glymur-iris\n+\n+ reg:\n+ maxItems: 1\n+\n+ clocks:\n+ maxItems: 9\n+\n+ clock-names:\n+ items:\n+ - const: iface\n+ - const: core\n+ - const: vcodec0_core\n+ - const: iface1\n+ - const: core_freerun\n+ - const: vcodec0_core_freerun\n+ - const: iface2\n+ - const: vcodec1_core\n+ - const: vcodec1_core_freerun\n+\n+ dma-coherent: true\n+\n+ firmware-name:\n+ maxItems: 1\n+\n+ interconnects:\n+ maxItems: 2\n+\n+ interconnect-names:\n+ items:\n+ - const: cpu-cfg\n+ - const: video-mem\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ iommus:\n+ maxItems: 4\n+\n+ iommu-map:\n+ maxItems: 1\n+\n+ memory-region:\n+ maxItems: 1\n+\n+ operating-points-v2: true\n+ opp-table:\n+ type: object\n+\n+ power-domains:\n+ maxItems: 5\n+\n+ power-domain-names:\n+ items:\n+ - const: venus\n+ - const: vcodec0\n+ - const: mxc\n+ - const: mmcx\n+ - const: vcodec1\n+\n+ resets:\n+ maxItems: 6\n+\n+ reset-names:\n+ items:\n+ - const: bus0\n+ - const: bus1\n+ - const: core\n+ - const: vcodec0_core\n+ - const: bus2\n+ - const: vcodec1_core\n+\n+required:\n+ - compatible\n+ - reg\n+ - clocks\n+ - clock-names\n+ - dma-coherent\n+ - interconnects\n+ - interconnect-names\n+ - interrupts\n+ - iommus\n+ - memory-region\n+ - power-domains\n+ - power-domain-names\n+ - resets\n+ - reset-names\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+ #include <dt-bindings/media/qcom,glymur-iris.h>\n+ #include <dt-bindings/power/qcom,rpmhpd.h>\n+\n+ video-codec@aa00000 {\n+ compatible = \"qcom,glymur-iris\";\n+ reg = <0x0aa00000 0xf0000>;\n+\n+ clocks = <&gcc_video_axi0_clk>,\n+ <&videocc_mvs0c_clk>,\n+ <&videocc_mvs0_clk>,\n+ <&gcc_video_axi0c_clk>,\n+ <&videocc_mvs0c_freerun_clk>,\n+ <&videocc_mvs0_freerun_clk>,\n+ <&gcc_video_axi1_clk>,\n+ <&videocc_mvs1_clk>,\n+ <&videocc_mvs1_freerun_clk>;\n+ clock-names = \"iface\",\n+ \"core\",\n+ \"vcodec0_core\",\n+ \"iface1\",\n+ \"core_freerun\",\n+ \"vcodec0_core_freerun\",\n+ \"iface2\",\n+ \"vcodec1_core\",\n+ \"vcodec1_core_freerun\";\n+\n+ dma-coherent;\n+\n+ interconnects = <&hsc_noc_master_appss_proc &config_noc_slave_venus_cfg>,\n+ <&mmss_noc_master_video &mc_virt_slave_ebi1>;\n+ interconnect-names = \"cpu-cfg\",\n+ \"video-mem\";\n+\n+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;\n+\n+ iommus = <&apps_smmu 0x1940 0x0>,\n+ <&apps_smmu 0x1943 0x0>,\n+ <&apps_smmu 0x1944 0x0>,\n+ <&apps_smmu 0x19e0 0x0>;\n+\n+ iommu-map = <IOMMU_FID_IRIS_FIRMWARE &apps_smmu 0x19e2 0x1>;\n+\n+ memory-region = <&video_mem>;\n+\n+ operating-points-v2 = <&iris_opp_table>;\n+\n+ power-domains = <&videocc_mvs0c_gdsc>,\n+ <&videocc_mvs0_gdsc>,\n+ <&rpmhpd RPMHPD_MXC>,\n+ <&rpmhpd RPMHPD_MMCX>,\n+ <&videocc_mvs1_gdsc>;\n+ power-domain-names = \"venus\",\n+ \"vcodec0\",\n+ \"mxc\",\n+ \"mmcx\",\n+ \"vcodec1\";\n+\n+ resets = <&gcc_video_axi0_clk_ares>,\n+ <&gcc_video_axi0c_clk_ares>,\n+ <&videocc_mvs0c_freerun_clk_ares>,\n+ <&videocc_mvs0_freerun_clk_ares>,\n+ <&gcc_video_axi1_clk_ares>,\n+ <&videocc_mvs1_freerun_clk_ares>;\n+ reset-names = \"bus0\",\n+ \"bus1\",\n+ \"core\",\n+ \"vcodec0_core\",\n+ \"bus2\",\n+ \"vcodec1_core\";\n+\n+ iris_opp_table: opp-table {\n+ compatible = \"operating-points-v2\";\n+\n+ opp-240000000 {\n+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;\n+ required-opps = <&rpmhpd_opp_svs>,\n+ <&rpmhpd_opp_low_svs>;\n+ };\n+\n+ opp-338000000 {\n+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;\n+ required-opps = <&rpmhpd_opp_svs>,\n+ <&rpmhpd_opp_svs>;\n+ };\n+\n+ opp-366000000 {\n+ opp-hz = /bits/ 64 <366000000 366000000 549000000>;\n+ required-opps = <&rpmhpd_opp_svs_l1>,\n+ <&rpmhpd_opp_svs_l1>;\n+ };\n+\n+ opp-444000000 {\n+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;\n+ required-opps = <&rpmhpd_opp_svs_l1>,\n+ <&rpmhpd_opp_nom>;\n+ };\n+\n+ opp-533333334 {\n+ opp-hz = /bits/ 64 <533333334 533333334 800000000>;\n+ required-opps = <&rpmhpd_opp_svs_l1>,\n+ <&rpmhpd_opp_turbo>;\n+ };\n+\n+ opp-655000000 {\n+ opp-hz = /bits/ 64 <655000000 655000000 982000000>;\n+ required-opps = <&rpmhpd_opp_nom>,\n+ <&rpmhpd_opp_turbo_l1>;\n+ };\n+ };\n+ };\ndiff --git a/include/dt-bindings/media/qcom,glymur-iris.h b/include/dt-bindings/media/qcom,glymur-iris.h\nnew file mode 100644\nindex 000000000000..dcaa2bc21db5\n--- /dev/null\n+++ b/include/dt-bindings/media/qcom,glymur-iris.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#ifndef _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_\n+#define _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_\n+\n+#define IOMMU_FID_IRIS_FIRMWARE\t0\n+\n+#endif\n", "prefixes": [ "v2", "04/13" ] }