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GET /api/patches/2227351/?format=api
{ "id": 2227351, "url": "http://patchwork.ozlabs.org/api/patches/2227351/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-8-0296bccb9f4e@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423-glymur-v2-8-0296bccb9f4e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T13:29:37", "name": "[v2,08/13] media: iris: Use power domain type to look up pd_devs index", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d2d34cbc719f4f79b8f812258f6555723e6a3469", "submitter": { "id": 93161, "url": "http://patchwork.ozlabs.org/api/people/93161/?format=api", "name": "Vishnu Reddy", "email": "busanna.reddy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-8-0296bccb9f4e@oss.qualcomm.com/mbox/", "series": [ { "id": 501197, "url": "http://patchwork.ozlabs.org/api/series/501197/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197", "date": "2026-04-23T13:29:29", "name": "media: iris: Add support for glymur platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501197/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227351/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227351/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13925-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=MX8sGrcq;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Ce6Rp88s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260423-glymur-v2-8-0296bccb9f4e@oss.qualcomm.com>", "References": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "In-Reply-To": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "To": "Bryan O'Donoghue <bod@kernel.org>,\n Vikash Garodia <vikash.garodia@oss.qualcomm.com>,\n Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,\n Abhinav Kumar <abhinav.kumar@linux.dev>,\n Mauro Carvalho Chehab <mchehab@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joerg Roedel <joro@8bytes.org>,\n Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Stefan Schmidt <stefan.schmidt@linaro.org>,\n Hans Verkuil <hverkuil@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n \"Rafael J. Wysocki\" <rafael@kernel.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Thierry Reding <thierry.reding@kernel.org>,\n Mikko Perttunen <mperttunen@nvidia.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Jonathan Hunter <jonathanh@nvidia.com>", "Cc": "linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy <busanna.reddy@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776950985; l=23045;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=snCiGYnE5lR7k11Sd8HZYZBUpIgzZpSwTWZQd9WBf78=;\n b=pGyp064lgiKzU7aaLuO6hn1B6gZtziER1XyFZ5rtaSBdVqLv2bijg47KbU3J0iQwVzuE3dPlT\n RyqvuxQJIjsALVpa8mE8yckSaoF063plyk+NtK3Ki9M8r4FucM7Datx", "X-Developer-Key": "i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfX1j7VvJ/rzIFx\n Jo+uynuvVVwQfGVsfnScvpcdrT3aVd5r7n6N5Lwg5jEGHPENous7n7ybfO5fVN5IDeUyNw0sclg\n HWYvsrEqMa11lHgGYQ9apD8G48SrYXm0F+z3kj8GXaeQtpCGExa5ovDbWb2jofpO4vxoJlWYzZE\n olXPaaR+tMCrN8OnC/mNR3CY2t1yGHwELkroZewq7SJwdmFiZ8jQ5r7bVqOHqJk7EiWlxbXJyV4\n IVJKdirL5fxWU0YO37JFtwlxweQlC/QZyubxYcFUTA8ijhSuzUlNw0f2UgGa79uKRWQyujBKcw7\n cdo5Z/jmm4JP9HfsLaxc9UvP9goef5MXPMII0VK/DIECopHc553KVzNwpmD3dt3XtxD6X1J7snx\n x6iP1Xq9NgimAiovX+KhXEJJabx1ezH16RwUDnF3h4VeU1ngAm/70by36jsXdT4dOjnvWfSEdqx\n vC0XG7xDXxr61zxz84g==", "X-Authority-Analysis": "v=2.4 cv=dL+WXuZb c=1 sm=1 tr=0 ts=69ea1f20 cx=c_pps\n a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22\n a=EUspDBNiAAAA:8 a=3jpyDGP9Yv0p6WhxEk8A:9 a=QEXdDO2ut3YA:10\n a=1OuFwYUASf3TG4hYMiVC:22", "X-Proofpoint-GUID": "a2cU-7VRI5Xr4AjC1NYF3ryLuePF2ZLv", "X-Proofpoint-ORIG-GUID": "a2cU-7VRI5Xr4AjC1NYF3ryLuePF2ZLv", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0\n adultscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230134" }, "content": "The pmdomain_tbl was a array of strings holding only the power domain\nnames. Callers had to pass a pd_devs[] pointer indexed directly by the\nplatform_pm_domain_type enum value to iris_enable_power_domains() and\niris_disable_power_domains().\n\nA future platform may need to introduce a new enum value that aliases\nan existing one (e.g. IRIS_VCODEC1_POWER_DOMAIN aliasing the\nIRIS_VPP0_HW_POWER_DOMAIN on Glymur), which would break the assumption\nthat enum values map 1:1 to pd_devs[] indices.\n\nTo fix this, replace the string array with a new struct platform_pd_data\nthat pairs each power domain name with its platform_pm_domain_type. Add\na helper iris_get_pd_index_by_type() that walks this table and returns\nthe correct pd_devs[] index for a given type.\n\nUpdate iris_enable_power_domains() and iris_disable_power_domains()\nto accept a platform_pm_domain_type instead of a struct device pointer.\nThey now call the helper internally to resolve the index, removing the\nneed for callers to do the index lookup themselves.\n\nThis prepares the driver for adding new platforms where power domain enum\nvalues cannot be used directly as pd_devs[] indices.\n\nSigned-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n---\n .../platform/qcom/iris/iris_platform_common.h | 9 +++-\n .../media/platform/qcom/iris/iris_platform_gen1.c | 18 +++++---\n .../media/platform/qcom/iris/iris_platform_gen2.c | 24 ++++++----\n drivers/media/platform/qcom/iris/iris_probe.c | 4 +-\n drivers/media/platform/qcom/iris/iris_resources.c | 44 +++++++++++++++++-\n drivers/media/platform/qcom/iris/iris_resources.h | 6 ++-\n drivers/media/platform/qcom/iris/iris_vpu3x.c | 9 ++--\n drivers/media/platform/qcom/iris/iris_vpu4x.c | 52 ++++++++--------------\n drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 +++++-----\n 9 files changed, 117 insertions(+), 72 deletions(-)", "diff": "diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h\nindex 30e9d4d288c6..7d59e6364e9d 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_common.h\n+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h\n@@ -212,6 +212,12 @@ enum platform_pm_domain_type {\n \tIRIS_APV_HW_POWER_DOMAIN,\n };\n \n+struct platform_pd_data {\n+\tenum platform_pm_domain_type *pd_types;\n+\tconst char **pd_names;\n+\tu32 pd_count;\n+};\n+\n struct iris_platform_data {\n \tvoid (*init_hfi_command_ops)(struct iris_core *core);\n \tvoid (*init_hfi_response_ops)(struct iris_core *core);\n@@ -225,8 +231,7 @@ struct iris_platform_data {\n \tunsigned int icc_tbl_size;\n \tconst struct bw_info *bw_tbl_dec;\n \tunsigned int bw_tbl_dec_size;\n-\tconst char * const *pmdomain_tbl;\n-\tunsigned int pmdomain_tbl_size;\n+\tconst struct platform_pd_data *pmdomain_tbl;\n \tconst char * const *opp_pd_tbl;\n \tunsigned int opp_pd_tbl_size;\n \tconst struct platform_clk_data *clk_tbl;\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c\nindex be6a631f8ede..0ec73783bc10 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c\n+++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c\n@@ -279,7 +279,17 @@ static const struct bw_info sm8250_bw_table_dec[] = {\n \t{ ((1920 * 1080) / 256) * 30, 416000 },\n };\n \n-static const char * const sm8250_pmdomain_table[] = { \"venus\", \"vcodec0\" };\n+static const struct platform_pd_data sm8250_pmdomain_table = {\n+\t.pd_types = (enum platform_pm_domain_type []) {\n+\t\tIRIS_CTRL_POWER_DOMAIN,\n+\t\tIRIS_VCODEC_POWER_DOMAIN,\n+\t},\n+\t.pd_names = (const char *[]) {\n+\t\t\"venus\",\n+\t\t\"vcodec0\",\n+\t},\n+\t.pd_count = 2,\n+};\n \n static const char * const sm8250_opp_pd_table[] = { \"mx\" };\n \n@@ -350,8 +360,7 @@ const struct iris_platform_data sm8250_data = {\n \t.clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table),\n \t.bw_tbl_dec = sm8250_bw_table_dec,\n \t.bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),\n-\t.pmdomain_tbl = sm8250_pmdomain_table,\n-\t.pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),\n+\t.pmdomain_tbl = &sm8250_pmdomain_table,\n \t.opp_pd_tbl = sm8250_opp_pd_table,\n \t.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),\n \t.clk_tbl = sm8250_clk_table,\n@@ -403,8 +412,7 @@ const struct iris_platform_data sc7280_data = {\n \t.icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),\n \t.bw_tbl_dec = sc7280_bw_table_dec,\n \t.bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),\n-\t.pmdomain_tbl = sm8250_pmdomain_table,\n-\t.pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),\n+\t.pmdomain_tbl = &sm8250_pmdomain_table,\n \t.opp_pd_tbl = sc7280_opp_pd_table,\n \t.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),\n \t.clk_tbl = sc7280_clk_table,\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c\nindex 47c6b650f0b4..5862c89a4971 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c\n+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c\n@@ -775,7 +775,17 @@ static const struct bw_info sm8550_bw_table_dec[] = {\n \t{ ((1920 * 1080) / 256) * 30, 294000 },\n };\n \n-static const char * const sm8550_pmdomain_table[] = { \"venus\", \"vcodec0\" };\n+static const struct platform_pd_data sm8550_pmdomain_table = {\n+\t.pd_types = (enum platform_pm_domain_type []) {\n+\t\tIRIS_CTRL_POWER_DOMAIN,\n+\t\tIRIS_VCODEC_POWER_DOMAIN,\n+\t},\n+\t.pd_names = (const char *[]) {\n+\t\t\"venus\",\n+\t\t\"vcodec0\",\n+\t},\n+\t.pd_count = 2,\n+};\n \n static const char * const sm8550_opp_pd_table[] = { \"mxc\", \"mmcx\" };\n \n@@ -934,8 +944,7 @@ const struct iris_platform_data sm8550_data = {\n \t.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),\n \t.bw_tbl_dec = sm8550_bw_table_dec,\n \t.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),\n-\t.pmdomain_tbl = sm8550_pmdomain_table,\n-\t.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),\n+\t.pmdomain_tbl = &sm8550_pmdomain_table,\n \t.opp_pd_tbl = sm8550_opp_pd_table,\n \t.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),\n \t.clk_tbl = sm8550_clk_table,\n@@ -1039,8 +1048,7 @@ const struct iris_platform_data sm8650_data = {\n \t.controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),\n \t.bw_tbl_dec = sm8550_bw_table_dec,\n \t.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),\n-\t.pmdomain_tbl = sm8550_pmdomain_table,\n-\t.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),\n+\t.pmdomain_tbl = &sm8550_pmdomain_table,\n \t.opp_pd_tbl = sm8550_opp_pd_table,\n \t.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),\n \t.clk_tbl = sm8550_clk_table,\n@@ -1135,8 +1143,7 @@ const struct iris_platform_data sm8750_data = {\n \t.clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),\n \t.bw_tbl_dec = sm8550_bw_table_dec,\n \t.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),\n-\t.pmdomain_tbl = sm8550_pmdomain_table,\n-\t.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),\n+\t.pmdomain_tbl = &sm8550_pmdomain_table,\n \t.opp_pd_tbl = sm8550_opp_pd_table,\n \t.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),\n \t.clk_tbl = sm8750_clk_table,\n@@ -1235,8 +1242,7 @@ const struct iris_platform_data qcs8300_data = {\n \t.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),\n \t.bw_tbl_dec = sm8550_bw_table_dec,\n \t.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),\n-\t.pmdomain_tbl = sm8550_pmdomain_table,\n-\t.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),\n+\t.pmdomain_tbl = &sm8550_pmdomain_table,\n \t.opp_pd_tbl = sm8550_opp_pd_table,\n \t.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),\n \t.clk_tbl = sm8550_clk_table,\ndiff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c\nindex 34751912f871..34c981be9bc1 100644\n--- a/drivers/media/platform/qcom/iris/iris_probe.c\n+++ b/drivers/media/platform/qcom/iris/iris_probe.c\n@@ -43,8 +43,8 @@ static int iris_init_power_domains(struct iris_core *core)\n \tint ret;\n \n \tstruct dev_pm_domain_attach_data iris_pd_data = {\n-\t\t.pd_names = core->iris_platform_data->pmdomain_tbl,\n-\t\t.num_pd_names = core->iris_platform_data->pmdomain_tbl_size,\n+\t\t.pd_names = core->iris_platform_data->pmdomain_tbl->pd_names,\n+\t\t.num_pd_names = core->iris_platform_data->pmdomain_tbl->pd_count,\n \t\t.pd_flags = PD_FLAG_NO_DEV_LINK,\n \t};\n \ndiff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c\nindex 773f6548370a..ae27488579d7 100644\n--- a/drivers/media/platform/qcom/iris/iris_resources.c\n+++ b/drivers/media/platform/qcom/iris/iris_resources.c\n@@ -70,10 +70,43 @@ int iris_opp_set_rate(struct device *dev, unsigned long freq)\n \treturn dev_pm_opp_set_opp(dev, opp);\n }\n \n-int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)\n+static int iris_get_pd_index_by_type(struct iris_core *core, enum platform_pm_domain_type pd_type)\n {\n+\tconst struct platform_pd_data *pd_tbl;\n+\tu32 pd_count, i;\n+\n+\tpd_tbl = core->iris_platform_data->pmdomain_tbl;\n+\tpd_count = core->iris_platform_data->pmdomain_tbl->pd_count;\n+\n+\tfor (i = 0; i < pd_count; i++) {\n+\t\tif (pd_tbl->pd_types[i] == pd_type)\n+\t\t\treturn i;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, bool hwmode)\n+{\n+\tint pd_index = iris_get_pd_index_by_type(core, pd_type);\n+\n+\tif (pd_index < 0)\n+\t\treturn pd_index;\n+\n+\treturn dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[pd_index], hwmode);\n+}\n+\n+int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type)\n+{\n+\tint pd_index = iris_get_pd_index_by_type(core, pd_type);\n+\tstruct device *pd_dev;\n \tint ret;\n \n+\tif (pd_index < 0)\n+\t\treturn pd_index;\n+\n+\tpd_dev = core->pmdomain_tbl->pd_devs[pd_index];\n+\n \tret = iris_opp_set_rate(core->dev, ULONG_MAX);\n \tif (ret)\n \t\treturn ret;\n@@ -85,10 +118,17 @@ int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)\n \treturn ret;\n }\n \n-int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)\n+int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type)\n {\n+\tint pd_index = iris_get_pd_index_by_type(core, pd_type);\n+\tstruct device *pd_dev;\n \tint ret;\n \n+\tif (pd_index < 0)\n+\t\treturn pd_index;\n+\n+\tpd_dev = core->pmdomain_tbl->pd_devs[pd_index];\n+\n \tret = iris_opp_set_rate(core->dev, 0);\n \tif (ret)\n \t\treturn ret;\ndiff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h\nindex 6bfbd2dc6db0..d5692e4694b1 100644\n--- a/drivers/media/platform/qcom/iris/iris_resources.h\n+++ b/drivers/media/platform/qcom/iris/iris_resources.h\n@@ -9,11 +9,13 @@\n struct iris_core;\n \n int iris_opp_set_rate(struct device *dev, unsigned long freq);\n-int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);\n-int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);\n+int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type);\n+int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type);\n int iris_unset_icc_bw(struct iris_core *core);\n int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw);\n int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type);\n int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type);\n+int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type,\n+\t\t\t bool hwmode);\n \n #endif\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c\nindex 1f0a3a47d87f..a9f43dbfc695 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c\n+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c\n@@ -208,7 +208,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core)\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_CLK);\n \n disable_power:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);\n \tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n \n \treturn 0;\n@@ -218,8 +218,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)\n {\n \tint ret;\n \n-\tret = iris_enable_power_domains(core,\n-\t\t\t\t\tcore->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n \tif (ret)\n \t\treturn ret;\n \n@@ -235,7 +234,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)\n \tif (ret)\n \t\tgoto err_disable_hw_free_clk;\n \n-\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);\n+\tret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true);\n \tif (ret)\n \t\tgoto err_disable_hw_clk;\n \n@@ -248,7 +247,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)\n err_disable_axi_clk:\n \tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n err_disable_power:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n \n \treturn ret;\n }\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c\nindex 4082d331d2f3..7b8922d8aec7 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu4x.c\n+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c\n@@ -27,28 +27,24 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32\n {\n \tint ret;\n \n-\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN],\n-\t\t\t\t hw_mode);\n+\tret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, hw_mode);\n \tif (ret)\n \t\treturn ret;\n \n \tif (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {\n-\t\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode);\n+\t\tret = iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, hw_mode);\n \t\tif (ret)\n \t\t\tgoto restore_hw_domain_mode;\n \t}\n \n \tif (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {\n-\t\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode);\n+\t\tret = iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, hw_mode);\n \t\tif (ret)\n \t\t\tgoto restore_vpp0_domain_mode;\n \t}\n \n \tif (!(efuse_value & DISABLE_VIDEO_APV_BIT)) {\n-\t\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t [IRIS_APV_HW_POWER_DOMAIN], hw_mode);\n+\t\tret = iris_genpd_set_hwmode(core, IRIS_APV_HW_POWER_DOMAIN, hw_mode);\n \t\tif (ret)\n \t\t\tgoto restore_vpp1_domain_mode;\n \t}\n@@ -57,14 +53,12 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32\n \n restore_vpp1_domain_mode:\n \tif (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))\n-\t\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN],\n-\t\t\t\t\t!hw_mode);\n+\t\tiris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, !hw_mode);\n restore_vpp0_domain_mode:\n \tif (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))\n-\t\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],\n-\t\t\t\t\t!hw_mode);\n+\t\tiris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, !hw_mode);\n restore_hw_domain_mode:\n-\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode);\n+\tiris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, !hw_mode);\n \n \treturn ret;\n }\n@@ -73,8 +67,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core)\n {\n \tint ret;\n \n-\tret = iris_enable_power_domains(core,\n-\t\t\t\t\tcore->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN);\n \tif (ret)\n \t\treturn ret;\n \n@@ -85,7 +78,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core)\n \treturn 0;\n \n disable_apv_hw_power_domain:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN);\n \n \treturn ret;\n }\n@@ -140,7 +133,7 @@ static void iris_vpu4x_power_off_apv(struct iris_core *core)\n \n disable_clocks_and_power:\n \tiris_disable_unprepare_clock(core, IRIS_APV_HW_CLK);\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN);\n }\n \n static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core)\n@@ -227,21 +220,18 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)\n \tu32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);\n \tint ret;\n \n-\tret = iris_enable_power_domains(core,\n-\t\t\t\t\tcore->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n \tif (ret)\n \t\treturn ret;\n \n \tif (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {\n-\t\tret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t\t[IRIS_VPP0_HW_POWER_DOMAIN]);\n+\t\tret = iris_enable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN);\n \t\tif (ret)\n \t\t\tgoto disable_hw_power_domain;\n \t}\n \n \tif (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {\n-\t\tret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t\t[IRIS_VPP1_HW_POWER_DOMAIN]);\n+\t\tret = iris_enable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN);\n \t\tif (ret)\n \t\t\tgoto disable_vpp0_power_domain;\n \t}\n@@ -273,14 +263,12 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)\n \tiris_vpu4x_disable_hardware_clocks(core, efuse_value);\n disable_vpp1_power_domain:\n \tif (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))\n-\t\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t\t[IRIS_VPP1_HW_POWER_DOMAIN]);\n+\t\tiris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN);\n disable_vpp0_power_domain:\n \tif (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))\n-\t\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t\t[IRIS_VPP0_HW_POWER_DOMAIN]);\n+\t\tiris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN);\n disable_hw_power_domain:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n \n \treturn ret;\n }\n@@ -351,14 +339,12 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core)\n \tiris_vpu4x_disable_hardware_clocks(core, efuse_value);\n \n \tif (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))\n-\t\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t [IRIS_VPP1_HW_POWER_DOMAIN]);\n+\t\tiris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN);\n \n \tif (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))\n-\t\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs\n-\t\t\t\t\t [IRIS_VPP0_HW_POWER_DOMAIN]);\n+\t\tiris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN);\n \n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n }\n \n const struct vpu_ops iris_vpu4x_ops = {\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c\nindex 006fd3ffc752..74b4dccd6a66 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c\n+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c\n@@ -214,15 +214,15 @@ int iris_vpu_power_off_controller(struct iris_core *core)\n \tiris_disable_unprepare_clock(core, IRIS_AHB_CLK);\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_CLK);\n \tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);\n \n \treturn 0;\n }\n \n void iris_vpu_power_off_hw(struct iris_core *core)\n {\n-\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false);\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tiris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false);\n+\tiris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n \tiris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);\n \tiris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);\n }\n@@ -243,7 +243,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)\n \tu32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;\n \tint ret;\n \n-\tret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);\n \tif (ret)\n \t\treturn ret;\n \n@@ -270,7 +270,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)\n err_disable_axi_clock:\n \tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n err_disable_power:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);\n \n \treturn ret;\n }\n@@ -279,8 +279,7 @@ int iris_vpu_power_on_hw(struct iris_core *core)\n {\n \tint ret;\n \n-\tret = iris_enable_power_domains(core,\n-\t\t\t\t\tcore->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n \tif (ret)\n \t\treturn ret;\n \n@@ -292,7 +291,7 @@ int iris_vpu_power_on_hw(struct iris_core *core)\n \tif (ret && ret != -ENOENT)\n \t\tgoto err_disable_hw_clock;\n \n-\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);\n+\tret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true);\n \tif (ret)\n \t\tgoto err_disable_hw_ahb_clock;\n \n@@ -303,7 +302,7 @@ int iris_vpu_power_on_hw(struct iris_core *core)\n err_disable_hw_clock:\n \tiris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);\n err_disable_power:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);\n \n \treturn ret;\n }\n@@ -365,7 +364,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);\n \tiris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);\n \n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);\n \n \treset_control_bulk_reset(clk_rst_tbl_size, core->resets);\n \n@@ -376,7 +375,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)\n {\n \tint ret;\n \n-\tret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);\n \tif (ret)\n \t\treturn ret;\n \n@@ -399,7 +398,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)\n err_disable_axi1_clk:\n \tiris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);\n err_disable_power:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);\n \n \treturn ret;\n }\n", "prefixes": [ "v2", "08/13" ] }