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GET /api/patches/2227350/?format=api
{ "id": 2227350, "url": "http://patchwork.ozlabs.org/api/patches/2227350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-6-0296bccb9f4e@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423-glymur-v2-6-0296bccb9f4e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T13:29:35", "name": "[v2,06/13] media: iris: Enable Secure PAS support with IOMMU managed by Linux", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a6aa91e51f631a9a1ce98379cf6342fe9251001a", "submitter": { "id": 93161, "url": "http://patchwork.ozlabs.org/api/people/93161/?format=api", "name": "Vishnu Reddy", "email": "busanna.reddy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-6-0296bccb9f4e@oss.qualcomm.com/mbox/", "series": [ { "id": 501197, "url": "http://patchwork.ozlabs.org/api/series/501197/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197", "date": "2026-04-23T13:29:29", "name": "media: iris: Add support for glymur platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501197/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227350/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227350/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13923-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ctgTCfjt;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ghca5sgQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260423-glymur-v2-6-0296bccb9f4e@oss.qualcomm.com>", "References": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "In-Reply-To": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "To": "Bryan O'Donoghue <bod@kernel.org>,\n Vikash Garodia <vikash.garodia@oss.qualcomm.com>,\n Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,\n Abhinav Kumar <abhinav.kumar@linux.dev>,\n Mauro Carvalho Chehab <mchehab@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joerg Roedel <joro@8bytes.org>,\n Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Stefan Schmidt <stefan.schmidt@linaro.org>,\n Hans Verkuil <hverkuil@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n \"Rafael J. Wysocki\" <rafael@kernel.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Thierry Reding <thierry.reding@kernel.org>,\n Mikko Perttunen <mperttunen@nvidia.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Jonathan Hunter <jonathanh@nvidia.com>", "Cc": "linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy <busanna.reddy@oss.qualcomm.com>,\n Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776950985; l=6587;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=+wQbHvxygQq1aTrGxrx3UsURZ3ABehuwxnmcohM5NBw=;\n b=IHAV46nQNLUubTgKIDVGhPfQgFqulUO86Kl3iSQPjE5X2LvjBkucJI7tXaO5ADNUMyAYQSmUy\n GeU+J5TShgmD+pOBgO8R/SKND0QoCtlowbWHzfA7yq598FkxFpcLcGV", "X-Developer-Key": "i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=", "X-Authority-Analysis": "v=2.4 cv=KPNqylFo c=1 sm=1 tr=0 ts=69ea1f0c cx=c_pps\n a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22\n a=EUspDBNiAAAA:8 a=gbwaY6mYjfx-u0ET_fsA:9 a=QEXdDO2ut3YA:10\n a=GvdueXVYPmCkWapjIL-Q:22", "X-Proofpoint-GUID": "BrIZSOPttMH_D9D5FHjzzCjWeoY5BHxG", "X-Proofpoint-ORIG-GUID": "BrIZSOPttMH_D9D5FHjzzCjWeoY5BHxG", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfX1NMyUAh+KJQO\n cH7ofl2VDkoWtZ5W+nLZlmOeGaY/4QJfVCICITubGZBcWClY4jutZGWtOezKlRqSQC82u/HAO5O\n gMAMBff2CY3RDIUgQONLPU11+S1qmNY53Nv0gooM8+5f5Xtb7esjAytKv60nwTcPqVDaYAsy/zp\n THKqtaFopcZ+jM4c7D1dHUeaTP0TVB+5zTIqM/AkRDXuS7wPibCQJNWKIECPzPFHVuwIhfE0tYP\n ICK4d0YXveYpzojqbCumOS8qSxhC0ysmM0KIk6RSnwhkzJG96HWhg7drJof3AU9hlO0tpOwcJYD\n wIO6RR2eUB5VRCFsXnlZsA6AsG7tZ+qs01hsliqsWxRvPQT6Edpdopud3kMIK31tjnuBZ46MEmE\n s7eIXho+fxHHwKjCF/MhHM3Fiemc5yPiyIrajvWU3RzaGmL2F/L9tuHuvs+sKhe629UydfRruBZ\n 4I/hNygGYu9NPAEF6tg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 malwarescore=0 bulkscore=0\n priorityscore=1501 suspectscore=0 spamscore=0 adultscore=0 phishscore=0\n impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604230134" }, "content": "From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>\n\nMost Qualcomm platforms feature a proprietary hypervisor (such as Gunyah\nor QHEE), which typically handles IOMMU configuration. This includes\nmapping memory regions and device memory resources for remote processors\nby intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are\nlater removed during teardown. Additionally, SHM bridge setup is required\nto enable memory protection for both remoteproc metadata and its memory\nregions.\n\nWhen the hypervisor is absent, the operating system must perform these\nconfigurations instead.\n\nSupport for handling IOMMU and SHM setup in the absence of a hypervisor\nis now in place. Extend the Iris driver to enable this functionality on\nplatforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE).\n\nAdditionally, the Iris driver must map the firmware and its required\nresources to the firmware SID, which is now specified via iommu-map in\nthe device tree.\n\nCo-developed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>\nSigned-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>\nSigned-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>\nSigned-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n---\n drivers/media/platform/qcom/iris/iris_core.h | 4 ++\n drivers/media/platform/qcom/iris/iris_firmware.c | 72 ++++++++++++++++++++----\n 2 files changed, 66 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h\nindex fb194c967ad4..b396c8cf595e 100644\n--- a/drivers/media/platform/qcom/iris/iris_core.h\n+++ b/drivers/media/platform/qcom/iris/iris_core.h\n@@ -34,6 +34,8 @@ enum domain_type {\n * struct iris_core - holds core parameters valid for all instances\n *\n * @dev: reference to device structure\n+ * @fw_dev: reference to the context bank device used for firmware load\n+ * @pas_ctx: SCM PAS context for authenticated firmware load and shutdown\n * @reg_base: IO memory base address\n * @irq: iris irq\n * @v4l2_dev: a holder for v4l2 device structure\n@@ -77,6 +79,8 @@ enum domain_type {\n \n struct iris_core {\n \tstruct device\t\t\t\t*dev;\n+\tstruct device\t\t\t\t*fw_dev;\n+\tstruct qcom_scm_pas_context\t\t*pas_ctx;\n \tvoid __iomem\t\t\t\t*reg_base;\n \tint\t\t\t\t\tirq;\n \tstruct v4l2_device\t\t\tv4l2_dev;\ndiff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c\nindex 5f408024e967..0085dd7ec052 100644\n--- a/drivers/media/platform/qcom/iris/iris_firmware.c\n+++ b/drivers/media/platform/qcom/iris/iris_firmware.c\n@@ -5,6 +5,7 @@\n \n #include <linux/firmware.h>\n #include <linux/firmware/qcom/qcom_scm.h>\n+#include <linux/iommu.h>\n #include <linux/of_address.h>\n #include <linux/of_reserved_mem.h>\n #include <linux/soc/qcom/mdt_loader.h>\n@@ -13,12 +14,15 @@\n #include \"iris_firmware.h\"\n \n #define MAX_FIRMWARE_NAME_SIZE\t128\n+#define IRIS_FW_START_ADDR\t0\n \n static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)\n {\n+\tstruct device *fw_dev = core->fw_dev ? core->fw_dev : core->dev;\n \tu32 pas_id = core->iris_platform_data->pas_id;\n \tconst struct firmware *firmware = NULL;\n-\tstruct device *dev = core->dev;\n+\tstruct qcom_scm_pas_context *pas_ctx;\n+\tstruct iommu_domain *domain;\n \tstruct resource res;\n \tphys_addr_t mem_phys;\n \tsize_t res_size;\n@@ -29,14 +33,18 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)\n \tif (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4)\n \t\treturn -EINVAL;\n \n-\tret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);\n+\tret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res);\n \tif (ret)\n \t\treturn ret;\n \n \tmem_phys = res.start;\n \tres_size = resource_size(&res);\n \n-\tret = request_firmware(&firmware, fw_name, dev);\n+\tpas_ctx = devm_qcom_scm_pas_context_alloc(fw_dev, pas_id, mem_phys, res_size);\n+\tif (IS_ERR(pas_ctx))\n+\t\treturn PTR_ERR(pas_ctx);\n+\n+\tret = request_firmware(&firmware, fw_name, fw_dev);\n \tif (ret)\n \t\treturn ret;\n \n@@ -52,9 +60,27 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)\n \t\tgoto err_release_fw;\n \t}\n \n-\tret = qcom_mdt_load(dev, firmware, fw_name,\n-\t\t\t pas_id, mem_virt, mem_phys, res_size, NULL);\n+\tpas_ctx->use_tzmem = !!core->fw_dev;\n+\tret = qcom_mdt_pas_load(pas_ctx, firmware, fw_name, mem_virt, NULL);\n+\tif (ret)\n+\t\tgoto err_mem_unmap;\n+\n+\tif (pas_ctx->use_tzmem) {\n+\t\tdomain = iommu_get_domain_for_dev(fw_dev);\n+\t\tif (!domain) {\n+\t\t\tret = -ENODEV;\n+\t\t\tgoto err_mem_unmap;\n+\t\t}\n+\n+\t\tret = iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size,\n+\t\t\t\tIOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL);\n+\t\tif (ret)\n+\t\t\tgoto err_mem_unmap;\n+\t}\n \n+\tcore->pas_ctx = pas_ctx;\n+\n+err_mem_unmap:\n \tmemunmap(mem_virt);\n err_release_fw:\n \trelease_firmware(firmware);\n@@ -62,6 +88,18 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)\n \treturn ret;\n }\n \n+static void iris_fw_iommu_unmap(struct iris_core *core)\n+{\n+\tstruct iommu_domain *domain;\n+\n+\tif (!core->pas_ctx->use_tzmem)\n+\t\treturn;\n+\n+\tdomain = iommu_get_domain_for_dev(core->fw_dev);\n+\tif (domain)\n+\t\tiommu_unmap(domain, IRIS_FW_START_ADDR, core->pas_ctx->mem_size);\n+}\n+\n int iris_fw_load(struct iris_core *core)\n {\n \tconst struct tz_cp_config *cp_config;\n@@ -79,10 +117,10 @@ int iris_fw_load(struct iris_core *core)\n \t\treturn -ENOMEM;\n \t}\n \n-\tret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id);\n+\tret = qcom_scm_pas_prepare_and_auth_reset(core->pas_ctx);\n \tif (ret) {\n \t\tdev_err(core->dev, \"auth and reset failed: %d\\n\", ret);\n-\t\treturn ret;\n+\t\tgoto err_unmap;\n \t}\n \n \tfor (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {\n@@ -93,17 +131,31 @@ int iris_fw_load(struct iris_core *core)\n \t\t\t\t\t\t cp_config->cp_nonpixel_size);\n \t\tif (ret) {\n \t\t\tdev_err(core->dev, \"qcom_scm_mem_protect_video_var failed: %d\\n\", ret);\n-\t\t\tqcom_scm_pas_shutdown(core->iris_platform_data->pas_id);\n-\t\t\treturn ret;\n+\t\t\tgoto err_pas_shutdown;\n \t\t}\n \t}\n \n+\treturn 0;\n+\n+err_pas_shutdown:\n+\tqcom_scm_pas_shutdown(core->pas_ctx->pas_id);\n+err_unmap:\n+\tiris_fw_iommu_unmap(core);\n+\n \treturn ret;\n }\n \n int iris_fw_unload(struct iris_core *core)\n {\n-\treturn qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);\n+\tint ret;\n+\n+\tret = qcom_scm_pas_shutdown(core->pas_ctx->pas_id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tiris_fw_iommu_unmap(core);\n+\n+\treturn ret;\n }\n \n int iris_set_hw_state(struct iris_core *core, bool resume)\n", "prefixes": [ "v2", "06/13" ] }