get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/2227106/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2227106,
    "url": "http://patchwork.ozlabs.org/api/patches/2227106/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423085718.70762-5-akhilrajeev@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260423085718.70762-5-akhilrajeev@nvidia.com>",
    "list_archive_url": null,
    "date": "2026-04-23T08:57:03",
    "name": "[v3,04/13] i3c: master: Support ACPI enumeration of child devices",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "d9d169bb6582583095cc3862f5c293c22b4be58d",
    "submitter": {
        "id": 81965,
        "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api",
        "name": "Akhil R",
        "email": "akhilrajeev@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423085718.70762-5-akhilrajeev@nvidia.com/mbox/",
    "series": [
        {
            "id": 501164,
            "url": "http://patchwork.ozlabs.org/api/series/501164/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501164",
            "date": "2026-04-23T08:56:59",
            "name": "Support ACPI and SETAASA device discovery",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/501164/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2227106/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2227106/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "\n <linux-tegra+bounces-13858-incoming=patchwork.ozlabs.org@vger.kernel.org>",
        "X-Original-To": [
            "incoming@patchwork.ozlabs.org",
            "linux-tegra@vger.kernel.org"
        ],
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
            "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=IrQSy/Ya;\n\tdkim-atps=neutral",
            "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13858-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)",
            "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"IrQSy/Ya\"",
            "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.208.35",
            "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com",
            "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com"
        ],
        "Received": [
            "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1VTN1HWYz1yGs\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 19:02:00 +1000 (AEST)",
            "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id A40C23033A86\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 08:59:16 +0000 (UTC)",
            "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 884223DFC80;\n\tThu, 23 Apr 2026 08:59:16 +0000 (UTC)",
            "from PH0PR06CU001.outbound.protection.outlook.com\n (mail-westus3azon11011035.outbound.protection.outlook.com [40.107.208.35])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 92F523DFC6B;\n\tThu, 23 Apr 2026 08:59:14 +0000 (UTC)",
            "from CH0PR03CA0219.namprd03.prod.outlook.com (2603:10b6:610:e7::14)\n by DS0PR12MB999080.namprd12.prod.outlook.com (2603:10b6:8:2fe::6) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.15; Thu, 23 Apr\n 2026 08:59:08 +0000",
            "from CH3PEPF0000000B.namprd04.prod.outlook.com\n (2603:10b6:610:e7:cafe::90) by CH0PR03CA0219.outlook.office365.com\n (2603:10b6:610:e7::14) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9846.21 via Frontend Transport; Thu,\n 23 Apr 2026 08:59:08 +0000",
            "from mail.nvidia.com (216.228.117.161) by\n CH3PEPF0000000B.mail.protection.outlook.com (10.167.244.38) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9846.18 via Frontend Transport; Thu, 23 Apr 2026 08:59:08 +0000",
            "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 23 Apr\n 2026 01:58:53 -0700",
            "from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 23 Apr\n 2026 01:58:53 -0700",
            "from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com\n (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend\n Transport; Thu, 23 Apr 2026 01:58:44 -0700"
        ],
        "ARC-Seal": [
            "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776934756; cv=fail;\n b=rNHBfoO3S2+9O1MmqipF1mkRtzmeuPCx9IEgFK1ZCqbu79F8UdEE/ghBfNd4sPOOSf9V5iAs+xbBxw308NBKVJsAcEv3l7rEsAASmXBleI64YKOvugiWETklt4eBtqwxP/7x0Hxl3oCb3y79ps/JJyHO6dA0tnmgt8JmcuhCWtQ=",
            "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=WYXCKGJIzUuZfWKYEliPHqOrjUZaggU8e8ZM3PEaAsyKt8CTRBjNfmVuGYKrG/zHbsFN3GPd9D8VqXurxyacoTmwIUTxOlvHJhvSg05DTIdgZgw4zc8dCxXL10Uvh2sYgqGoWBaAS6hf2rdsJZ6G5rD6jqfUQazxzE7dalEUpV9hkaGFuVyl7vSHHjzurSnaJJx2ouyn01cWvdbzck/yXcLFCkf2VIWoW7PoDKz4gUeKb2AA32sipFGSRQ2fg0oWpzlaYfDqM8KTPtWF0gDe10tQu3JjPmE413OJe0J3IM2vnEk8768HBguNnaDVD2/TZoSNRt7is06gQTnMG9Phvg=="
        ],
        "ARC-Message-Signature": [
            "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776934756; c=relaxed/simple;\n\tbh=Myjzc3Xch/GT2D5vkLkEObWRhP9v2wjnL0Lo3aE0U/I=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=NxtWIsUWmQv8fXsq7gzAi9UnD2psMBU4bt9JbAnPka8H1B9aSbYDcT+8wHIo8WVpUy3fdXCGQtMLnctiDkPD99T249urULdU66FfuWTvMu8uhjCw/jlQJge2W4mCzhdioSqfVlIxGJeg1W6HEyRrC36QHQgVVNdMoRccuFpLPL0=",
            "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=/oO13TN0bYaIX6MgiDPfO/k6cFCMqHGXAZ2+0IfZ6Gg=;\n b=K5Oi44JVxGQ0NyR1syxhha3k8Mr0PTj6ykOdaHuzsMeMYiHUtpFgRIRWcy2FLGe+A6Y+/Z/Yf0EB/5vQHLybpRkAxgbP+vO2WesdJR0rDFsnsfgjfC33qEW+3rxmyJpO0btuTtWMvH/qU/WDloJxXU/HFmJ1NBnCz8HpQ9C8Y0MTGSRoYzhg2cy+CcbRQf7Wwzw/SyzlDCtI8FJn40Kqru5uGCN5ocIYv4F74FYcPzv53ZQnuUEEfeauqOCU/u7/QvEXEectme/c9ezntlgmZGGrXzx9+yr49u9I3S1P958Ph46Jp2BDPr2mCUbeUkEIIaheQMB88JXSCcbjBAlkeA=="
        ],
        "ARC-Authentication-Results": [
            "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=IrQSy/Ya; arc=fail smtp.client-ip=40.107.208.35",
            "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=bootlin.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/oO13TN0bYaIX6MgiDPfO/k6cFCMqHGXAZ2+0IfZ6Gg=;\n b=IrQSy/YaVRkx6H8th/JnPY7bWuUb5VQsj0kaL/O3KLmKs0yz49p5rptTqKEUdeR2TjN60Fms6OYTgDf9bS5fUqcwvPZYxJcqusu6emGEmwBf/aabEwBZLsqf8rRSAq5Qtah23jHd4b0LdSRuJqP4djEDoKLrvd8Dqr1XfYOOnu3CM2wPV4avcB15LvmPWpabY0jxWadDRaw4JIKw9ysRu3NmtWO+YEiLC/mWghrenlzGrOzUOjZp55mMQGy37f/uyvHX6feJSBtAV7W5KYB4R8WI7xB34p2qArNXNZebioH+S5hV6l+NYmAm4F96EmBHd8bx/rRNc5SQjAxcMVVfTg==",
        "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;",
        "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C",
        "From": "Akhil R <akhilrajeev@nvidia.com>",
        "To": "Alexandre Belloni <alexandre.belloni@bootlin.com>, Frank Li\n\t<Frank.Li@nxp.com>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski\n\t<krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, \"Rafael J .\n Wysocki\" <rafael@kernel.org>, Saket Dumbre <saket.dumbre@intel.com>, \"Len\n Brown\" <lenb@kernel.org>, Guenter Roeck <linux@roeck-us.net>, Philipp Zabel\n\t<p.zabel@pengutronix.de>, Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>,\n\tGeert Uytterhoeven <geert@linux-m68k.org>, Dmitry Baryshkov\n\t<dmitry.baryshkov@oss.qualcomm.com>, Arnd Bergmann <arnd@arndb.de>, \"Eric\n Biggers\" <ebiggers@kernel.org>, Wolfram Sang\n\t<wsa+renesas@sang-engineering.com>, Miquel Raynal\n\t<miquel.raynal@bootlin.com>, Jon Hunter <jonathanh@nvidia.com>, \"Thierry\n Reding\" <treding@nvidia.com>, <linux-tegra@vger.kernel.org>,\n\t<linux-i3c@lists.infradead.org>, <devicetree@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<acpica-devel@lists.linux.dev>, <linux-hwmon@vger.kernel.org>",
        "CC": "Akhil R <akhilrajeev@nvidia.com>",
        "Subject": "[PATCH v3 04/13] i3c: master: Support ACPI enumeration of child\n devices",
        "Date": "Thu, 23 Apr 2026 14:27:03 +0530",
        "Message-ID": "<20260423085718.70762-5-akhilrajeev@nvidia.com>",
        "X-Mailer": "git-send-email 2.50.1",
        "In-Reply-To": "<20260423085718.70762-1-akhilrajeev@nvidia.com>",
        "References": "<20260423085718.70762-1-akhilrajeev@nvidia.com>",
        "Precedence": "bulk",
        "X-Mailing-List": "linux-tegra@vger.kernel.org",
        "List-Id": "<linux-tegra.vger.kernel.org>",
        "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>",
        "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>",
        "MIME-Version": "1.0",
        "X-NVConfidentiality": "public",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-NV-OnPremToCloud": "ExternallySecured",
        "X-EOPAttributedMessage": "0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-TrafficTypeDiagnostic": "CH3PEPF0000000B:EE_|DS0PR12MB999080:EE_",
        "X-MS-Office365-Filtering-Correlation-Id": "ace60fd3-1eea-49b4-3db9-08dea1169465",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
        "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|376014|36860700016|7416014|1800799024|13003099007|56012099003|921020|22082099003|18002099003;",
        "X-Microsoft-Antispam-Message-Info": "\n\tH/kwA3HqXCKD5UUzX21VndCeVns/jDBLl76inPPilrQfb/+z3YbI40wpRB104E60LDVdeU6gTC+R7sWaOsxU/vn3r3qoQ7AIXmq2FIE7yOTCpM/kE1r6MQEGNbncUL0wjaEbXaMsLg9OegT9WNjrOvfaPaNRm5OrySf8NvMrctqrG7egN1XTa10S+dHPsfDrOVDDMx+2K7W5CLL6hTvd1TrLtjawpxPOOVEX63NnS0DY+drXDZBK9sFIBJlTFgiMnJX/MicFQgNuFI3o8WS8Q8yc/DW+jkdA5s7Zs6tXFCLGwiDjG1rj/kzLdrIJtfjuvuaJBXufVYv9eARfVKCWUc4zExScLBMCzkBMytxIZaPXWDhdq7kAkCxHd+tMhS7OEEjLEifG6gMFd45l8jcNCPVqk7P9P8IIEOY18tLfE1yF6wEGkwl0s87j5T9FTPivOKyL15X8VDBeiJmSNo1Tk33siXeoP8RBmPbgGcc6W++RfNyUtKMc5VN3NeymjGQDLhUyW924mYfwJkAm17fyopz1FywpzHv5+aPOu7jna92bRR5JFze3aU2zJVcVZ/E9clHEzuVqqGQb3GVpErUYlwqCT7vI0VcH+DItpnH18EfvUzbV524Gmcb/8zQ08mRIvTCl4AHh8tjedSkx/q6Y7nARLPnFWyhNhNLvQT32hDiaI3luBNHfeZ41/XJfh5bkzrK8oEQnqTg4Qc1L+kuL5aCRrx1Mf8Rai1OeKHbDZrk4XzKmvIGsNDsZ0zyaafHFh324HPNbLl0nG8lxyqyXcEgTuZAoYYYTMCyOjilWlXVEEjqpTfamfJTA1jETOTkdNAPNesR0uIk0tVWblDm50A==",
        "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(7416014)(1800799024)(13003099007)(56012099003)(921020)(22082099003)(18002099003);DIR:OUT;SFP:1101;",
        "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1",
        "X-MS-Exchange-AntiSpam-MessageData-0": "\n\towjvJYCVTfxa0uqJOrYu8+12ROnfQ6Ew7MYlPxQEhlTTYTfjC9nECh8e00qcc0WuMqvwe4Ybc5TujVc2kcrvWnULPwvZfoOnIupwyTdeEdWgU4DwyXR+CgdQ35la+ppBanwIRi95ME008qe9yFZYf4C4929XMIbvpegNSF7EeQB9v79o5AXKORaCkGx4h61w5G46jcjaYohv5m+NgVAfIUHB9q1EWWXxeALtsJiyjpELoBpeR1OF/tJrKW4VmKo3RVWHL99MOSVG32DU+HbVhk176LcVRrjNfyRkBPvZXEbxkyhMiv3KELdCRuaxc/h73kMQaR/35IR+xi6Te2CSYwW3QJcAlHiOXtywHg0UaphkS3NBLBXeKkA7cTAs90WO/nz2fxHZ2JGVZls5FE8Za5GjpjMU+QdhOjIHpSr3e+6l7OABqr/eO/IdFkJdbJ+Y",
        "X-OriginatorOrg": "Nvidia.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Apr 2026 08:59:08.2712\n (UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ace60fd3-1eea-49b4-3db9-08dea1169465",
        "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a",
        "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]",
        "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCH3PEPF0000000B.namprd04.prod.outlook.com",
        "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB999080"
    },
    "content": "Although the existing subsystem allows host controllers to register\nthrough the ACPI table, it was not possible to describe I3C or I2C devices\nwhen using ACPI. This is because the driver relied on the reg property to\nretrieve the PID, static address, etc., whereas ACPI uses _ADR or serial\nresources to describe such devices.\n\nRead _ADR and LVR from the ACPI resources and extract the data as per the\nACPI specification for an I3C bus. Also read mipi-i3c-static-address as\nper the MIPI DISCO specifications [1] to get the static address to be\nused. Hence enable describing the I3C or I2C devices in the ACPI table,\nwhich is required if the device is using a static address or if it needs\nsome specific properties to be attached to it.\n\n[1] https://www.mipi.org/mipi-disco-for-i3c-download\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\n---\n drivers/i3c/master.c | 140 ++++++++++++++++++++++++++++++++++++++++---\n 1 file changed, 132 insertions(+), 8 deletions(-)",
    "diff": "diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c\nindex d0677061faab..ffec97157d48 100644\n--- a/drivers/i3c/master.c\n+++ b/drivers/i3c/master.c\n@@ -5,6 +5,7 @@\n  * Author: Boris Brezillon <boris.brezillon@bootlin.com>\n  */\n \n+#include <linux/acpi.h>\n #include <linux/atomic.h>\n #include <linux/bug.h>\n #include <linux/device.h>\n@@ -2409,6 +2410,53 @@ EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked);\n \n #define OF_I3C_REG1_IS_I2C_DEV\t\t\tBIT(31)\n \n+#ifdef CONFIG_ACPI\n+static int i3c_acpi_get_i2c_resource(struct acpi_resource *ares, void *data)\n+{\n+\tstruct i2c_dev_boardinfo *boardinfo = data;\n+\tstruct acpi_resource_i2c_serialbus *sb;\n+\n+\tif (!i2c_acpi_get_i2c_resource(ares, &sb))\n+\t\treturn 1;\n+\n+\tboardinfo->base.addr = sb->slave_address;\n+\tif (sb->access_mode == ACPI_I2C_10BIT_MODE)\n+\t\tboardinfo->base.flags |= I2C_CLIENT_TEN;\n+\n+\tboardinfo->lvr = sb->lvr;\n+\n+\treturn 0;\n+}\n+\n+static int i3c_acpi_add_i2c_boardinfo(struct i2c_dev_boardinfo *boardinfo,\n+\t\t\t\t      struct fwnode_handle *fwnode)\n+{\n+\tstruct acpi_device *adev = to_acpi_device_node(fwnode);\n+\tLIST_HEAD(resources);\n+\tint ret;\n+\n+\tboardinfo->base.fwnode = acpi_fwnode_handle(adev);\n+\n+\tret = acpi_dev_get_resources(adev, &resources,\n+\t\t\t\t     i3c_acpi_get_i2c_resource, boardinfo);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tacpi_dev_free_resource_list(&resources);\n+\n+\tif (!boardinfo->base.addr)\n+\t\treturn -ENODEV;\n+\n+\treturn 0;\n+}\n+#else\n+static inline int i3c_acpi_add_i2c_boardinfo(struct i2c_dev_boardinfo *boardinfo,\n+\t\t\t\t\t     struct fwnode_handle *fwnode)\n+{\n+\treturn -ENODEV;\n+}\n+#endif\n+\n static int\n i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,\n \t\t\t     struct fwnode_handle *fwnode, u32 *reg)\n@@ -2425,6 +2473,13 @@ i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,\n \t\tret = of_i2c_get_board_info(dev, to_of_node(fwnode), &boardinfo->base);\n \t\tif (ret)\n \t\t\treturn ret;\n+\n+\t\t/* LVR is encoded in reg[2] for Device Tree. */\n+\t\tboardinfo->lvr = reg[2];\n+\t} else if (is_acpi_device_node(fwnode)) {\n+\t\tret = i3c_acpi_add_i2c_boardinfo(boardinfo, fwnode);\n+\t\tif (ret)\n+\t\t\treturn ret;\n \t} else {\n \t\treturn -EINVAL;\n \t}\n@@ -2439,9 +2494,6 @@ i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,\n \t\treturn -EOPNOTSUPP;\n \t}\n \n-\t/* LVR is encoded in reg[2]. */\n-\tboardinfo->lvr = reg[2];\n-\n \tlist_add_tail(&boardinfo->node, &master->boardinfo.i2c);\n \tfwnode_handle_get(fwnode);\n \n@@ -2496,8 +2548,8 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,\n \treturn 0;\n }\n \n-static int i3c_master_add_dev(struct i3c_master_controller *master,\n-\t\t\t      struct fwnode_handle *fwnode)\n+static int i3c_master_add_of_dev(struct i3c_master_controller *master,\n+\t\t\t\t struct fwnode_handle *fwnode)\n {\n \tu32 reg[3];\n \tint ret;\n@@ -2521,6 +2573,67 @@ static int i3c_master_add_dev(struct i3c_master_controller *master,\n \treturn ret;\n }\n \n+#ifdef CONFIG_ACPI\n+static int i3c_master_add_acpi_dev(struct i3c_master_controller *master,\n+\t\t\t\t   struct fwnode_handle *fwnode)\n+{\n+\tstruct acpi_device *adev = to_acpi_device_node(fwnode);\n+\tacpi_bus_address adr;\n+\tu32 reg[3] = { 0 };\n+\n+\t/*\n+\t * If the ACPI table entry does not have _ADR method, it's an I2C device\n+\t * If the ACPI table entry has _ADR method, it's an I3C device\n+\t */\n+\tif (!acpi_has_method(adev->handle, \"_ADR\"))\n+\t\treturn i3c_master_add_i2c_boardinfo(master, fwnode, reg);\n+\n+\tadr = acpi_device_adr(adev);\n+\n+\t/* For I3C devices, _ADR will have the 48 bit PID of the device  */\n+\treg[1] = upper_32_bits(adr);\n+\treg[2] = lower_32_bits(adr);\n+\n+\tfwnode_property_read_u32(fwnode, \"mipi-i3c-static-address\", &reg[0]);\n+\n+\treturn i3c_master_add_i3c_boardinfo(master, fwnode, reg);\n+}\n+\n+static u8 i3c_acpi_i2c_get_lvr(struct i2c_client *client)\n+{\n+\tstruct acpi_device *adev = to_acpi_device_node(client->dev.fwnode);\n+\tstruct i2c_dev_boardinfo boardinfo = {};\n+\tLIST_HEAD(resources);\n+\tint ret;\n+\tu8 lvr;\n+\n+\tlvr = I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE;\n+\n+\tret = acpi_dev_get_resources(adev, &resources,\n+\t\t\t\t     i3c_acpi_get_i2c_resource, &boardinfo);\n+\tif (ret < 0)\n+\t\treturn lvr;\n+\n+\tif (boardinfo.base.addr)\n+\t\tlvr = boardinfo.lvr;\n+\n+\tacpi_dev_free_resource_list(&resources);\n+\n+\treturn lvr;\n+}\n+#else\n+static inline int i3c_master_add_acpi_dev(struct i3c_master_controller *master,\n+\t\t\t\t\t  struct fwnode_handle *fwnode)\n+{\n+\treturn -ENODEV;\n+}\n+\n+static inline u8 i3c_acpi_i2c_get_lvr(struct i2c_client *client)\n+{\n+\treturn I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE;\n+}\n+#endif\n+\n static int fwnode_populate_i3c_bus(struct i3c_master_controller *master)\n {\n \tstruct device *dev = &master->dev;\n@@ -2532,7 +2645,13 @@ static int fwnode_populate_i3c_bus(struct i3c_master_controller *master)\n \t\treturn 0;\n \n \tfwnode_for_each_available_child_node_scoped(fwnode, child) {\n-\t\tret = i3c_master_add_dev(master, child);\n+\t\tif (is_of_node(child))\n+\t\t\tret = i3c_master_add_of_dev(master, child);\n+\t\telse if (is_acpi_device_node(child))\n+\t\t\tret = i3c_master_add_acpi_dev(master, child);\n+\t\telse\n+\t\t\tcontinue;\n+\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n@@ -2600,8 +2719,13 @@ static u8 i3c_master_i2c_get_lvr(struct i2c_client *client)\n \tu8 lvr = I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE;\n \tu32 reg[3];\n \n-\tif (!fwnode_property_read_u32_array(client->dev.fwnode, \"reg\", reg, ARRAY_SIZE(reg)))\n-\t\tlvr = reg[2];\n+\tif (is_of_node(client->dev.fwnode)) {\n+\t\tif (!fwnode_property_read_u32_array(client->dev.fwnode, \"reg\",\n+\t\t\t\t\t\t    reg, ARRAY_SIZE(reg)))\n+\t\t\tlvr = reg[2];\n+\t} else if (is_acpi_device_node(client->dev.fwnode)) {\n+\t\tlvr = i3c_acpi_i2c_get_lvr(client);\n+\t}\n \n \treturn lvr;\n }\n",
    "prefixes": [
        "v3",
        "04/13"
    ]
}