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GET /api/patches/2227081/?format=api
{ "id": 2227081, "url": "http://patchwork.ozlabs.org/api/patches/2227081/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/bf46348985e9c89b8c3f40cd3d00f5bca9d97097.1776932336.git.andrea.porta@suse.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bf46348985e9c89b8c3f40cd3d00f5bca9d97097.1776932336.git.andrea.porta@suse.com>", "list_archive_url": null, "date": "2026-04-23T08:30:20", "name": "[v3,2/3] pwm: rp1: Add RP1 PWM controller driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f0cd947b7b9a393421e6df1c87454e1f7ba07fac", "submitter": { "id": 88172, "url": "http://patchwork.ozlabs.org/api/people/88172/?format=api", "name": "Andrea della Porta", "email": "andrea.porta@suse.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/bf46348985e9c89b8c3f40cd3d00f5bca9d97097.1776932336.git.andrea.porta@suse.com/mbox/", "series": [ { "id": 501159, "url": "http://patchwork.ozlabs.org/api/series/501159/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=501159", "date": "2026-04-23T08:30:20", "name": "Add RP1 PWM controller support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501159/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227081/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227081/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-8674-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=suse.com header.i=@suse.com header.a=rsa-sha256\n header.s=google header.b=G4b6aTov;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "From: Naushir Patuck <naush@raspberrypi.com>\n\nThe Raspberry Pi RP1 southbridge features an embedded PWM\ncontroller with 4 output channels, alongside an RPM interface\nto read the fan speed on the Raspberry Pi 5.\n\nAdd the supporting driver.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\nCo-developed-by: Stanimir Varbanov <svarbanov@suse.de>\nSigned-off-by: Stanimir Varbanov <svarbanov@suse.de>\nSigned-off-by: Andrea della Porta <andrea.porta@suse.com>\n---\n drivers/pwm/Kconfig | 9 +\n drivers/pwm/Makefile | 1 +\n drivers/pwm/pwm-rp1.c | 414 ++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 424 insertions(+)\n create mode 100644 drivers/pwm/pwm-rp1.c", "diff": "diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig\nindex 6f3147518376a..32031f2af75af 100644\n--- a/drivers/pwm/Kconfig\n+++ b/drivers/pwm/Kconfig\n@@ -625,6 +625,15 @@ config PWM_ROCKCHIP\n \t Generic PWM framework driver for the PWM controller found on\n \t Rockchip SoCs.\n \n+config PWM_RASPBERRYPI_RP1\n+\tbool \"RP1 PWM support\"\n+\tdepends on MISC_RP1 || COMPILE_TEST\n+\tdepends on HAS_IOMEM\n+\tselect REGMAP_MMIO\n+\tselect MFD_SYSCON\n+\thelp\n+\t PWM framework driver for Raspberry Pi RP1 controller.\n+\n config PWM_SAMSUNG\n \ttristate \"Samsung PWM support\"\n \tdepends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST\ndiff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile\nindex 0dc0d2b69025d..59f29f60f9123 100644\n--- a/drivers/pwm/Makefile\n+++ b/drivers/pwm/Makefile\n@@ -56,6 +56,7 @@ obj-$(CONFIG_PWM_RENESAS_RZG2L_GPT)\t+= pwm-rzg2l-gpt.o\n obj-$(CONFIG_PWM_RENESAS_RZ_MTU3)\t+= pwm-rz-mtu3.o\n obj-$(CONFIG_PWM_RENESAS_TPU)\t+= pwm-renesas-tpu.o\n obj-$(CONFIG_PWM_ROCKCHIP)\t+= pwm-rockchip.o\n+obj-$(CONFIG_PWM_RASPBERRYPI_RP1)\t+= pwm-rp1.o\n obj-$(CONFIG_PWM_SAMSUNG)\t+= pwm-samsung.o\n obj-$(CONFIG_PWM_SIFIVE)\t+= pwm-sifive.o\n obj-$(CONFIG_PWM_SL28CPLD)\t+= pwm-sl28cpld.o\ndiff --git a/drivers/pwm/pwm-rp1.c b/drivers/pwm/pwm-rp1.c\nnew file mode 100644\nindex 0000000000000..15087917a18e9\n--- /dev/null\n+++ b/drivers/pwm/pwm-rp1.c\n@@ -0,0 +1,414 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * pwm-rp1.c\n+ *\n+ * Raspberry Pi RP1 PWM.\n+ *\n+ * Copyright © 2026 Raspberry Pi Ltd.\n+ *\n+ * Author: Naushir Patuck (naush@raspberrypi.com)\n+ *\n+ * Based on the pwm-bcm2835 driver by:\n+ * Bart Tanghe <bart.tanghe@thomasmore.be>\n+ *\n+ * Datasheet: https://pip-assets.raspberrypi.com/categories/892-raspberry-pi-5/documents/RP-008370-DS-1-rp1-peripherals.pdf?disposition=inline\n+ *\n+ * Limitations:\n+ * - Channels can be enabled/disabled through a global update flag, while the\n+ * period and duty per-channel registers are independently updatable, and\n+ * they are latched on the end of (specific channel) period strobe.\n+ * This means that period and duty changes might result in glitches if the\n+ * period/duty is changed exactly during an end of period strobe.\n+ * - Since the duty/period registers are freely updatable (do not depend on\n+ * the global update flag), setting one of them close to the period end and\n+ * the other right afterwards results in a mixed output for that cycle because\n+ * the write ops are not atomic.\n+ * - The global update flag prevents mis-sampling of multi-bit bus signals in\n+ * the PWM clock domain. This ensures that all PWM channel settings update\n+ * on the same PWM clock cycle. Channels start in sync only if they share the\n+ * same period.\n+ * - If both duty and period are set to 0, the output is a constant low signal\n+ * if polarity is normal or a constant high signal if polarity is inversed.\n+ * - When disabled the output is driven to 0 if polarity is normal, or to 1\n+ * if polarity is inversed.\n+ * - Disabling the PWM stops the output immediately, without waiting for current\n+ * period to complete first.\n+ * - Channels are phase-capable, but on RPi5, the firmware can use a channel\n+ * phase register to report the RPM of the fan connected to that PWM\n+ * channel. As a result, phase control will be ignored for now.\n+ */\n+\n+#include <linux/bitops.h>\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/pwm.h>\n+#include <linux/regmap.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/units.h>\n+\n+#define RP1_PWM_GLB_CTRL\t\t\t0x000\n+#define RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(chan)\tBIT(chan)\n+#define RP1_PWM_GLB_CTRL_SET_UPDATE\t\tBIT(31)\n+\n+#define RP1_PWM_CHAN_CTRL(chan)\t\t\t(0x014 + ((chan) * 0x10))\n+#define RP1_PWM_CHAN_CTRL_POLARITY\t\tBIT(3)\n+#define RP1_PWM_CHAN_CTRL_FIFO_POP_MASK\t\tBIT(8)\n+#define RP1_PWM_CHAN_CTRL_MODE\t\t\tGENMASK(2, 0)\n+enum rp1_pwm_ctrl_mode {\n+\tRP1_PWM_CHAN_CTRL_MODE_ZERO,\n+\tRP1_PWM_CHAN_CTRL_MODE_TE_MS,\n+\tRP1_PWM_CHAN_CTRL_MODE_PC_MS,\n+\tRP1_PWM_CHAN_CTRL_MODE_PD_ENC,\n+\tRP1_PWM_CHAN_CTRL_MODE_MSB_SER,\n+\tRP1_PWM_CHAN_CTRL_MODE_PPM,\n+\tRP1_PWM_CHAN_CTRL_MODE_LE_MS,\n+\tRP1_PWM_CHAN_CTRL_MODE_LSB_SER,\n+};\n+\n+#define RP1_PWM_CHAN_CTRL_DEFAULT\t\t(RP1_PWM_CHAN_CTRL_FIFO_POP_MASK + \\\n+\t\t\t\t\t\tFIELD_PREP(RP1_PWM_CHAN_CTRL_MODE, \\\n+\t\t\t\t\t\tRP1_PWM_CHAN_CTRL_MODE_TE_MS))\n+\n+#define RP1_PWM_RANGE(chan)\t\t\t(0x018 + ((chan) * 0x10))\n+#define RP1_PWM_PHASE(chan)\t\t\t(0x01C + ((chan) * 0x10))\n+#define RP1_PWM_DUTY(chan)\t\t\t(0x020 + ((chan) * 0x10))\n+\n+#define RP1_PWM_NUM_PWMS\t\t\t4\n+\n+struct rp1_pwm {\n+\tstruct regmap *regmap;\n+\tstruct clk *clk;\n+\tunsigned long clk_rate;\n+\tbool clk_enabled;\n+};\n+\n+struct rp1_pwm_waveform {\n+\tu32 period_ticks;\n+\tu32 duty_ticks;\n+\tbool enabled;\n+\tbool inverted_polarity;\n+};\n+\n+static const struct regmap_config rp1_pwm_regmap_config = {\n+\t.reg_bits = 32,\n+\t.val_bits = 32,\n+\t.reg_stride = 4,\n+\t.max_register = 0x60,\n+};\n+\n+static void rp1_pwm_apply_config(struct pwm_chip *chip, struct pwm_device *pwm)\n+{\n+\tstruct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);\n+\tu32 value;\n+\n+\t/* update the changed registers on the next strobe to avoid glitches */\n+\tregmap_read(rp1->regmap, RP1_PWM_GLB_CTRL, &value);\n+\tvalue |= RP1_PWM_GLB_CTRL_SET_UPDATE;\n+\tregmap_write(rp1->regmap, RP1_PWM_GLB_CTRL, value);\n+}\n+\n+static int rp1_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)\n+{\n+\tstruct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);\n+\n+\t/* init channel to reset defaults */\n+\tregmap_write(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), RP1_PWM_CHAN_CTRL_DEFAULT);\n+\treturn 0;\n+}\n+\n+static int rp1_pwm_round_waveform_tohw(struct pwm_chip *chip,\n+\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t const struct pwm_waveform *wf,\n+\t\t\t\t void *_wfhw)\n+{\n+\tstruct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);\n+\tu64 period_ticks, duty_ticks, offset_ticks;\n+\tstruct rp1_pwm_waveform *wfhw = _wfhw;\n+\tu64 clk_rate = rp1->clk_rate;\n+\tint ret = 0;\n+\n+\tif (!wf->period_length_ns) {\n+\t\twfhw->enabled = false;\n+\t\treturn 0;\n+\t}\n+\n+\tperiod_ticks = mul_u64_u64_div_u64(wf->period_length_ns, clk_rate, NSEC_PER_SEC);\n+\n+\t/*\n+\t * The period is limited to U32_MAX - 1\n+\t * to allow 100% duty cycle.\n+\t */\n+\tif (period_ticks > U32_MAX) {\n+\t\tperiod_ticks = U32_MAX - 1;\n+\t} else if (!period_ticks) {\n+\t\tperiod_ticks = 2;\n+\t\tret = 1;\n+\t}\n+\n+\tduty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, clk_rate, NSEC_PER_SEC);\n+\toffset_ticks = mul_u64_u64_div_u64(wf->duty_offset_ns, clk_rate, NSEC_PER_SEC);\n+\tif (duty_ticks && offset_ticks &&\n+\t duty_ticks + offset_ticks >= period_ticks) {\n+\t\twfhw->duty_ticks = period_ticks - duty_ticks;\n+\t\twfhw->inverted_polarity = true;\n+\t} else {\n+\t\twfhw->duty_ticks = duty_ticks;\n+\t\twfhw->inverted_polarity = false;\n+\t}\n+\t/* Account for the extra tick at the end of the period */\n+\twfhw->period_ticks = period_ticks - 1;\n+\n+\twfhw->enabled = true;\n+\n+\treturn ret;\n+}\n+\n+static int rp1_pwm_round_waveform_fromhw(struct pwm_chip *chip,\n+\t\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t\t const void *_wfhw,\n+\t\t\t\t\t struct pwm_waveform *wf)\n+{\n+\tstruct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);\n+\tconst struct rp1_pwm_waveform *wfhw = _wfhw;\n+\tu64 clk_rate = rp1->clk_rate;\n+\tu32 ticks;\n+\n+\t*wf = (struct pwm_waveform){ };\n+\n+\tif (!wfhw->enabled)\n+\t\treturn 0;\n+\n+\twf->period_length_ns = DIV_ROUND_UP_ULL((u64)(wfhw->period_ticks + 1) * NSEC_PER_SEC,\n+\t\t\t\t\t\tclk_rate);\n+\n+\tif (!wfhw->inverted_polarity) {\n+\t\twf->duty_length_ns = DIV_ROUND_UP_ULL((u64)wfhw->duty_ticks * NSEC_PER_SEC,\n+\t\t\t\t\t\t clk_rate);\n+\t} else {\n+\t\tticks = wfhw->period_ticks + 1 - wfhw->duty_ticks;\n+\t\twf->duty_length_ns = DIV_ROUND_UP_ULL((u64)ticks * NSEC_PER_SEC, clk_rate);\n+\t\twf->duty_offset_ns = wf->period_length_ns - wf->duty_length_ns;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rp1_pwm_write_waveform(struct pwm_chip *chip,\n+\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t const void *_wfhw)\n+{\n+\tstruct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);\n+\tconst struct rp1_pwm_waveform *wfhw = _wfhw;\n+\tu32 value, ctrl;\n+\n+\t/* early exit if disabled */\n+\tregmap_read(rp1->regmap, RP1_PWM_GLB_CTRL, &ctrl);\n+\tif (!wfhw->enabled) {\n+\t\tctrl &= ~RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(pwm->hwpwm);\n+\t\tgoto exit_disable;\n+\t}\n+\n+\t/* set period and duty cycle */\n+\tregmap_write(rp1->regmap,\n+\t\t RP1_PWM_RANGE(pwm->hwpwm), wfhw->period_ticks);\n+\tregmap_write(rp1->regmap,\n+\t\t RP1_PWM_DUTY(pwm->hwpwm), wfhw->duty_ticks);\n+\n+\t/* set polarity */\n+\tregmap_read(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), &value);\n+\tif (!wfhw->inverted_polarity)\n+\t\tvalue &= ~RP1_PWM_CHAN_CTRL_POLARITY;\n+\telse\n+\t\tvalue |= RP1_PWM_CHAN_CTRL_POLARITY;\n+\tregmap_write(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), value);\n+\n+\t/* enable the channel */\n+\tctrl |= RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(pwm->hwpwm);\n+exit_disable:\n+\tregmap_write(rp1->regmap, RP1_PWM_GLB_CTRL, ctrl);\n+\n+\trp1_pwm_apply_config(chip, pwm);\n+\n+\treturn 0;\n+}\n+\n+static int rp1_pwm_read_waveform(struct pwm_chip *chip,\n+\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t void *_wfhw)\n+{\n+\tstruct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);\n+\tstruct rp1_pwm_waveform *wfhw = _wfhw;\n+\tu32 value;\n+\n+\tregmap_read(rp1->regmap, RP1_PWM_GLB_CTRL, &value);\n+\twfhw->enabled = !!(value & RP1_PWM_GLB_CTRL_CHANNEL_ENABLE(pwm->hwpwm));\n+\n+\tregmap_read(rp1->regmap, RP1_PWM_CHAN_CTRL(pwm->hwpwm), &value);\n+\twfhw->inverted_polarity = !!(value & RP1_PWM_CHAN_CTRL_POLARITY);\n+\n+\tif (wfhw->enabled) {\n+\t\tregmap_read(rp1->regmap, RP1_PWM_RANGE(pwm->hwpwm), &wfhw->period_ticks);\n+\t\tregmap_read(rp1->regmap, RP1_PWM_DUTY(pwm->hwpwm), &wfhw->duty_ticks);\n+\t} else {\n+\t\twfhw->period_ticks = 0;\n+\t\twfhw->duty_ticks = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct pwm_ops rp1_pwm_ops = {\n+\t.sizeof_wfhw = sizeof(struct rp1_pwm_waveform),\n+\t.request = rp1_pwm_request,\n+\t.round_waveform_tohw = rp1_pwm_round_waveform_tohw,\n+\t.round_waveform_fromhw = rp1_pwm_round_waveform_fromhw,\n+\t.read_waveform = rp1_pwm_read_waveform,\n+\t.write_waveform = rp1_pwm_write_waveform,\n+};\n+\n+static int rp1_pwm_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *np = dev->of_node;\n+\tunsigned long clk_rate;\n+\tstruct pwm_chip *chip;\n+\tvoid __iomem\t*base;\n+\tstruct rp1_pwm *rp1;\n+\tint ret;\n+\n+\tchip = devm_pwmchip_alloc(dev, RP1_PWM_NUM_PWMS, sizeof(*rp1));\n+\tif (IS_ERR(chip))\n+\t\treturn PTR_ERR(chip);\n+\n+\trp1 = pwmchip_get_drvdata(chip);\n+\n+\tbase = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\trp1->regmap = devm_regmap_init_mmio(dev, base, &rp1_pwm_regmap_config);\n+\tif (IS_ERR(rp1->regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(rp1->regmap), \"Cannot initialize regmap\\n\");\n+\n+\tret = of_syscon_register_regmap(np, rp1->regmap);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to register syscon\\n\");\n+\n+\trp1->clk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(rp1->clk))\n+\t\treturn dev_err_probe(dev, PTR_ERR(rp1->clk), \"Clock not found\\n\");\n+\n+\tret = clk_prepare_enable(rp1->clk);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to enable clock\\n\");\n+\trp1->clk_enabled = true;\n+\n+\tret = devm_clk_rate_exclusive_get(dev, rp1->clk);\n+\tif (ret) {\n+\t\tdev_err_probe(dev, ret, \"Failed to get exclusive rate\\n\");\n+\t\tgoto err_disable_clk;\n+\t}\n+\n+\tclk_rate = clk_get_rate(rp1->clk);\n+\tif (!clk_rate) {\n+\t\tret = dev_err_probe(dev, -EINVAL, \"Failed to get clock rate\\n\");\n+\t\tgoto err_disable_clk;\n+\t}\n+\t/*\n+\t * To prevent u64 overflow in period calculations:\n+\t * mul_u64_u64_div_u64(period_ns, clk_rate, NSEC_PER_SEC)\n+\t * If clk_rate > 1 GHz, the result can overflow.\n+\t */\n+\tif (clk_rate > HZ_PER_GHZ) {\n+\t\tret = dev_err_probe(dev, -EINVAL, \"Clock rate > 1 GHz is not supported\\n\");\n+\t\tgoto err_disable_clk;\n+\t}\n+\trp1->clk_rate = clk_rate;\n+\n+\tchip->ops = &rp1_pwm_ops;\n+\n+\tplatform_set_drvdata(pdev, chip);\n+\n+\tret = pwmchip_add(chip);\n+\tif (ret) {\n+\t\tdev_err_probe(dev, ret, \"Failed to register PWM chip\\n\");\n+\t\tgoto err_disable_clk;\n+\t}\n+\n+\treturn 0;\n+\n+err_disable_clk:\n+\tclk_disable_unprepare(rp1->clk);\n+\n+\treturn ret;\n+}\n+\n+static void rp1_pwm_remove(struct platform_device *pdev)\n+{\n+\tstruct pwm_chip *chip = platform_get_drvdata(pdev);\n+\tstruct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);\n+\n+\tpwmchip_remove(chip);\n+\n+\tif (rp1->clk_enabled) {\n+\t\tclk_disable_unprepare(rp1->clk);\n+\t\trp1->clk_enabled = false;\n+\t}\n+}\n+\n+static int rp1_pwm_suspend(struct device *dev)\n+{\n+\tstruct rp1_pwm *rp1 = dev_get_drvdata(dev);\n+\n+\tif (rp1->clk_enabled) {\n+\t\tclk_disable_unprepare(rp1->clk);\n+\t\trp1->clk_enabled = false;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rp1_pwm_resume(struct device *dev)\n+{\n+\tstruct rp1_pwm *rp1 = dev_get_drvdata(dev);\n+\tint ret;\n+\n+\tret = clk_prepare_enable(rp1->clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to enable clock on resume: %pe\\n\", ERR_PTR(ret));\n+\t\treturn ret;\n+\t}\n+\n+\trp1->clk_enabled = true;\n+\n+\treturn 0;\n+}\n+\n+static DEFINE_SIMPLE_DEV_PM_OPS(rp1_pwm_pm_ops, rp1_pwm_suspend, rp1_pwm_resume);\n+\n+static const struct of_device_id rp1_pwm_of_match[] = {\n+\t{ .compatible = \"raspberrypi,rp1-pwm\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, rp1_pwm_of_match);\n+\n+static struct platform_driver rp1_pwm_driver = {\n+\t.probe = rp1_pwm_probe,\n+\t.remove = rp1_pwm_remove,\n+\t.driver = {\n+\t\t.name = \"rp1-pwm\",\n+\t\t.of_match_table = rp1_pwm_of_match,\n+\t\t.pm = pm_ptr(&rp1_pwm_pm_ops),\n+\t\t.suppress_bind_attrs = true,\n+\t},\n+};\n+module_platform_driver(rp1_pwm_driver);\n+\n+MODULE_DESCRIPTION(\"RP1 PWM driver\");\n+MODULE_AUTHOR(\"Naushir Patuck <naush@raspberrypi.com>\");\n+MODULE_AUTHOR(\"Andrea della Porta <andrea.porta@suse.com>\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "v3", "2/3" ] }