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GET /api/patches/2227060/?format=api
{ "id": 2227060, "url": "http://patchwork.ozlabs.org/api/patches/2227060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260423052339.356900-5-anup.patel@oss.qualcomm.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260423052339.356900-5-anup.patel@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T05:23:37", "name": "[4/6] lib: sbi_irqchip: Allow marking hardware interrupts as reserved", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "563b17b0ee9440d4e41b25e7dee77f242a805f3d", "submitter": { "id": 92322, "url": "http://patchwork.ozlabs.org/api/people/92322/?format=api", "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260423052339.356900-5-anup.patel@oss.qualcomm.com/mbox/", "series": [ { "id": 501146, "url": "http://patchwork.ozlabs.org/api/series/501146/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=501146", "date": "2026-04-23T05:23:35", "name": "Extend irqchip framework for MSIs and line sensing", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501146/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227060/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=4rkV4qGq;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=BqmgdnJv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=temperror (SPF Temporary Error: DNS Timeout)\n smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133;\n helo=bombadil.infradead.org;\n envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1PfQ14qNz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; 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s=qcppdkim1; bh=kMH8BvPuN1F\n\tHEYKs+UPWpnJs4RDr0GOsQ/cpq7rdpkQ=; b=BqmgdnJvTrkaBPxWIY4WeEN8hZ3\n\tO6aoZqic9q4/Cs/na+mzIk8iEpKUXqANSjnvb+bW9WfEROoqlKoqZXxMU3+ogRHd\n\tYF+PuHBzAo7og/8peLU9v+n47IsuPZ5cofCQVrz6v6DCF92Sm4v8H1JqviALZk8z\n\tapIRZD6mfKeSD/NsR0+l05gkuTmhO04oaRbcSM8N9jd+3ghlt+aM50MZ9+s8VOrT\n\tS/q4CU1eFcz0SQx0yuyiS/0tmVrbDEPQYRnGq93nsvQbfCJGjp6KOeurppHzw/G3\n\tRctHQ9PmZGR65CIlFmq2bjNKM4dA+wVDxG75mnPAm7VziG6ACFUO7FZjTww==" ], "From": "Anup Patel <anup.patel@oss.qualcomm.com>", "To": "Atish Patra <atish.patra@linux.dev>", "Cc": "Andrew Jones <andrew.jones@oss.qualcomm.com>,\n Raymond Mao <raymond.mao@riscstar.com>,\n Dave Patel <dave.patel@riscstar.com>,\n Evgeny Voevodin <evvoevod@tenstorrent.com>,\n Samuel Holland <samuel.holland@sifive.com>,\n Anup Patel <anup@brainfault.org>, opensbi@lists.infradead.org,\n Anup Patel <anup.patel@oss.qualcomm.com>", "Subject": "[PATCH 4/6] lib: sbi_irqchip: Allow marking hardware interrupts as\n reserved", "Date": "Thu, 23 Apr 2026 10:53:37 +0530", "Message-ID": "<20260423052339.356900-5-anup.patel@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260423052339.356900-1-anup.patel@oss.qualcomm.com>", "References": "<20260423052339.356900-1-anup.patel@oss.qualcomm.com>", "MIME-Version": "1.0", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-ORIG-GUID": "UMpJvOX3s6I2AXHaAxZjUZku1oXa42AQ", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDA0NyBTYWx0ZWRfX5FqOwtbPtk6f\n rJpVdcCs93YN4o1xCiO0gYyR3R28tC2PDb46hdJnLsl0scjB59ZjBE/ERRPNk6CUFPdIpNfoENE\n yQEIilQtSAYHAvSWW88PH5O5gJo+a002C9CECIBfPFVpysk2cCairtmJzAb1KeKS2u5fT8dAia3\n S2i7osZyUAXAF3cmljPO6b+UBXMYwuY4WakkvSQuBrW37Kl20qFoDHx1DqPAFeF0vW2zSnwA88Q\n Pu5/NtXplkZIu6rwmoSxuGpnNmR3SE0f/wKlH7I+e9p9mcUfIcUS4MQ3fn+PRKfqR9BlKZLvvDp\n 50VTmPP6mBNzw8X4hI/cWppyjLp+i6+JXgelAjqgr3QLzsPJ4Buz6Bfr4VbnYLzOiyR33wBiU3b\n upVmOhWTtJmHqCX2Tkj0AixoCp0dbrDeAEivM87j1RDbZI+H04smTvYiZX83LwSjxEZeFXLV5Q6\n 8/XeQG/NHKMM4WDcd4w==", "X-Authority-Analysis": "v=2.4 cv=PsOjqQM3 c=1 sm=1 tr=0 ts=69e9ace1 cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22\n a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=dnB8MZ6qHW_oZ28M05AA:9", "X-Proofpoint-GUID": "UMpJvOX3s6I2AXHaAxZjUZku1oXa42AQ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_01,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0\n priorityscore=1501 impostorscore=0 clxscore=1011 bulkscore=0 malwarescore=0\n spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604230047", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260422_222359_228478_94C484DD ", "X-CRM114-Status": "GOOD ( 12.69 )", "X-Spam-Score": "-2.7 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Some of the hardware interrupts may be special so allow\n irqchip\n drivers to make these hardware interrupts as reserved. Introduce\n sbi_irqchip_register_reserved()\n for this purpose. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com>\n --- include/sbi/sbi_irqchip.h | 6 +++++- lib/sbi/sbi_irqchip.c | 44\n +++++++++++++++++++++++++++++\n lib/utils/irqchip/imsic.c | 7 ++++++ [...]\n Content analysis details: (-2.7 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low\n trust\n [205.220.168.131 listed in list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Some of the hardware interrupts may be special so allow irqchip\ndrivers to make these hardware interrupts as reserved. Introduce\nsbi_irqchip_register_reserved() for this purpose.\n\nSigned-off-by: Anup Patel <anup.patel@oss.qualcomm.com>\n---\n include/sbi/sbi_irqchip.h | 6 +++++-\n lib/sbi/sbi_irqchip.c | 44 +++++++++++++++++++++++++++++----------\n lib/utils/irqchip/imsic.c | 7 ++++++-\n 3 files changed, 44 insertions(+), 13 deletions(-)", "diff": "diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h\nindex 9035dcef..880ff49f 100644\n--- a/include/sbi/sbi_irqchip.h\n+++ b/include/sbi/sbi_irqchip.h\n@@ -101,7 +101,11 @@ int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,\n /** Register a hardware interrupt handler */\n int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\n-\t\t\t\t int (*callback)(u32 hwirq, void *opaque), void *opaque);\n+\t\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv);\n+\n+/** Register a hardware interrupts as reserved */\n+int sbi_irqchip_register_reserved(struct sbi_irqchip_device *chip,\n+\t\t\t\t u32 first_hwirq, u32 num_hwirq);\n \n /** Unregister a hardware interrupt handler */\n int sbi_irqchip_unregister_handler(struct sbi_irqchip_device *chip,\ndiff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c\nindex ea684303..15ea2211 100644\n--- a/lib/sbi/sbi_irqchip.c\n+++ b/lib/sbi/sbi_irqchip.c\n@@ -108,13 +108,14 @@ static struct sbi_irqchip_handler *sbi_irqchip_find_handler(struct sbi_irqchip_d\n int sbi_irqchip_raw_handler_default(struct sbi_irqchip_device *chip, u32 hwirq)\n {\n \tstruct sbi_irqchip_handler *h;\n-\tint rc;\n+\tint rc = SBI_OK;\n \n \tif (!chip || chip->num_hwirq <= hwirq)\n \t\treturn SBI_EINVAL;\n \n \th = sbi_irqchip_find_handler(chip, hwirq);\n-\trc = h->callback(hwirq, h->priv);\n+\tif (h->callback)\n+\t\trc = h->callback(hwirq, h->priv);\n \n \tif (chip->hwirq_eoi)\n \t\tchip->hwirq_eoi(chip, hwirq);\n@@ -135,20 +136,14 @@ int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,\n \treturn 0;\n }\n \n-int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n-\t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\n-\t\t\t\t int (*callback)(u32 hwirq, void *opaque), void *priv)\n+static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n+\t\t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\n+\t\t\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv)\n {\n \tstruct sbi_irqchip_handler *h, *th, *nh;\n \tu32 i, j;\n \tint rc;\n \n-\tif (!chip || !num_hwirq || !callback)\n-\t\treturn SBI_EINVAL;\n-\tif (chip->num_hwirq <= first_hwirq ||\n-\t chip->num_hwirq <= (first_hwirq + num_hwirq - 1))\n-\t\treturn SBI_EBAD_RANGE;\n-\n \tfor (i = first_hwirq; i < (first_hwirq + num_hwirq); i++) {\n \t\th = sbi_irqchip_find_handler(chip, i);\n \t\tif (h)\n@@ -198,6 +193,33 @@ int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \treturn 0;\n }\n \n+int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n+\t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\n+\t\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv)\n+{\n+\tif (!chip || !num_hwirq || !callback)\n+\t\treturn SBI_EINVAL;\n+\tif (chip->num_hwirq <= first_hwirq ||\n+\t chip->num_hwirq <= (first_hwirq + num_hwirq - 1))\n+\t\treturn SBI_EBAD_RANGE;\n+\n+\treturn __sbi_irqchip_register_handler(chip, first_hwirq, num_hwirq, hwirq_flags,\n+\t\t\t\t\t callback, priv);\n+}\n+\n+int sbi_irqchip_register_reserved(struct sbi_irqchip_device *chip,\n+\t\t\t\t u32 first_hwirq, u32 num_hwirq)\n+{\n+\tif (!chip || !num_hwirq)\n+\t\treturn SBI_EINVAL;\n+\tif (chip->num_hwirq <= first_hwirq ||\n+\t chip->num_hwirq <= (first_hwirq + num_hwirq - 1))\n+\t\treturn SBI_EBAD_RANGE;\n+\n+\treturn __sbi_irqchip_register_handler(chip, first_hwirq, num_hwirq,\n+\t\t\t\t\t SBI_HWIRQ_FLAGS_NONE, NULL, NULL);\n+}\n+\n int sbi_irqchip_unregister_handler(struct sbi_irqchip_device *chip,\n \t\t\t\t u32 first_hwirq, u32 num_hwirq)\n {\ndiff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c\nindex 877255f8..521d17fe 100644\n--- a/lib/utils/irqchip/imsic.c\n+++ b/lib/utils/irqchip/imsic.c\n@@ -348,7 +348,7 @@ int imsic_data_check(struct imsic_data *imsic)\n \n static int imsic_hwirq_setup(struct sbi_irqchip_device *chip, u32 hwirq, u32 hwirq_flags)\n {\n-\tif (!hwirq || hwirq == IMSIC_IPI_ID || hwirq_flags != SBI_HWIRQ_FLAGS_NONE)\n+\tif (hwirq_flags != SBI_HWIRQ_FLAGS_NONE)\n \t\treturn SBI_ENOTSUPP;\n \treturn 0;\n }\n@@ -406,6 +406,11 @@ int imsic_cold_irqchip_init(struct imsic_data *imsic)\n \tif (rc)\n \t\treturn rc;\n \n+\t/* Mark hwirq 0 and IPI hwirq as reserved */\n+\trc = sbi_irqchip_register_reserved(&imsic_device, 0, IMSIC_IPI_ID + 1);\n+\tif (rc)\n+\t\treturn rc;\n+\n \t/* Register IPI device */\n \tsbi_ipi_add_device(&imsic_ipi_device);\n \n", "prefixes": [ "4/6" ] }