Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2227056/?format=api
{ "id": 2227056, "url": "http://patchwork.ozlabs.org/api/patches/2227056/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260423052339.356900-6-anup.patel@oss.qualcomm.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260423052339.356900-6-anup.patel@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T05:23:38", "name": "[5/6] lib: sbi_irqchip: Allow setting hardware interrupt affinity", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e6634d428179595189a28e8ead6d50428acde985", "submitter": { "id": 92322, "url": "http://patchwork.ozlabs.org/api/people/92322/?format=api", "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260423052339.356900-6-anup.patel@oss.qualcomm.com/mbox/", "series": [ { "id": 501146, "url": "http://patchwork.ozlabs.org/api/series/501146/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=501146", "date": "2026-04-23T05:23:35", "name": "Extend irqchip framework for MSIs and line sensing", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501146/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227056/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227056/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=DyiiiKQe;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=MytU0r2J;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Pf30Bn1z1yJ6\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 15:24:10 +1000 (AEST)", "from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wFmXk-0000000B3mZ-0cw8;\n\tThu, 23 Apr 2026 05:24:04 +0000", "from mx0a-0031df01.pphosted.com ([205.220.168.131])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wFmXh-0000000B3lR-3KYY\n\tfor opensbi@lists.infradead.org;\n\tThu, 23 Apr 2026 05:24:02 +0000", "from pps.filterd (m0279862.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63N3Yacv3173021;\n\tThu, 23 Apr 2026 05:23:46 GMT", "from apblrppmta01.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dq1m3283k-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 23 Apr 2026 05:23:46 +0000 (GMT)", "from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1])\n\tby APBLRPPMTA01.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id\n 63N5Ngt6007157;\n\tThu, 23 Apr 2026 05:23:43 GMT", "from pps.reinject (localhost [127.0.0.1])\n\tby APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4dm31jyv28-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 23 Apr 2026 05:23:43 +0000 (GMT)", "from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com\n [127.0.0.1])\n\tby pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 63N5NgZc007163;\n\tThu, 23 Apr 2026 05:23:42 GMT", "from hu-devc-blr-u24-a.qualcomm.com (hu-anuppate-blr.qualcomm.com\n [10.131.36.165])\n\tby APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 63N5Ngbb007162\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 23 Apr 2026 05:23:42 +0000 (GMT)", "by hu-devc-blr-u24-a.qualcomm.com (Postfix, from userid 486687)\n\tid 0945722A5B; Thu, 23 Apr 2026 10:53:41 +0530 (+0530)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=HrIjERNyUpf90tDO7h09T9TJR1UIBZzhUmTkFMcHNJo=; b=DyiiiKQeo0VA96\n\tEwk5pW2RdH52NVtxybyj0/nHR9ZRMdozsL1Zy6GuNjfKMFc7xOg9PS5Ua5V9kGJpkuHqtbzg81H/C\n\tbWYcuc1WrHHnqN7EmK0d6XbkpOtkY08e8Ne4Y907lLxCQidtQbt3HJOX73owo9H/iV1bUYpZLbbuR\n\tcZkUdPeOR/hw5DH0tFQD7idGfg2Q1EXgPdiMydtw7mKmwXr0fcOWe1RGOCk0JpW3OIqA7D/YhnPV3\n\t1GRVL4U0aMePJ7Wz4v10AqP4F+aBqGCTgS/m6murONrA1DUvsA7CszpdkqD9+yTFVY4vhM2/KS6TW\n\tOkNH+ck9dxuZuewkb4xg==;", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:date:from:in-reply-to:message-id\n\t:mime-version:references:subject:to; s=qcppdkim1; bh=PJenAc+eY6C\n\t5c7HGE2yCoN9GUNdnZ7lYojmVzwKhVUc=; b=MytU0r2JMO4PW+QPmpPxN0PT+6N\n\t4QlLXMamCKQjGhFmoKRxDv/83rtK7+4V3BaY+lLEs9cKdYgIZsMDp414UFUnurmg\n\t+YEEnxtlypTrPqim0EZuQ2YZ/+YAbVagAsUJSS5549JBRZmDcxEN0paEIkl9ij6J\n\tJ0okIY7T5qYsooM+dsFbISzQZhBoDlaualAoinydlQOPaf9tsVpYKAdMJJCshhhO\n\tqqBRpXHK1EWgcTbJeGFYgMupDDLq6zMU6QtVtRSP7mMqqHMQR8NQMWh/pmr276AZ\n\tw6SwOS5ijj71LAnpr+hZpyztq44lqkrO2oLUn9nx8Lg2tijsVkYf/8Qd6Hg==" ], "From": "Anup Patel <anup.patel@oss.qualcomm.com>", "To": "Atish Patra <atish.patra@linux.dev>", "Cc": "Andrew Jones <andrew.jones@oss.qualcomm.com>,\n Raymond Mao <raymond.mao@riscstar.com>,\n Dave Patel <dave.patel@riscstar.com>,\n Evgeny Voevodin <evvoevod@tenstorrent.com>,\n Samuel Holland <samuel.holland@sifive.com>,\n Anup Patel <anup@brainfault.org>, opensbi@lists.infradead.org,\n Anup Patel <anup.patel@oss.qualcomm.com>", "Subject": "[PATCH 5/6] lib: sbi_irqchip: Allow setting hardware interrupt\n affinity", "Date": "Thu, 23 Apr 2026 10:53:38 +0530", "Message-ID": "<20260423052339.356900-6-anup.patel@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260423052339.356900-1-anup.patel@oss.qualcomm.com>", "References": "<20260423052339.356900-1-anup.patel@oss.qualcomm.com>", "MIME-Version": "1.0", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-ORIG-GUID": "YrIIXbpHos8L2Sv8bGLVly8pzNSZmBsh", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDA0NyBTYWx0ZWRfX/4j8y0+G/fik\n whpVd00bz7POQOCqwu9F95hWa4F4GwwYWAWpkjjyjm7KGyc+tZy8gJwV8E1fOncxl03WAvpfCp1\n 2sDWZBPlzWWmckPfviM5RZz1lZ7rYf9STbZDhMZxkIa6jK7u7wtMy2anQkdCRBXGrV4U/m129EE\n O9BNt+xVR7/zMODZW/z9svKOk3joPho2bOZqG/+rbTty31z+UUmEqzp1OqPEU+qrKNbexKPjLGK\n i6XMUU5vQ+qsMRb3kIdfvxNyoNbg6r01e509QHmfd4k3oDPfgtPrA66pnRkwVsSGWphhPieBijq\n 6ZNfrKB1aRpSv6Bj4iLiOQME6K2wSzIwxMjN3sNEgF7DHFrYZ62SGLSjHjDrzGg/yazrCTbkjDj\n p4c93MhLKFk1Lw4Dn51sF0UFx+Q3A+sAnYKTYuyyMsw9o0qB2O/AykZ+0RVWoPC+LTeOOuNREDC\n EHSKO47DlW5PO7WwkMw==", "X-Authority-Analysis": "v=2.4 cv=PsOjqQM3 c=1 sm=1 tr=0 ts=69e9ace2 cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22\n a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=bDdBU3oEAAAA:8\n a=DUg25WrKxpq9Pd_k14kA:9 a=DN7SgORnOiO7RqxRx1GC:22", "X-Proofpoint-GUID": "YrIIXbpHos8L2Sv8bGLVly8pzNSZmBsh", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_01,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0\n priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 malwarescore=0\n spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604230047", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260422_222401_837405_D4FD9B77 ", "X-CRM114-Status": "GOOD ( 19.86 )", "X-Spam-Score": "-2.7 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: The irqchip drivers can provide mechanism to set interrupt\n affinity so add hwirq_set_affinity() callback for irqchip drivers and use\n it to implement sbi_irqchip_set_affinity() which can be used by oth [...] \n Content analysis details: (-2.7 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low\n trust\n [205.220.168.131 listed in list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "The irqchip drivers can provide mechanism to set interrupt affinity\nso add hwirq_set_affinity() callback for irqchip drivers and use it\nto implement sbi_irqchip_set_affinity() which can be used by other\ndrivers.\n\nSigned-off-by: Anup Patel <anup.patel@oss.qualcomm.com>\n---\n include/sbi/sbi_irqchip.h | 11 ++++\n lib/sbi/sbi_irqchip.c | 123 +++++++++++++++++++++++++++++++++++++-\n 2 files changed, 133 insertions(+), 1 deletion(-)", "diff": "diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h\nindex 880ff49f..03a01038 100644\n--- a/include/sbi/sbi_irqchip.h\n+++ b/include/sbi/sbi_irqchip.h\n@@ -60,6 +60,10 @@ struct sbi_irqchip_device {\n \t/** End of hardware interrupt of this irqchip */\n \tvoid (*hwirq_eoi)(struct sbi_irqchip_device *chip, u32 hwirq);\n \n+\t/** Set hardware interrupt affinity */\n+\tint (*hwirq_set_affinity)(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t\t u32 hart_index);\n+\n \t/** Mask a hardware interrupt of this irqchip */\n \tvoid (*hwirq_mask)(struct sbi_irqchip_device *chip, u32 hwirq);\n \n@@ -98,6 +102,13 @@ int sbi_irqchip_raw_handler_default(struct sbi_irqchip_device *chip, u32 hwirq);\n int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,\n \t\t\t\tint (*raw_hndl)(struct sbi_irqchip_device *, u32));\n \n+/** Get hardware interrupt affinity */\n+int sbi_irqchip_get_affinity(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t u32 *out_hart_index);\n+\n+/** Set hardware interrupt affinity */\n+int sbi_irqchip_set_affinity(struct sbi_irqchip_device *chip, u32 hwirq, u32 hart_index);\n+\n /** Register a hardware interrupt handler */\n int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\ndiff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c\nindex 15ea2211..386dfd87 100644\n--- a/lib/sbi/sbi_irqchip.c\n+++ b/lib/sbi/sbi_irqchip.c\n@@ -7,7 +7,9 @@\n * Anup Patel <apatel@ventanamicro.com>\n */\n \n+#include <sbi/sbi_console.h>\n #include <sbi/sbi_heap.h>\n+#include <sbi/sbi_hsm.h>\n #include <sbi/sbi_irqchip.h>\n #include <sbi/sbi_list.h>\n #include <sbi/sbi_platform.h>\n@@ -17,6 +19,9 @@\n struct sbi_irqchip_hwirq_data {\n \t/** raw hardware interrupt handler */\n \tint (*raw_handler)(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+\t/** target hart index */\n+\tu32 hart_index;\n };\n \n /** Internal irqchip interrupt handler */\n@@ -136,6 +141,78 @@ int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,\n \treturn 0;\n }\n \n+int sbi_irqchip_get_affinity(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t u32 *out_hart_index)\n+{\n+\tif (!chip || chip->num_hwirq <= hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\t/*\n+\t * If no handler registered for hwirq then hwirq\n+\t * is not being used so return failure\n+\t */\n+\tif (!sbi_irqchip_find_handler(chip, hwirq))\n+\t\treturn SBI_ENOTSUPP;\n+\n+\t*out_hart_index = chip->hwirqs[hwirq].hart_index;\n+\treturn 0;\n+}\n+\n+int sbi_irqchip_set_affinity(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t u32 hart_index)\n+{\n+\tstruct sbi_irqchip_hwirq_data *data;\n+\tint rc;\n+\n+\tif (!chip || chip->num_hwirq <= hwirq || sbi_hart_count() <= hart_index)\n+\t\treturn SBI_EINVAL;\n+\n+\t/*\n+\t * If no handler registered for hwirq then hwirq\n+\t * is not being used so return failure\n+\t */\n+\tif (!sbi_irqchip_find_handler(chip, hwirq))\n+\t\treturn SBI_ENOTSUPP;\n+\n+\tdata = &chip->hwirqs[hwirq];\n+\tif (data->hart_index != hart_index) {\n+\t\tif (chip->hwirq_set_affinity) {\n+\t\t\trc = chip->hwirq_set_affinity(chip, hwirq, hart_index);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\t\tdata->hart_index = hart_index;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int __sbi_irqchip_handler_set_affinity(struct sbi_irqchip_device *chip,\n+\t\t\t\t\t struct sbi_irqchip_handler *h,\n+\t\t\t\t\t u32 compare_hart_index,\n+\t\t\t\t\t u32 hart_index)\n+{\n+\tu32 i, current_hart_index;\n+\tint rc;\n+\n+\tfor (i = 0; i < h->num_hwirq; i++) {\n+\t\trc = sbi_irqchip_get_affinity(chip, h->first_hwirq + i,\n+\t\t\t\t\t ¤t_hart_index);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tif (compare_hart_index != -1U &&\n+\t\t current_hart_index != compare_hart_index)\n+\t\t\tcontinue;\n+\n+\t\trc = sbi_irqchip_set_affinity(chip, h->first_hwirq + i, hart_index);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\n \t\t\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv)\n@@ -185,6 +262,17 @@ static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\t}\n \t}\n \n+\trc = __sbi_irqchip_handler_set_affinity(chip, h, -1U, current_hartindex());\n+\tif (rc) {\n+\t\tif (chip->hwirq_cleanup) {\n+\t\t\tfor (i = 0; i < h->num_hwirq; i++)\n+\t\t\t\tchip->hwirq_cleanup(chip, h->first_hwirq + i);\n+\t\t}\n+\t\tsbi_list_del(&h->node);\n+\t\tsbi_free(h);\n+\t\treturn rc;\n+\t}\n+\n \tif (chip->hwirq_unmask) {\n \t\tfor (i = 0; i < h->num_hwirq; i++)\n \t\t\tchip->hwirq_unmask(chip, h->first_hwirq + i);\n@@ -294,8 +382,10 @@ int sbi_irqchip_add_device(struct sbi_irqchip_device *chip)\n \tchip->hwirqs = sbi_zalloc(sizeof(*chip->hwirqs) * chip->num_hwirq);\n \tif (!chip->hwirqs)\n \t\treturn SBI_ENOMEM;\n-\tfor (i = 0; i < chip->num_hwirq; i++)\n+\tfor (i = 0; i < chip->num_hwirq; i++) {\n \t\tsbi_irqchip_set_raw_handler(chip, i, sbi_irqchip_raw_handler_default);\n+\t\tchip->hwirqs[i].hart_index = -1U;\n+\t}\n \n \tSBI_INIT_LIST_HEAD(&chip->handler_list);\n \n@@ -340,6 +430,37 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)\n void sbi_irqchip_exit(struct sbi_scratch *scratch)\n {\n \tstruct sbi_irqchip_hart_data *hd;\n+\tstruct sbi_irqchip_device *chip;\n+\tstruct sbi_irqchip_handler *h;\n+\tu32 migrate_hidx = -1U;\n+\tbool migrate = false;\n+\tint rc;\n+\n+\tsbi_for_each_hartindex(i) {\n+\t\tif (i == current_hartindex())\n+\t\t\tcontinue;\n+\t\tif (__sbi_hsm_hart_get_state(i) == SBI_HSM_STATE_STOPPED ||\n+\t\t __sbi_hsm_hart_get_state(i) == SBI_HSM_STATE_STOP_PENDING)\n+\t\t\tcontinue;\n+\t\tmigrate_hidx = i;\n+\t\tmigrate = true;\n+\t\tbreak;\n+\t}\n+\n+\tif (!migrate)\n+\t\tgoto skip_migrate;\n+\tsbi_list_for_each_entry(chip, &irqchip_list, node) {\n+\t\tsbi_list_for_each_entry(h, &chip->handler_list, node) {\n+\t\t\trc = __sbi_irqchip_handler_set_affinity(chip, h,\n+\t\t\t\t\t\t\t\tcurrent_hartindex(),\n+\t\t\t\t\t\t\t\tmigrate_hidx);\n+\t\t\tif (rc) {\n+\t\t\t\tsbi_printf(\"%s: chip 0x%x handler 0x%x set affinity (err %d)\\n\",\n+\t\t\t\t\t __func__, chip->id, h->first_hwirq, rc);\n+\t\t\t}\n+\t\t}\n+\t}\n+skip_migrate:\n \n \thd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);\n \tif (hd && hd->chip && hd->chip->process_hwirqs)\n", "prefixes": [ "5/6" ] }