Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2226935/?format=api
{ "id": 2226935, "url": "http://patchwork.ozlabs.org/api/patches/2226935/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-4-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422214225.2242-4-mohamed@unpredictable.fr>", "list_archive_url": null, "date": "2026-04-22T21:41:51", "name": "[v3,03/37] whpx: i386: wire up feature probing", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e2e65eecd63039d953ad73f14a8bf27ac1e93142", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-4-mohamed@unpredictable.fr/mbox/", "series": [ { "id": 501116, "url": "http://patchwork.ozlabs.org/api/series/501116/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501116", "date": "2026-04-22T21:41:48", "name": "[v3,01/37] target/i386: emulate: include name of unhandled instruction", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501116/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226935/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226935/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=cYT/Cn2a;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1CTm3y7Kz1yD5\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 07:46:20 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFfLK-0007tM-9a; Wed, 22 Apr 2026 17:42:46 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wFfLI-0007sn-8p\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:42:44 -0400", "from p-east2-cluster1-host2-snip4-4.eps.apple.com ([57.103.76.37]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wFfLF-0006wp-7q\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:42:43 -0400", "from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n 7E86E1800951; Wed, 22 Apr 2026 21:42:36 +0000 (UTC)", "from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n D074418006EB; Wed, 22 Apr 2026 21:42:33 +0000 (UTC)" ], "X-ICL-Out-Info": "\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJAU1fDl4fBBdGGVUERx5dVkAZGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCC0oCWQVZB14LSgdfGl8fHVYQUgBSD3IFVwhBCFMCUQRYGl8IGQ1AThkMSh1SVlEFSgxcAGgPXR1YEV0=", "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776894160; x=1779486160;\n bh=IeLwDiWpTVXNjCjqgANs/S5+IQILH2QyjipMpqv8C+Y=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=cYT/Cn2aYPmMCxi2xzJj+7HDU+h1h5mjj2u4I+Pmv80cGHYghEhRRtNdzrZu1kAN9ZoXnE2yIrUqFcsHWm4FAcxlVuj7HraDiHicpOigeXtgB2kR8qGiRzHoN3b5hl1VMR3GF1NCiNThYmKcbkADAVkrByqvrGfkg9TvJnC24NIJ9H6UAvKws8vaHMhjuJLgNxP0s5HslhmUDd0WDzi6t5csRCrXMr4uI7jd/5KfC+n7S9KrU3Kci9Dh3tQYRijlKCF6qX+uTPXWS63TBH4xWNZu1Ri1Gndb5W0JdeQc2Kniyrk2/HODZP/7WjaObRpm96S0jQsF6txIpC2UGEv1rQ==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "Pedro Barbuda <pbarbuda@microsoft.com>, qemu-arm@nongnu.org,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Mohamed Mediouni <mohamed@unpredictable.fr>,\n Roman Bolshakov <rbolshakov@ddn.com>,\n \"Michael S. Tsirkin\" <mst@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Phil Dennis-Jordan <phil@philjordan.eu>,\n Peter Maydell <peter.maydell@linaro.org>, Zhao Liu <zhao1.liu@intel.com>,\n Paolo Bonzini <pbonzini@redhat.com>", "Subject": "[PATCH v3 03/37] whpx: i386: wire up feature probing", "Date": "Wed, 22 Apr 2026 23:41:51 +0200", "Message-ID": "<20260422214225.2242-4-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260422214225.2242-1-mohamed@unpredictable.fr>", "References": "<20260422214225.2242-1-mohamed@unpredictable.fr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "bGkY5p5kwID_cDFf8wnwCNpgda7jZX8w", "X-Proofpoint-ORIG-GUID": "bGkY5p5kwID_cDFf8wnwCNpgda7jZX8w", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIyMDIxMSBTYWx0ZWRfX2G1pS9R0xnua\n dJ1Iq8BlHu25mfbpVpoaXdkoEIDKOdiX+Fq/RlrW9fm1ZkM6L+UH4N6tt+XrTBTYMwSCqeVpJQR\n mbhRFS78Y3dgX8P+lrhxCDuZmBWsSUwR5SQB+MYUfRH71wvG/NcU0PDpCbOJs03yYbNwcLLHOxQ\n L8AhSe1NghE6NF65+GdArppZO6DGJoKeasdEBfLlBoLI+cyZD28547k/hpTDFKeR8PPUYqnkUTR\n HTIAOmtpif3hoG/juihay5w2K76IvXGd4BqNwK8zMvM2rge16WoWo0g6eVynot+jpoO6zsViAr9\n 6NS/W6w41/hSJFcHUEI8SWZLb6EIOQvZIeVjH8jsPmchezSG5joh94ygEt7lFM=", "X-Authority-Info-Out": "v=2.4 cv=b7e/I9Gx c=1 sm=1 tr=0 ts=69e940ce\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=mDV3o1hIAAAA:8 a=E2jrspqCZx2CoTvb7ogA:9", "Received-SPF": "pass client-ip=57.103.76.37;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Windows 10 doesn't have the API for this, so using this\nonly for Windows 11.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n include/system/whpx-internal.h | 9 ++\n target/i386/cpu.c | 17 +++\n target/i386/whpx/meson.build | 1 +\n target/i386/whpx/whpx-all.c | 165 +++++++++++++++++++++++++++-\n target/i386/whpx/whpx-cpu-legacy.c | 171 +++++++++++++++++++++++++++++\n target/i386/whpx/whpx-i386.h | 12 ++\n 6 files changed, 370 insertions(+), 5 deletions(-)\n create mode 100644 target/i386/whpx/whpx-cpu-legacy.c\n create mode 100644 target/i386/whpx/whpx-i386.h", "diff": "diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h\nindex 8482901f71..5902124b63 100644\n--- a/include/system/whpx-internal.h\n+++ b/include/system/whpx-internal.h\n@@ -73,6 +73,14 @@ void whpx_apic_get(APICCommonState *s);\n X(HRESULT, WHvGetVirtualProcessorRegisters, (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, const WHV_REGISTER_NAME* RegisterNames, UINT32 RegisterCount, WHV_REGISTER_VALUE* RegisterValues)) \\\n X(HRESULT, WHvSetVirtualProcessorRegisters, (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, const WHV_REGISTER_NAME* RegisterNames, UINT32 RegisterCount, const WHV_REGISTER_VALUE* RegisterValues)) \\\n \n+#ifdef __x86_64__\n+#define LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL_ARCH(X) \\\n+ X(HRESULT, WHvGetVirtualProcessorCpuidOutput, \\\n+ (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, UINT32 Eax, \\\n+ UINT32 Ecx, WHV_CPUID_OUTPUT *CpuidOutput))\n+#else\n+#define LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL_ARCH(X)\n+#endif\n /*\n * These are supplemental functions that may not be present\n * on all versions and are not critical for basic functionality.\n@@ -89,6 +97,7 @@ void whpx_apic_get(APICCommonState *s);\n UINT32 StateSize)) \\\n X(HRESULT, WHvResetPartition, \\\n (WHV_PARTITION_HANDLE Partition)) \\\n+ LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL_ARCH(X)\n \n #define WHP_DEFINE_TYPE(return_type, function_name, signature) \\\n typedef return_type (WINAPI *function_name ## _t) signature;\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex c6fd1dc00e..a5f1a1a8fd 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -26,6 +26,8 @@\n #include \"tcg/helper-tcg.h\"\n #include \"exec/translation-block.h\"\n #include \"system/hvf.h\"\n+#include \"system/whpx.h\"\n+#include \"whpx/whpx-i386.h\"\n #include \"hvf/hvf-i386.h\"\n #include \"kvm/kvm_i386.h\"\n #include \"kvm/tdx.h\"\n@@ -8087,6 +8089,16 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w)\n r = hvf_get_supported_cpuid(wi->cpuid.eax,\n wi->cpuid.ecx,\n wi->cpuid.reg);\n+ } else if (whpx_enabled()) {\n+ switch (wi->type) {\n+ case CPUID_FEATURE_WORD:\n+ r = whpx_get_supported_cpuid(wi->cpuid.eax, wi->cpuid.ecx,\n+ wi->cpuid.reg);\n+ break;\n+ case MSR_FEATURE_WORD:\n+ r = whpx_get_supported_msr_feature(wi->msr.index);\n+ break;\n+ }\n } else if (tcg_enabled() || qtest_enabled()) {\n r = wi->tcg_features;\n } else {\n@@ -8168,6 +8180,11 @@ static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,\n *ebx = hvf_get_supported_cpuid(func, index, R_EBX);\n *ecx = hvf_get_supported_cpuid(func, index, R_ECX);\n *edx = hvf_get_supported_cpuid(func, index, R_EDX);\n+ } else if (whpx_enabled()) {\n+ *eax = whpx_get_supported_cpuid(func, index, R_EAX);\n+ *ebx = whpx_get_supported_cpuid(func, index, R_EBX);\n+ *ecx = whpx_get_supported_cpuid(func, index, R_ECX);\n+ *edx = whpx_get_supported_cpuid(func, index, R_EDX);\n } else {\n *eax = 0;\n *ebx = 0;\ndiff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build\nindex c3aaaff9fd..1c6a4ce377 100644\n--- a/target/i386/whpx/meson.build\n+++ b/target/i386/whpx/meson.build\n@@ -1,4 +1,5 @@\n i386_system_ss.add(when: 'CONFIG_WHPX', if_true: files(\n 'whpx-all.c',\n 'whpx-apic.c',\n+ 'whpx-cpu-legacy.c'\n ))\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 4127440c0c..d211b3f2ef 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -36,6 +36,7 @@\n #include \"system/whpx-accel-ops.h\"\n #include \"system/whpx-all.h\"\n #include \"system/whpx-common.h\"\n+#include \"whpx-i386.h\"\n \n #include \"emulate/x86_decode.h\"\n #include \"emulate/x86_emu.h\"\n@@ -49,6 +50,8 @@\n /* for kernel-irqchip=off */\n #define HV_X64_MSR_APIC_FREQUENCY 0x40000023\n \n+static bool is_modern_os = true;\n+\n static const WHV_REGISTER_NAME whpx_register_names[] = {\n \n /* X64 General purpose registers */\n@@ -265,11 +268,30 @@ typedef enum WhpxStepMode {\n static uint32_t max_vcpu_index;\n static WHV_PROCESSOR_XSAVE_FEATURES whpx_xsave_cap;\n \n-static bool whpx_has_xsave(void)\n+bool whpx_has_xsave(void)\n {\n return whpx_xsave_cap.XsaveSupport;\n }\n \n+bool whpx_has_xsaves(void)\n+{\n+ return whpx_xsave_cap.XsaveSupervisorSupport;\n+}\n+\n+static bool whpx_rdtsc_cap;\n+\n+bool whpx_has_rdtscp(void)\n+{\n+ return whpx_rdtsc_cap;\n+}\n+\n+static bool whpx_invpcid_cap;\n+\n+bool whpx_has_invpcid(void)\n+{\n+ return whpx_invpcid_cap;\n+}\n+\n static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v86,\n int r86)\n {\n@@ -1062,6 +1084,137 @@ static void whpx_init_emu(void)\n init_emu(&whpx_x86_emul_ops);\n }\n \n+bool whpx_is_legacy_os(void)\n+{\n+ return !is_modern_os;\n+}\n+\n+uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg)\n+{\n+ WHV_CPUID_OUTPUT output = {};\n+ uint32_t eax, ebx, ecx, edx;\n+ uint32_t cpu_index = 0;\n+ bool temp_cpu = true;\n+ HRESULT hr;\n+\n+ /* Legacy OSes don't have WHvGetVirtualProcessorCpuidOutput */\n+ if (whpx_is_legacy_os()) {\n+ return whpx_get_supported_cpuid_legacy(func, idx, reg);\n+ }\n+\n+ hr = whp_dispatch.WHvCreateVirtualProcessor(\n+ whpx_global.partition, cpu_index, 0);\n+\n+ /* This means that the CPU already exists... */\n+ if (FAILED(hr)) {\n+ temp_cpu = false;\n+ }\n+\n+ hr = whp_dispatch.WHvGetVirtualProcessorCpuidOutput(whpx_global.partition,\n+ cpu_index, func, idx, &output);\n+\n+ if (FAILED(hr)) {\n+ abort();\n+ }\n+\n+ if (temp_cpu) {\n+ hr = whp_dispatch.WHvDeleteVirtualProcessor(whpx_global.partition, cpu_index);\n+ if (FAILED(hr)) {\n+ abort();\n+ }\n+ }\n+\n+ eax = output.Eax;\n+ ebx = output.Ebx;\n+ ecx = output.Ecx;\n+ edx = output.Edx;\n+\n+ /*\n+ * We can emulate X2APIC even for the kernel-irqchip=off case.\n+ * CPUID_EXT_HYPERVISOR and CPUID_HT should be considered present\n+ * always, so report them as unconditionally supported here.\n+ */\n+ if (func == 1) {\n+ ecx |= CPUID_EXT_X2APIC;\n+ ecx |= CPUID_EXT_HYPERVISOR;\n+ edx |= CPUID_HT;\n+ }\n+\n+ switch (reg) {\n+ case R_EAX:\n+ return eax;\n+ case R_EBX:\n+ return ebx;\n+ case R_ECX:\n+ return ecx;\n+ case R_EDX:\n+ return edx;\n+ default:\n+ return 0;\n+ }\n+}\n+\n+uint64_t whpx_get_supported_msr_feature(uint32_t index)\n+{\n+ WHV_CAPABILITY_CODE cap;\n+ uint64_t val = 0;\n+\n+ switch (index) {\n+ case MSR_IA32_VMX_BASIC:\n+ cap = WHvCapabilityCodeVmxBasic;\n+ break;\n+ case MSR_IA32_VMX_MISC:\n+ cap = WHvCapabilityCodeVmxMisc;\n+ break;\n+ case MSR_IA32_VMX_CR0_FIXED0:\n+ cap = WHvCapabilityCodeVmxCr0Fixed0;\n+ break;\n+ case MSR_IA32_VMX_CR0_FIXED1:\n+ cap = WHvCapabilityCodeVmxCr0Fixed1;\n+ break;\n+ case MSR_IA32_VMX_CR4_FIXED0:\n+ cap = WHvCapabilityCodeVmxCr4Fixed0;\n+ break;\n+ case MSR_IA32_VMX_CR4_FIXED1:\n+ cap = WHvCapabilityCodeVmxCr4Fixed1;\n+ break;\n+ case MSR_IA32_VMX_VMCS_ENUM:\n+ cap = WHvCapabilityCodeVmxVmcsEnum;\n+ break;\n+ case MSR_IA32_VMX_PROCBASED_CTLS2:\n+ cap = WHvCapabilityCodeVmxProcbasedCtls2;\n+ break;\n+ case MSR_IA32_VMX_EPT_VPID_CAP:\n+ cap = WHvCapabilityCodeVmxEptVpidCap;\n+ break;\n+ case MSR_IA32_VMX_TRUE_PINBASED_CTLS:\n+ cap = WHvCapabilityCodeVmxPinbasedCtls;\n+ break;\n+ case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:\n+ cap = WHvCapabilityCodeVmxProcbasedCtls;\n+ break;\n+ case MSR_IA32_VMX_TRUE_ENTRY_CTLS:\n+ cap = WHvCapabilityCodeVmxTrueEntryCtls;\n+ break;\n+ case MSR_IA32_VMX_TRUE_EXIT_CTLS:\n+ cap = WHvCapabilityCodeVmxTrueExitCtls;\n+ break;\n+ default:\n+ cap = 0;\n+ }\n+\n+ if (cap != 0) {\n+ HRESULT hr = whp_dispatch.WHvGetCapability(\n+ cap, &val, sizeof(val),\n+ NULL);\n+ if (FAILED(hr)) {\n+ return 0;\n+ }\n+ return val;\n+ }\n+ return 0;\n+}\n+\n /*\n * Controls whether we should intercept various exceptions on the guest,\n * namely breakpoint/single-step events.\n@@ -2235,7 +2388,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n WHV_CAPABILITY_FEATURES features = {0};\n WHV_PROCESSOR_FEATURES_BANKS processor_features;\n WHV_PROCESSOR_PERFMON_FEATURES perfmon_features;\n- bool is_legacy_os = false;\n UINT32 cpuidExitList[] = {1};\n \n whpx = &whpx_global;\n@@ -2355,6 +2507,9 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n goto error;\n }\n \n+ whpx_rdtsc_cap = processor_features.Bank0.RdtscpSupport;\n+ whpx_invpcid_cap = processor_features.Bank0.InvpcidSupport;\n+\n if (whpx_irqchip_in_kernel() && processor_features.Bank1.NestedVirtSupport) {\n memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));\n prop.NestedVirtualization = 1;\n@@ -2395,7 +2550,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n if (FAILED(hr)) {\n warn_report(\"WHPX: Failed to get performance \"\n \"monitoring features, hr=%08lx\", hr);\n- is_legacy_os = true;\n+ is_modern_os = false;\n } else {\n hr = whp_dispatch.WHvSetPartitionProperty(\n whpx->partition,\n@@ -2435,7 +2590,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n synthetic_features.Bank0.DirectSyntheticTimers = 1;\n }\n \n- if (!is_legacy_os && whpx->hyperv_enlightenments_allowed) {\n+ if (is_modern_os && whpx->hyperv_enlightenments_allowed) {\n hr = whp_dispatch.WHvSetPartitionProperty(\n whpx->partition,\n WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks,\n@@ -2446,7 +2601,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n ret = -EINVAL;\n goto error;\n }\n- } else if (is_legacy_os && whpx->hyperv_enlightenments_required) {\n+ } else if (!is_modern_os && whpx->hyperv_enlightenments_required) {\n error_report(\"Hyper-V enlightenments not available on legacy Windows\");\n ret = -EINVAL;\n goto error;\ndiff --git a/target/i386/whpx/whpx-cpu-legacy.c b/target/i386/whpx/whpx-cpu-legacy.c\nnew file mode 100644\nindex 0000000000..477429b460\n--- /dev/null\n+++ b/target/i386/whpx/whpx-cpu-legacy.c\n@@ -0,0 +1,171 @@\n+/*\n+ * i386 CPUID helper functions\n+ *\n+ * Copyright (c) 2003 Fabrice Bellard\n+ * Copyright (c) 2017 Google Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU Lesser General Public\n+ * License as published by the Free Software Foundation; either\n+ * version 2.1 of the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ * Lesser General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU Lesser General Public\n+ * License along with this program; if not, see <http://www.gnu.org/licenses/>.\n+ *\n+ * cpuid\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/cpuid.h\"\n+#include \"host/cpuinfo.h\"\n+#include \"cpu.h\"\n+#include \"emulate/x86.h\"\n+#include \"whpx-i386.h\"\n+\n+static bool cached_xcr0;\n+static uint64_t supported_xcr0;\n+\n+static void cache_host_xcr0(void)\n+{\n+ if (cached_xcr0) {\n+ return;\n+ }\n+\n+ if (whpx_has_xsave()) {\n+ uint64_t host_xcr0 = xgetbv_low(0);\n+\n+ /* Only show xcr0 bits corresponding to usable features. */\n+ supported_xcr0 = host_xcr0 & (XSTATE_FP_MASK |\n+ XSTATE_SSE_MASK | XSTATE_YMM_MASK |\n+ XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK |\n+ XSTATE_Hi16_ZMM_MASK);\n+ if ((supported_xcr0 & (XSTATE_FP_MASK | XSTATE_SSE_MASK)) !=\n+ (XSTATE_FP_MASK | XSTATE_SSE_MASK)) {\n+ supported_xcr0 = 0;\n+ }\n+ }\n+\n+ cached_xcr0 = true;\n+}\n+\n+uint32_t whpx_get_supported_cpuid_legacy(uint32_t func, uint32_t idx,\n+ int reg)\n+{\n+ uint32_t eax, ebx, ecx, edx;\n+\n+ cache_host_xcr0();\n+ host_cpuid(func, idx, &eax, &ebx, &ecx, &edx);\n+\n+ switch (func) {\n+ case 0:\n+ eax = eax < (uint32_t)0xd ? eax : (uint32_t)0xd;\n+ break;\n+ case 1:\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |\n+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_HT;\n+ ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |\n+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |\n+ CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |\n+ CPUID_EXT_POPCNT | CPUID_EXT_AES |\n+ (supported_xcr0 ? CPUID_EXT_XSAVE : 0) |\n+ CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND;\n+ ecx |= CPUID_EXT_HYPERVISOR;\n+ ecx |= CPUID_EXT_X2APIC;\n+ edx |= CPUID_HT;\n+ break;\n+ case 6:\n+ eax = CPUID_6_EAX_ARAT;\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ break;\n+ case 7:\n+ if (idx == 0) {\n+ ebx &= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |\n+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |\n+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |\n+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_RTM |\n+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |\n+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |\n+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |\n+ CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |\n+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |\n+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |\n+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |\n+ CPUID_7_0_EBX_INVPCID;\n+\n+ if (!whpx_has_invpcid()) {\n+ ebx &= ~CPUID_7_0_EBX_INVPCID;\n+ }\n+\n+ ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ |\n+ CPUID_7_0_ECX_RDPID;\n+ edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;\n+ } else {\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ }\n+ eax = 0;\n+ break;\n+ case 0xD:\n+ if (!supported_xcr0 || idx >= 63 ||\n+ (idx > 1 && !(supported_xcr0 & (UINT64_C(1) << idx)))) {\n+ eax = ebx = ecx = edx = 0;\n+ break;\n+ }\n+\n+ if (idx == 0) {\n+ eax = supported_xcr0;\n+ } else if (idx == 1) {\n+ eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;\n+ if (!whpx_has_xsaves()) {\n+ eax &= ~CPUID_XSAVE_XSAVES;\n+ }\n+ }\n+ break;\n+ case 0x80000001:\n+ /* LM only if HVF in 64-bit mode */\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_EXT2_MMXEXT | CPUID_MMX |\n+ CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |\n+ CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;\n+ if (!(whpx_has_rdtscp())) {\n+ edx &= ~CPUID_EXT2_RDTSCP;\n+ }\n+ ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |\n+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE |\n+ CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP |\n+ CPUID_EXT3_FMA4 | CPUID_EXT3_TBM;\n+ break;\n+ case 0x80000007:\n+ edx &= CPUID_APM_INVTSC;\n+ eax = ebx = ecx = 0;\n+ break;\n+ default:\n+ return 0;\n+ }\n+\n+ switch (reg) {\n+ case R_EAX:\n+ return eax;\n+ case R_EBX:\n+ return ebx;\n+ case R_ECX:\n+ return ecx;\n+ case R_EDX:\n+ return edx;\n+ default:\n+ return 0;\n+ }\n+}\ndiff --git a/target/i386/whpx/whpx-i386.h b/target/i386/whpx/whpx-i386.h\nnew file mode 100644\nindex 0000000000..a1cf732862\n--- /dev/null\n+++ b/target/i386/whpx/whpx-i386.h\n@@ -0,0 +1,12 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg);\n+uint64_t whpx_get_supported_msr_feature(uint32_t index);\n+bool whpx_is_legacy_os(void);\n+\n+uint32_t whpx_get_supported_cpuid_legacy(uint32_t func, uint32_t idx,\n+ int reg);\n+bool whpx_has_xsave(void);\n+bool whpx_has_xsaves(void);\n+bool whpx_has_rdtscp(void);\n+bool whpx_has_invpcid(void);\n", "prefixes": [ "v3", "03/37" ] }