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GET /api/patches/2226892/?format=api
{ "id": 2226892, "url": "http://patchwork.ozlabs.org/api/patches/2226892/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.4@forge-stage.sourceware.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.4@forge-stage.sourceware.org>", "list_archive_url": null, "date": "2026-04-22T19:01:38", "name": "[v2,04/14] arm: [MVE intrinsics] rework vgetq_lane vsetq_lane", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5cc7b61b9859af5fd8c483c84c3dd806d722e91a", "submitter": { "id": 92734, "url": "http://patchwork.ozlabs.org/api/people/92734/?format=api", "name": "Christophe Lyon via Sourceware Forge", "email": "forge-bot+clyon@forge-stage.sourceware.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.4@forge-stage.sourceware.org/mbox/", "series": [ { "id": 501104, "url": "http://patchwork.ozlabs.org/api/series/501104/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501104", "date": "2026-04-22T19:01:35", "name": "arm: [MVE intrinsics] rework vpnot, vgetq_lane, vsetq_lane, vuninitialized and scalar shifts", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501104/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226892/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226892/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org", "sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org", "server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Bsk03F5z1yD5\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 07:18:34 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 0173F4F168BE\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 21:18:32 +0000 (GMT)", "from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id A431E4365928\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 19:02:46 +0000 (GMT)", "from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id 6D55F4360A;\n Wed, 22 Apr 2026 19:02:46 +0000 (UTC)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 0173F4F168BE", "OpenDKIM Filter v2.11.0 sourceware.org A431E4365928" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org A431E4365928", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org A431E4365928", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776884566; cv=none;\n b=E3+RiZJhPi+eQiVvR3hO0ZwRI9Kulc21tuBYv1xVSnZj6hNCn4OOSwc90G5rCH0jY8Sk4MJRkMb/2H0CnsoXMlRXac/bDH0QIAEvLg3XVfObRLd5LqZ3oHPrlt7UoegK2NE6ZFbwSxr8i2s+xjrBGlBl0jM4Y4aljuAXuzznNJM=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776884566; c=relaxed/simple;\n bh=GqUthnd4Uw3CufjZFcjSW8mR3f0H6p3HiB9S3jUQmrg=;\n h=From:Date:Subject:To:Message-ID;\n b=ltjE5HxncHxgCW4Fy+G5sn8L5k62GQY51jiwAedg+OMDiaJmoj9m5MErKEU/AI6e+EElCRSHVSWgvN8wFyFSUMM7OMfJD/2Fp3ZpTK4tau+WAwniFBp9XGl12k30V3GZWyAPF5/8Msk6Sd2PQwGiN572xbVDl0FLM+2zxA0a6zM=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Christophe Lyon via Sourceware Forge\n <forge-bot+clyon@forge-stage.sourceware.org>", "Date": "Wed, 22 Apr 2026 19:01:38 +0000", "Subject": "[PATCH v2 04/14] arm: [MVE intrinsics] rework vgetq_lane vsetq_lane", "To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>", "Cc": "sloosemore@baylibre.com", "Message-ID": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.4@forge-stage.sourceware.org>", "X-Mailer": "batrachomyomachia", "X-Pull-Request-Organization": "gcc", "X-Pull-Request-Repository": "gcc-TEST", "X-Pull-Request": "https://forge.sourceware.org/gcc/gcc-TEST/pulls/121", "References": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org>", "In-Reply-To": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org>", "X-Patch-URL": "\n https://forge.sourceware.org/clyon/gcc-TEST/commit/2134090689813af4177c4852a6a58226071861f0", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Reply-To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>,\n sloosemore@baylibre.com, clyon@gcc.gnu.org", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Christophe Lyon <christophe.lyon@linaro.org>\n\nImplement vgetq_lane and vsetq_lane using the new MVE builtins\nframework.\n\nAlthough MVE intrinsics are not supported in big-endian mode, we keep\nthe code to convert lane indices into GCC's vector indices, so that\nit's already in place in case we want to support big-endian in the\nfuture.\n\nThe patch adds new tests, to check that we emit an error when the lane\nnumber is not in the expected range.\n\ngcc/ChangeLog:\n\n\t* config/arm/arm-mve-builtins-base.cc (class\n\tmve_function_vset_vget_lane): New.\n\t(vgetq_lane, vsetq_lane): New.\n\t* config/arm/arm-mve-builtins-base.def (vgetq_lane, vsetq_lane):\n\tNew.\n\t* config/arm/arm-mve-builtins-base.h (vgetq_lane, vsetq_lane):\n\tNew.\n\n\t* config/arm/arm-mve-builtins-shapes.cc (struct getq_lane)\n\t(setq_lane): New.\n\t* config/arm/arm-mve-builtins-shapes.h (getq_lane, setq_lane):\n\tNew.\n\t* config/arm/arm_mve.h (vsetq_lane): Delete.\n\t(vgetq_lane): Delete.\n\t(vsetq_lane_f16): Delete.\n\t(vsetq_lane_f32): Delete.\n\t(vsetq_lane_s16): Delete.\n\t(vsetq_lane_s32): Delete.\n\t(vsetq_lane_s8): Delete.\n\t(vsetq_lane_s64): Delete.\n\t(vsetq_lane_u8): Delete.\n\t(vsetq_lane_u16): Delete.\n\t(vsetq_lane_u32): Delete.\n\t(vsetq_lane_u64): Delete.\n\t(vgetq_lane_f16): Delete.\n\t(vgetq_lane_f32): Delete.\n\t(vgetq_lane_s16): Delete.\n\t(vgetq_lane_s32): Delete.\n\t(vgetq_lane_s8): Delete.\n\t(vgetq_lane_s64): Delete.\n\t(vgetq_lane_u8): Delete.\n\t(vgetq_lane_u16): Delete.\n\t(vgetq_lane_u32): Delete.\n\t(vgetq_lane_u64): Delete.\n\t(__ARM_NUM_LANES): Delete.\n\t(__ARM_LANEQ): Delete.\n\t(__ARM_CHECK_LANEQ): Delete.\n\t(__arm_vsetq_lane_s16): Delete.\n\t(__arm_vsetq_lane_s32): Delete.\n\t(__arm_vsetq_lane_s8): Delete.\n\t(__arm_vsetq_lane_s64): Delete.\n\t(__arm_vsetq_lane_u8): Delete.\n\t(__arm_vsetq_lane_u16): Delete.\n\t(__arm_vsetq_lane_u32): Delete.\n\t(__arm_vsetq_lane_u64): Delete.\n\t(__arm_vgetq_lane_s16): Delete.\n\t(__arm_vgetq_lane_s32): Delete.\n\t(__arm_vgetq_lane_s8): Delete.\n\t(__arm_vgetq_lane_s64): Delete.\n\t(__arm_vgetq_lane_u8): Delete.\n\t(__arm_vgetq_lane_u16): Delete.\n\t(__arm_vgetq_lane_u32): Delete.\n\t(__arm_vgetq_lane_u64): Delete.\n\t(__arm_vsetq_lane_f16): Delete.\n\t(__arm_vsetq_lane_f32): Delete.\n\t(__arm_vgetq_lane_f16): Delete.\n\t(__arm_vgetq_lane_f32): Delete.\n\t(__arm_vsetq_lane): Delete.\n\t(__arm_vgetq_lane): Delete.\n\t* config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Add '@'\n\tprefix.\n\t(mve_vec_set<mode>_internal): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_f16_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_f32_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_s16_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_s32_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_s64_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_s8_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_u16_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_u32_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_u64_bounds.c: New test.\n\t* gcc.target/arm/mve/intrinsics/vsetq_lane_u8_bounds.c: New test.\n---\n gcc/config/arm/arm-mve-builtins-base.cc | 59 +++\n gcc/config/arm/arm-mve-builtins-base.def | 4 +\n gcc/config/arm/arm-mve-builtins-base.h | 2 +\n gcc/config/arm/arm-mve-builtins-shapes.cc | 82 ++++\n gcc/config/arm/arm-mve-builtins-shapes.h | 2 +\n gcc/config/arm/arm_mve.h | 401 ------------------\n gcc/config/arm/mve.md | 5 +-\n .../mve/intrinsics/vsetq_lane_f16_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_f32_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_s16_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_s32_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_s64_bounds.c | 19 +\n .../arm/mve/intrinsics/vsetq_lane_s8_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_u16_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_u32_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_u64_bounds.c | 19 +\n .../arm/mve/intrinsics/vsetq_lane_u8_bounds.c | 19 +\n 17 files changed, 342 insertions(+), 403 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8_bounds.c", "diff": "diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc\nindex e5016f7fb238..eecfb31f0cc6 100644\n--- a/gcc/config/arm/arm-mve-builtins-base.cc\n+++ b/gcc/config/arm/arm-mve-builtins-base.cc\n@@ -1185,6 +1185,63 @@ public:\n }\n };\n \n+ /* Map the function directly to mve_vec_set_internal (M) or mve_vec_extract\n+ (M, M) where M is the vector mode associated with type suffix 0, except when\n+ mode is V2DI where the builtin name is hardcoded. */\n+class mve_function_vsetq_vgetq_lane : public function_base\n+{\n+public:\n+ CONSTEXPR mve_function_vsetq_vgetq_lane (bool is_get)\n+ : m_is_get (is_get)\n+ {}\n+\n+ /* True for vgetq_lane, false for vsetq_lane. */\n+ bool m_is_get;\n+\n+ rtx\n+ expand (function_expander &e) const override\n+ {\n+ machine_mode mode = e.vector_mode (0);\n+ insn_code code;\n+ HOST_WIDE_INT elem;\n+\n+ code = (mode == V2DImode)\n+ ? (m_is_get\n+\t ? CODE_FOR_mve_vec_extractv2didi\n+\t : CODE_FOR_mve_vec_setv2di_internal)\n+ : (m_is_get\n+\t ? code_for_mve_vec_extract (mode, mode)\n+\t : code_for_mve_vec_set_internal (mode));\n+\n+ if (!m_is_get)\n+ {\n+\t/* mve_vec_set has vector and lane number arguments in opposite order\n+\t compared to the intrinsic: swap them now... */\n+\tstd::swap (e.args[1], e.args[2]);\n+ }\n+\n+ elem = INTVAL (e.args[1]);\n+\n+ /* For big-endian, GCC's vector indices are reversed within each 64 bits\n+ compared to the architectural lane indices used by MVE intrinsics. */\n+ if (BYTES_BIG_ENDIAN)\n+ {\n+\tunsigned int num_lanes = 128 / e.type_suffix (0).element_bits;\n+\telem ^= (num_lanes / 2) - 1;\n+ }\n+\n+ if (!m_is_get)\n+ {\n+\t/* ... and convert the lane number into a mask as expected by the\n+\t builtin. */\n+\telem = HOST_WIDE_INT_1 << elem;\n+ }\n+ e.args[1] = GEN_INT (elem);\n+\n+ return e.use_unpred_insn (code);\n+ }\n+};\n+\n } /* end anonymous namespace */\n \n namespace arm_mve {\n@@ -1408,6 +1465,7 @@ FUNCTION_WITH_RTX_M (veorq, XOR, VEORQ)\n FUNCTION (vfmaq, unspec_mve_function_exact_insn, (-1, -1, VFMAQ_F, -1, -1, VFMAQ_N_F, -1, -1, VFMAQ_M_F, -1, -1, VFMAQ_M_N_F))\n FUNCTION (vfmasq, unspec_mve_function_exact_insn, (-1, -1, -1, -1, -1, VFMASQ_N_F, -1, -1, -1, -1, -1, VFMASQ_M_N_F))\n FUNCTION (vfmsq, unspec_mve_function_exact_insn, (-1, -1, VFMSQ_F, -1, -1, -1, -1, -1, VFMSQ_M_F, -1, -1, -1))\n+FUNCTION (vgetq_lane, mve_function_vsetq_vgetq_lane, (true))\n FUNCTION_WITH_M_N_NO_F (vhaddq, VHADDQ)\n FUNCTION_WITH_M_N_NO_F (vhsubq, VHSUBQ)\n FUNCTION (vld1q, vld1_impl,)\n@@ -1536,6 +1594,7 @@ FUNCTION_ONLY_N_NO_F (vrshrntq, VRSHRNTQ)\n FUNCTION_ONLY_N_NO_F (vrshrq, VRSHRQ)\n FUNCTION (vsbciq, vadc_vsbc_impl, (true, false))\n FUNCTION (vsbcq, vadc_vsbc_impl, (false, false))\n+FUNCTION (vsetq_lane, mve_function_vsetq_vgetq_lane, (false))\n FUNCTION (vshlcq, vshlc_impl,)\n FUNCTION_ONLY_N_NO_F (vshllbq, VSHLLBQ)\n FUNCTION_ONLY_N_NO_F (vshlltq, VSHLLTQ)\ndiff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def\nindex 5c2860dc7201..e5a295265f6c 100644\n--- a/gcc/config/arm/arm-mve-builtins-base.def\n+++ b/gcc/config/arm/arm-mve-builtins-base.def\n@@ -52,6 +52,7 @@ DEF_MVE_FUNCTION (vddupq, viddup, all_unsigned, mx_or_none)\n DEF_MVE_FUNCTION (vdupq, unary_n, all_integer, mx_or_none)\n DEF_MVE_FUNCTION (vdwdupq, vidwdup, all_unsigned, mx_or_none)\n DEF_MVE_FUNCTION (veorq, binary, all_integer, mx_or_none)\n+DEF_MVE_FUNCTION (vgetq_lane, getq_lane, all_integer_with_64, none)\n DEF_MVE_FUNCTION (vhaddq, binary_opt_n, all_integer, mx_or_none)\n DEF_MVE_FUNCTION (vhcaddq_rot270, binary, all_signed, mx_or_none)\n DEF_MVE_FUNCTION (vhcaddq_rot90, binary, all_signed, mx_or_none)\n@@ -172,6 +173,7 @@ DEF_MVE_FUNCTION (vrshrq, binary_rshift, all_integer, mx_or_none)\n DEF_MVE_FUNCTION (vsbciq, vadc_vsbc, integer_32, m_or_none)\n DEF_MVE_FUNCTION (vsbcq, vadc_vsbc, integer_32, m_or_none)\n DEF_MVE_FUNCTION (vshlcq, vshlc, all_integer, m_or_none)\n+DEF_MVE_FUNCTION (vsetq_lane, setq_lane, all_integer_with_64, none)\n DEF_MVE_FUNCTION (vshllbq, binary_widen_n, integer_8_16, mx_or_none)\n DEF_MVE_FUNCTION (vshlltq, binary_widen_n, integer_8_16, mx_or_none)\n DEF_MVE_FUNCTION (vshlq, binary_lshift, all_integer, mx_or_none)\n@@ -238,6 +240,7 @@ DEF_MVE_FUNCTION (veorq, binary, all_float, mx_or_none)\n DEF_MVE_FUNCTION (vfmaq, ternary_opt_n, all_float, m_or_none)\n DEF_MVE_FUNCTION (vfmasq, ternary_n, all_float, m_or_none)\n DEF_MVE_FUNCTION (vfmsq, ternary, all_float, m_or_none)\n+DEF_MVE_FUNCTION (vgetq_lane, getq_lane, all_float, none)\n DEF_MVE_FUNCTION (vld1q, load, all_float, z_or_none)\n DEF_MVE_FUNCTION (vld2q, load, all_float, none)\n DEF_MVE_FUNCTION (vld4q, load, all_float, none)\n@@ -270,6 +273,7 @@ DEF_MVE_FUNCTION (vrndnq, unary, all_float, mx_or_none)\n DEF_MVE_FUNCTION (vrndpq, unary, all_float, mx_or_none)\n DEF_MVE_FUNCTION (vrndq, unary, all_float, mx_or_none)\n DEF_MVE_FUNCTION (vrndxq, unary, all_float, mx_or_none)\n+DEF_MVE_FUNCTION (vsetq_lane, setq_lane, all_float, none)\n DEF_MVE_FUNCTION (vst1q, store, all_float, p_or_none)\n DEF_MVE_FUNCTION (vst2q, store, all_float, none)\n DEF_MVE_FUNCTION (vst4q, store, all_float, none)\ndiff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h\nindex 2b6b6b5a9efb..285cb0c69575 100644\n--- a/gcc/config/arm/arm-mve-builtins-base.h\n+++ b/gcc/config/arm/arm-mve-builtins-base.h\n@@ -75,6 +75,7 @@ extern const function_base *const veorq;\n extern const function_base *const vfmaq;\n extern const function_base *const vfmasq;\n extern const function_base *const vfmsq;\n+extern const function_base *const vgetq_lane;\n extern const function_base *const vhaddq;\n extern const function_base *const vhcaddq_rot270;\n extern const function_base *const vhcaddq_rot90;\n@@ -207,6 +208,7 @@ extern const function_base *const vrshrntq;\n extern const function_base *const vrshrq;\n extern const function_base *const vsbciq;\n extern const function_base *const vsbcq;\n+extern const function_base *const vsetq_lane;\n extern const function_base *const vshlcq;\n extern const function_base *const vshllbq;\n extern const function_base *const vshlltq;\ndiff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-mve-builtins-shapes.cc\nindex b324c2847dbc..03f70f8ba167 100644\n--- a/gcc/config/arm/arm-mve-builtins-shapes.cc\n+++ b/gcc/config/arm/arm-mve-builtins-shapes.cc\n@@ -1467,6 +1467,47 @@ struct create_def : public nonoverloaded_base\n };\n SHAPE (create)\n \n+/* <S0>_t vfoo[_t0](<T0>_t, const int)\n+\n+ Check that 'idx' is in the [0..#num_lanes - 1] range.\n+\n+ Example: vgetq_lane.\n+ int8_t [__arm_]vgetq_lane[_s8](int8x16_t a, const int idx) */\n+\n+struct getq_lane_def : public overloaded_base<0>\n+{\n+ void\n+ build (function_builder &b, const function_group_info &group,\n+\t bool preserve_user_namespace) const override\n+ {\n+ b.add_overloaded_functions (group, MODE_none, preserve_user_namespace);\n+ build_all (b, \"s0,v0,su64\", group, MODE_none, preserve_user_namespace);\n+ }\n+\n+ tree\n+ resolve (function_resolver &r) const override\n+ {\n+ unsigned int i, nargs;\n+ type_suffix_index type;\n+ if (!r.check_gp_argument (2, i, nargs)\n+\t|| (type = r.infer_vector_type (i-1)) == NUM_TYPE_SUFFIXES\n+\t|| !r.require_integer_immediate (i))\n+ return error_mark_node;\n+\n+ return r.resolve_to (r.mode_suffix_id, type);\n+ }\n+\n+ bool\n+ check (function_checker &c) const override\n+ {\n+ unsigned int num_lanes = 128 / c.type_suffix (0).element_bits;\n+\n+ return c.require_immediate_range (1, 0, num_lanes - 1);\n+ }\n+\n+};\n+SHAPE (getq_lane)\n+\n /* <T0>[xN]_t vfoo_t0().\n \n Example: vuninitializedq.\n@@ -1682,6 +1723,47 @@ struct mvn_def : public overloaded_base<0>\n };\n SHAPE (mvn)\n \n+/* <T0>_t vfoo[_t0](<S0>_t, <T0>_t, const_int)\n+\n+ Check that 'idx' is in the [0..#num_lanes - 1] range.\n+\n+ Example: vsetq_lane.\n+ int8x16_t [__arm_]vsetq_lane[_s8](int8_t a, int8x16_t b, const int idx) */\n+struct setq_lane_def : public overloaded_base<0>\n+{\n+ void\n+ build (function_builder &b, const function_group_info &group,\n+\t bool preserve_user_namespace) const override\n+ {\n+ b.add_overloaded_functions (group, MODE_none, preserve_user_namespace);\n+ build_all (b, \"v0,s0,v0,su64\", group, MODE_none, preserve_user_namespace);\n+ }\n+\n+ tree\n+ resolve (function_resolver &r) const override\n+ {\n+ unsigned int i, nargs;\n+ type_suffix_index type;\n+ if (!r.check_gp_argument (3, i, nargs)\n+\t|| (type = r.infer_vector_type (i-1)) == NUM_TYPE_SUFFIXES\n+\t|| !r.require_derived_scalar_type (i - 2, r.SAME_TYPE_CLASS)\n+\t|| !r.require_integer_immediate (i))\n+ return error_mark_node;\n+\n+ return r.resolve_to (r.mode_suffix_id, type);\n+ }\n+\n+ bool\n+ check (function_checker &c) const override\n+ {\n+ unsigned int num_lanes = 128 / c.type_suffix (0).element_bits;\n+\n+ return c.require_immediate_range (2, 0, num_lanes - 1);\n+ }\n+\n+};\n+SHAPE (setq_lane)\n+\n /* void vfoo[_t0](<X>_t *, <T0>[xN]_t)\n \n where <X> might be tied to <t0> (for non-truncating stores) or might\ndiff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-mve-builtins-shapes.h\nindex 7614c92d1cd2..4763eeeda320 100644\n--- a/gcc/config/arm/arm-mve-builtins-shapes.h\n+++ b/gcc/config/arm/arm-mve-builtins-shapes.h\n@@ -60,12 +60,14 @@ namespace arm_mve\n extern const function_shape *const binary_widen_poly;\n extern const function_shape *const cmp;\n extern const function_shape *const create;\n+ extern const function_shape *const getq_lane;\n extern const function_shape *const inherent;\n extern const function_shape *const load;\n extern const function_shape *const load_ext;\n extern const function_shape *const load_ext_gather_offset;\n extern const function_shape *const load_gather_base;\n extern const function_shape *const mvn;\n+ extern const function_shape *const setq_lane;\n extern const function_shape *const store;\n extern const function_shape *const store_scatter_base;\n extern const function_shape *const store_scatter_offset;\ndiff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h\nindex 64b22759a990..9947420dcdb0 100644\n--- a/gcc/config/arm/arm_mve.h\n+++ b/gcc/config/arm/arm_mve.h\n@@ -46,8 +46,6 @@\n \n #ifndef __ARM_MVE_PRESERVE_USER_NAMESPACE\n #define vuninitializedq(__v) __arm_vuninitializedq(__v)\n-#define vsetq_lane(__a, __b, __idx) __arm_vsetq_lane(__a, __b, __idx)\n-#define vgetq_lane(__a, __idx) __arm_vgetq_lane(__a, __idx)\n \n \n #define vuninitializedq_u8(void) __arm_vuninitializedq_u8(void)\n@@ -60,26 +58,6 @@\n #define vuninitializedq_s64(void) __arm_vuninitializedq_s64(void)\n #define vuninitializedq_f16(void) __arm_vuninitializedq_f16(void)\n #define vuninitializedq_f32(void) __arm_vuninitializedq_f32(void)\n-#define vsetq_lane_f16(__a, __b, __idx) __arm_vsetq_lane_f16(__a, __b, __idx)\n-#define vsetq_lane_f32(__a, __b, __idx) __arm_vsetq_lane_f32(__a, __b, __idx)\n-#define vsetq_lane_s16(__a, __b, __idx) __arm_vsetq_lane_s16(__a, __b, __idx)\n-#define vsetq_lane_s32(__a, __b, __idx) __arm_vsetq_lane_s32(__a, __b, __idx)\n-#define vsetq_lane_s8(__a, __b, __idx) __arm_vsetq_lane_s8(__a, __b, __idx)\n-#define vsetq_lane_s64(__a, __b, __idx) __arm_vsetq_lane_s64(__a, __b, __idx)\n-#define vsetq_lane_u8(__a, __b, __idx) __arm_vsetq_lane_u8(__a, __b, __idx)\n-#define vsetq_lane_u16(__a, __b, __idx) __arm_vsetq_lane_u16(__a, __b, __idx)\n-#define vsetq_lane_u32(__a, __b, __idx) __arm_vsetq_lane_u32(__a, __b, __idx)\n-#define vsetq_lane_u64(__a, __b, __idx) __arm_vsetq_lane_u64(__a, __b, __idx)\n-#define vgetq_lane_f16(__a, __idx) __arm_vgetq_lane_f16(__a, __idx)\n-#define vgetq_lane_f32(__a, __idx) __arm_vgetq_lane_f32(__a, __idx)\n-#define vgetq_lane_s16(__a, __idx) __arm_vgetq_lane_s16(__a, __idx)\n-#define vgetq_lane_s32(__a, __idx) __arm_vgetq_lane_s32(__a, __idx)\n-#define vgetq_lane_s8(__a, __idx) __arm_vgetq_lane_s8(__a, __idx)\n-#define vgetq_lane_s64(__a, __idx) __arm_vgetq_lane_s64(__a, __idx)\n-#define vgetq_lane_u8(__a, __idx) __arm_vgetq_lane_u8(__a, __idx)\n-#define vgetq_lane_u16(__a, __idx) __arm_vgetq_lane_u16(__a, __idx)\n-#define vgetq_lane_u32(__a, __idx) __arm_vgetq_lane_u32(__a, __idx)\n-#define vgetq_lane_u64(__a, __idx) __arm_vgetq_lane_u64(__a, __idx)\n #define sqrshr(__p0, __p1) __arm_sqrshr(__p0, __p1)\n #define sqrshrl(__p0, __p1) __arm_sqrshrl(__p0, __p1)\n #define sqrshrl_sat48(__p0, __p1) __arm_sqrshrl_sat48(__p0, __p1)\n@@ -98,154 +76,6 @@\n #define asrl(__p0, __p1) __arm_asrl(__p0, __p1)\n #endif\n \n-/* For big-endian, GCC's vector indices are reversed within each 64 bits\n- compared to the architectural lane indices used by MVE intrinsics. */\n-#define __ARM_NUM_LANES(__v) (sizeof (__v) / sizeof (__v[0]))\n-#ifdef __ARM_BIG_ENDIAN\n-#define __ARM_LANEQ(__vec, __idx) (__idx ^ (__ARM_NUM_LANES(__vec)/2 - 1))\n-#else\n-#define __ARM_LANEQ(__vec, __idx) __idx\n-#endif\n-#define __ARM_CHECK_LANEQ(__vec, __idx)\t\t \\\n- __builtin_arm_lane_check (__ARM_NUM_LANES(__vec), \\\n-\t\t\t __ARM_LANEQ(__vec, __idx))\n-\n-__extension__ extern __inline int16x8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_s16 (int16_t __a, int16x8_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline int32x4_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_s32 (int32_t __a, int32x4_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline int8x16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_s8 (int8_t __a, int8x16_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline int64x2_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_s64 (int64_t __a, int64x2_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline uint8x16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_u8 (uint8_t __a, uint8x16_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline uint16x8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_u16 (uint16_t __a, uint16x8_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline uint32x4_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_u32 (uint32_t __a, uint32x4_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline uint64x2_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_u64 (uint64_t __a, uint64x2_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline int16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_s16 (int16x8_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline int32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_s32 (int32x4_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline int8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_s8 (int8x16_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline int64_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_s64 (int64x2_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline uint8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_u8 (uint8x16_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline uint16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_u16 (uint16x8_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline uint32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_u32 (uint32x4_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline uint64_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_u64 (uint64x2_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n __extension__ extern __inline uint64_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n __arm_lsll (uint64_t value, int32_t shift)\n@@ -358,189 +188,8 @@ __arm_srshr (int32_t value, const int shift)\n return __builtin_mve_srshr_si (value, shift);\n }\n \n-#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */\n-\n-__extension__ extern __inline float16x8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_f16 (float16_t __a, float16x8_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline float32x4_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane_f32 (float32_t __a, float32x4_t __b, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__b, __idx);\n- __b[__ARM_LANEQ(__b,__idx)] = __a;\n- return __b;\n-}\n-\n-__extension__ extern __inline float16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_f16 (float16x8_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-\n-__extension__ extern __inline float32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane_f32 (float32x4_t __a, const int __idx)\n-{\n- __ARM_CHECK_LANEQ (__a, __idx);\n- return __a[__ARM_LANEQ(__a,__idx)];\n-}\n-#endif\n-\n #ifdef __cplusplus\n \n-__extension__ extern __inline int16x8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (int16_t __a, int16x8_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_s16 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline int32x4_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (int32_t __a, int32x4_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_s32 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline int8x16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (int8_t __a, int8x16_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_s8 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline int64x2_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (int64_t __a, int64x2_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_s64 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline uint8x16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (uint8_t __a, uint8x16_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_u8 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline uint16x8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (uint16_t __a, uint16x8_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_u16 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline uint32x4_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (uint32_t __a, uint32x4_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_u32 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline uint64x2_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (uint64_t __a, uint64x2_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_u64 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline int16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (int16x8_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_s16 (__a, __idx);\n-}\n-\n-__extension__ extern __inline int32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (int32x4_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_s32 (__a, __idx);\n-}\n-\n-__extension__ extern __inline int8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (int8x16_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_s8 (__a, __idx);\n-}\n-\n-__extension__ extern __inline int64_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (int64x2_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_s64 (__a, __idx);\n-}\n-\n-__extension__ extern __inline uint8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (uint8x16_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_u8 (__a, __idx);\n-}\n-\n-__extension__ extern __inline uint16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (uint16x8_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_u16 (__a, __idx);\n-}\n-\n-__extension__ extern __inline uint32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (uint32x4_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_u32 (__a, __idx);\n-}\n-\n-__extension__ extern __inline uint64_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (uint64x2_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_u64 (__a, __idx);\n-}\n-\n-#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */\n-\n-__extension__ extern __inline float16x8_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (float16_t __a, float16x8_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_f16 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline float32x4_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vsetq_lane (float32_t __a, float32x4_t __b, const int __idx)\n-{\n- return __arm_vsetq_lane_f32 (__a, __b, __idx);\n-}\n-\n-__extension__ extern __inline float16_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (float16x8_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_f16 (__a, __idx);\n-}\n-\n-__extension__ extern __inline float32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_vgetq_lane (float32x4_t __a, const int __idx)\n-{\n- return __arm_vgetq_lane_f32 (__a, __idx);\n-}\n-#endif /* MVE Floating point. */\n-\n-\n __extension__ extern __inline uint8x16_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n __arm_vuninitializedq (uint8x16_t /* __v ATTRIBUTE UNUSED */)\n@@ -863,33 +512,6 @@ extern void *__ARM_undef;\n int (*)[__ARM_mve_type_float16x8_t]: __arm_vuninitializedq_f16 (), \\\n int (*)[__ARM_mve_type_float32x4_t]: __arm_vuninitializedq_f32 ());})\n \n-#define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \\\n- _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \\\n- int (*)[__ARM_mve_type_int8x16_t]: __arm_vgetq_lane_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \\\n- int (*)[__ARM_mve_type_int16x8_t]: __arm_vgetq_lane_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \\\n- int (*)[__ARM_mve_type_int32x4_t]: __arm_vgetq_lane_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \\\n- int (*)[__ARM_mve_type_int64x2_t]: __arm_vgetq_lane_s64 (__ARM_mve_coerce(__p0, int64x2_t), p1), \\\n- int (*)[__ARM_mve_type_uint8x16_t]: __arm_vgetq_lane_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \\\n- int (*)[__ARM_mve_type_uint16x8_t]: __arm_vgetq_lane_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \\\n- int (*)[__ARM_mve_type_uint32x4_t]: __arm_vgetq_lane_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1), \\\n- int (*)[__ARM_mve_type_uint64x2_t]: __arm_vgetq_lane_u64 (__ARM_mve_coerce(__p0, uint64x2_t), p1), \\\n- int (*)[__ARM_mve_type_float16x8_t]: __arm_vgetq_lane_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \\\n- int (*)[__ARM_mve_type_float32x4_t]: __arm_vgetq_lane_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));})\n-\n-#define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \\\n- __typeof(p1) __p1 = (p1); \\\n- _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \\\n- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \\\n- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})\n-\n #else /* MVE Integer. */\n \n #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \\\n@@ -903,29 +525,6 @@ extern void *__ARM_undef;\n int (*)[__ARM_mve_type_uint32x4_t]: __arm_vuninitializedq_u32 (), \\\n int (*)[__ARM_mve_type_uint64x2_t]: __arm_vuninitializedq_u64 ());})\n \n-#define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \\\n- _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \\\n- int (*)[__ARM_mve_type_int8x16_t]: __arm_vgetq_lane_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \\\n- int (*)[__ARM_mve_type_int16x8_t]: __arm_vgetq_lane_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \\\n- int (*)[__ARM_mve_type_int32x4_t]: __arm_vgetq_lane_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \\\n- int (*)[__ARM_mve_type_int64x2_t]: __arm_vgetq_lane_s64 (__ARM_mve_coerce(__p0, int64x2_t), p1), \\\n- int (*)[__ARM_mve_type_uint8x16_t]: __arm_vgetq_lane_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \\\n- int (*)[__ARM_mve_type_uint16x8_t]: __arm_vgetq_lane_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \\\n- int (*)[__ARM_mve_type_uint32x4_t]: __arm_vgetq_lane_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1), \\\n- int (*)[__ARM_mve_type_uint64x2_t]: __arm_vgetq_lane_u64 (__ARM_mve_coerce(__p0, uint64x2_t), p1));})\n-\n-#define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \\\n- __typeof(p1) __p1 = (p1); \\\n- _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \\\n- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));})\n-\n #endif /* MVE Integer. */\n \n #endif /* __cplusplus */\ndiff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md\nindex 87b45b2e41c2..9da6684ab9b3 100644\n--- a/gcc/config/arm/mve.md\n+++ b/gcc/config/arm/mve.md\n@@ -4158,10 +4158,11 @@\n return \"\";\n }\n [(set_attr \"length\" \"16\")])\n+\n ;;\n ;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f])\n ;;\n-(define_insn \"mve_vec_extract<mode><V_elem_l>\"\n+(define_insn \"@mve_vec_extract<mode><V_elem_l>\"\n [(set (match_operand:<V_elem> 0 \"nonimmediate_operand\" \"=r\")\n (vec_select:<V_elem>\n (match_operand:MVE_VLD_ST 1 \"s_register_operand\" \"w\")\n@@ -4236,7 +4237,7 @@\n ;;\n ;; [vsetq_lane_u, vsetq_lane_s, vsetq_lane_f])\n ;;\n-(define_insn \"mve_vec_set<mode>_internal\"\n+(define_insn \"@mve_vec_set<mode>_internal\"\n [(set (match_operand:VQ2 0 \"s_register_operand\" \"=w\")\n (vec_merge:VQ2\n \t(vec_duplicate:VQ2\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16_bounds.c\nnew file mode 100644\nindex 000000000000..0aec13fdf4e7\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_fp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+float16x8_t\n+foo (float16_t a, float16x8_t b)\n+{\n+ return vsetq_lane_f16 (a, b, 9); /* { dg-error {passing 9 to argument 3 of 'vsetq_lane_f16', which expects a value in the range \\[0, 7\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32_bounds.c\nnew file mode 100644\nindex 000000000000..5627e0a17c12\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_fp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+float32x4_t\n+foo (float32_t a, float32x4_t b)\n+{\n+ return vsetq_lane_f32 (a, b, 4); /* { dg-error {passing 4 to argument 3 of 'vsetq_lane_f32', which expects a value in the range \\[0, 3\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16_bounds.c\nnew file mode 100644\nindex 000000000000..af255f8dba98\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+int16x8_t\n+foo (int16_t a, int16x8_t b)\n+{\n+ return vsetq_lane_s16 (a, b, 9); /* { dg-error {passing 9 to argument 3 of 'vsetq_lane_s16', which expects a value in the range \\[0, 7\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32_bounds.c\nnew file mode 100644\nindex 000000000000..968910cf0a3a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+int32x4_t\n+foo (int32_t a, int32x4_t b)\n+{\n+ return vsetq_lane_s32 (a, b, 4); /* { dg-error {passing 4 to argument 3 of 'vsetq_lane_s32', which expects a value in the range \\[0, 3\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64_bounds.c\nnew file mode 100644\nindex 000000000000..f3bf3ac38861\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+int64x2_t\n+foo (int64_t a, int64x2_t b)\n+{\n+ return vsetq_lane_s64 (a, b, 2); /* { dg-error {passing 2 to argument 3 of 'vsetq_lane_s64', which expects a value in the range \\[0, 1\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8_bounds.c\nnew file mode 100644\nindex 000000000000..0f4f23805551\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+int8x16_t\n+foo (int8_t a, int8x16_t b)\n+{\n+ return vsetq_lane_s8 (a, b, 17); /* { dg-error {passing 17 to argument 3 of 'vsetq_lane_s8', which expects a value in the range \\[0, 15\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16_bounds.c\nnew file mode 100644\nindex 000000000000..62a03c0dc50b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+uint16x8_t\n+foo (uint16_t a, uint16x8_t b)\n+{\n+ return vsetq_lane_u16 (a, b, 8); /* { dg-error {passing 8 to argument 3 of 'vsetq_lane_u16', which expects a value in the range \\[0, 7\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32_bounds.c\nnew file mode 100644\nindex 000000000000..5836eeb994ff\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+uint32x4_t\n+foo (uint32_t a, uint32x4_t b)\n+{\n+ return vsetq_lane_u32 (a, b, 4); /* { dg-error {passing 4 to argument 3 of 'vsetq_lane_u32', which expects a value in the range \\[0, 3\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64_bounds.c\nnew file mode 100644\nindex 000000000000..8be2b80e5371\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+uint64x2_t\n+foo (uint64_t a, uint64x2_t b)\n+{\n+ return vsetq_lane_u64 (a, b, 2); /* { dg-error {passing 2 to argument 3 of 'vsetq_lane_u64', which expects a value in the range \\[0, 1\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8_bounds.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8_bounds.c\nnew file mode 100644\nindex 000000000000..987dc98b5e80\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8_bounds.c\n@@ -0,0 +1,19 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+uint8x16_t\n+foo (uint8_t a, uint8x16_t b)\n+{\n+ return vsetq_lane_u8 (a, b, 17); /* { dg-error {passing 17 to argument 3 of 'vsetq_lane_u8', which expects a value in the range \\[0, 15\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n", "prefixes": [ "v2", "04/14" ] }