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GET /api/patches/2226873/?format=api
{ "id": 2226873, "url": "http://patchwork.ozlabs.org/api/patches/2226873/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.2@forge-stage.sourceware.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.2@forge-stage.sourceware.org>", "list_archive_url": null, "date": "2026-04-22T19:01:36", "name": "[v2,02/14] arm: [MVE intrinsics] Avoid warnings when floating-point is not supported [PR 117814]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "611162397e8f6c449b23797818ba02ea2b0a70d6", "submitter": { "id": 92734, "url": "http://patchwork.ozlabs.org/api/people/92734/?format=api", "name": "Christophe Lyon via Sourceware Forge", "email": "forge-bot+clyon@forge-stage.sourceware.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.2@forge-stage.sourceware.org/mbox/", "series": [ { "id": 501104, "url": "http://patchwork.ozlabs.org/api/series/501104/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501104", "date": "2026-04-22T19:01:35", "name": "arm: [MVE intrinsics] rework vpnot, vgetq_lane, vsetq_lane, vuninitialized and scalar shifts", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501104/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226873/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226873/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org", "sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org", "server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1BTh1ZVBz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 07:01:12 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 819344AA0E7E\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 20:53:49 +0000 (GMT)", "from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id 7D7E640A1E9E\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 19:02:46 +0000 (GMT)", "from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id 50CB443608;\n Wed, 22 Apr 2026 19:02:46 +0000 (UTC)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 819344AA0E7E", "OpenDKIM Filter v2.11.0 sourceware.org 7D7E640A1E9E" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 7D7E640A1E9E", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 7D7E640A1E9E", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776884566; cv=none;\n b=m7UXgZY6qQ2afTakoWPNNTNMsd0YSxf5IWOmwDlmqA40HDm5s8n6JzFwQscVFQYOx1SEA2n4xJqgYkYX9K7XbOkGbggGZiGNDLH8mCiE25OYNkN7ewwnxhmtPZunlOknMo0RJfa2DAb//T5cJAadvCIZPzVaDMGJ3ofJp9bD0Hs=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776884566; c=relaxed/simple;\n bh=6S1F0rREwPD4I+GCa2iVE/KBdSTsPAbsRSGpf2g11GU=;\n h=From:Date:Subject:To:Message-ID;\n b=OVRaRwlx2SzzbRaKnCsndPGNsT92+BPZbyE3N1EuVbN7ofv0kHUGvQCgREc46yoSk81cIFDIWUa0LVi6+5dTMOLVcGZm5l4bVynhTxccLPsnhEvLf2+HyP5SulVkZkTF3Jm+YGnXu5Z8PHA/3OmQe8iYEFSe6oUqp+SPugjTKE4=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Christophe Lyon via Sourceware Forge\n <forge-bot+clyon@forge-stage.sourceware.org>", "Date": "Wed, 22 Apr 2026 19:01:36 +0000", "Subject": "[PATCH v2 02/14] arm: [MVE intrinsics] Avoid warnings when\n floating-point is not supported [PR 117814]", "To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>", "Cc": "sloosemore@baylibre.com", "Message-ID": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.2@forge-stage.sourceware.org>", "X-Mailer": "batrachomyomachia", "X-Pull-Request-Organization": "gcc", "X-Pull-Request-Repository": "gcc-TEST", "X-Pull-Request": "https://forge.sourceware.org/gcc/gcc-TEST/pulls/121", "References": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org>", "In-Reply-To": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org>", "X-Patch-URL": "\n https://forge.sourceware.org/clyon/gcc-TEST/commit/84550d5c0a2f4c480a5c1781f697e22b864e29ea", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Reply-To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>,\n sloosemore@baylibre.com, clyon@gcc.gnu.org", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Christophe Lyon <christophe.lyon@linaro.org>\n\nIf the target does not support floating-point, we register FP vector\ntypes as 'void' (see register_vector_type).\n\nThis leads to warnings about 'pure attribute on function returning\nvoid' when we declare the various load intrinsics because their\ncall_properties say CP_READ_MEMORY (thus giving them the 'pure'\nattribute), but their return type is void. This happens for instance\nin gcc.target/arm/pr112337.c, depending on how GCC is built (I didn't\nnotice the warnings because arm_mve.h is considered as a system\ninclude in my environment, and the warning is not emitted, but CI\nreported it).\n\nTo avoid such warnings, declare floating-point scalar and vector types\neven if the target does not have an FPU.\n\nNote that since an FPU can be activated via #pragma GCC target\n(\"arch=armv8.1-m.main+mve.fp\" for instance), it means that such types\ncannot appear and disappear withing a single TU, they have to be\navailable in all contexts. This implies a noteworthy change for\n__fp16: it not longer depends on using -mfp16-format=ieee or\nalternative. Also note that if the target ISA has the fp16 bit set,\nwe already silently activate -mfp16-format=ieee (with an error if\n-mfp16-format=alternative was supplied). The patch now enforces\n-mfp16-format=none if the option was used.\n\nIn arm-mve-builtins.cc (register_builtin_types, register_vector_type,\nregister_builtin_tuple_types), this means simply removing the early\nexits. However, for this to work, we need to update\narm_vector_mode_supported_p, so that vector floating-point types are\nalways defined, and __fp16 must always be registered by\narm_init_fp16_builtins (as it is the base type for vectors of\nfloat16_t. Another side effect is that the declaration of float16_t\nand float32_t typedefs is now unconditional.\n\nThe new tests verify that:\n- we emit an error if the code tries to use floating-point intrinsics\n and the target does not have the floating-point extension\n- we emit the expected code when activating the floating-point\n expected via a pragma\n- we emit the expected code when the target supports floating-point\n (no pragma needed)\n- we apply -mfp16-format=none where we used to default to ieee\n\nAn update is needed in g++.target/arm/mve/general-c++/nomve_fp_1.c,\nbecause the error message now correctly uses float16x8_t instead of\nvoid as return type.\n\nThe patch removes gcc.target/arm/fp16-compile-none-1.c which tests\nthat using __fp16 produces an error with -mfp16-format=none, since it\nis no longer the case.\n\ngcc/ChangeLog:\n\n\tPR target/117814\n\t* config/arm/arm-builtins.cc (arm_init_fp16_builtins): Always\n\tregister __fp16 type.\n\t* config/arm/arm-mve-builtins.cc (register_builtin_tuple_types):\n\tRemove special handling when TARGET_HAVE_MVE_FLOAT is false.\n\t(register_vector_type): Likewise.\n\t(register_builtin_tuple_types): Likewise.\n\t* config/arm/arm-opts.h (arm_fp16_format_type): Add\n\tARM_FP16_FORMAT_DEFAULT.\n\t* config/arm/arm.cc (arm_vector_mode_supported_p): Accept\n\tfloating-point vector modes even if TARGET_HAVE_MVE_FLOAT is\n\tfalse.\n\t(arm_option_reconfigure_globals): Apply ARM_FP16_FORMAT_NONE if\n\trequested.\n\t* config/arm/arm.opt (mfp16-format): Default to\n\tARM_FP16_FORMAT_DEFAULT.\n\t* config/arm/arm_mve_types.h (float16_t, float32_t): Define\n\tunconditionally.\n\t* doc/sourcebuild.texi (ARM-specific attributes): Document\n\tarm_v8_1m_mve_nofp_ok.\n\ngcc/testsuite/ChangeLog:\n\n\tPR target/117814\n\t* gcc.target/arm/mve/intrinsics/pr117814-f16.c: New test.\n\t* gcc.target/arm/mve/intrinsics/pr117814-2-f16.c: New test.\n\t* gcc.target/arm/mve/intrinsics/pr117814-3-f16.c: New test.\n\t* gcc.target/arm/mve/intrinsics/pr117814-4-f16.c: New test.\n\t* gcc.target/arm/mve/intrinsics/pr117814-f32.c: New test.\n\t* gcc.target/arm/mve/intrinsics/pr117814-2-f32.c: New test.\n\t* gcc.target/arm/mve/intrinsics/pr117814-3-f32.c: New test.\n\t* gcc.target/arm/fp16-compile-none-1.c: Delete.\n\t* g++.target/arm/mve/general-c++/nomve_fp_1.c: Fix expected error\n\tmessage.\n\t* lib/target-supports.exp\n\t(check_effective_target_arm_v8_1m_mve_nofp_ok_nocache): New.\n\t(check_effective_target_arm_v8_1m_mve_nofp_ok): New.\n\t(add_options_for_arm_v8_1m_mve_nofp): New.\n---\n gcc/config/arm/arm-builtins.cc | 4 +-\n gcc/config/arm/arm-mve-builtins.cc | 22 +-------\n gcc/config/arm/arm-opts.h | 1 +\n gcc/config/arm/arm.cc | 14 ++---\n gcc/config/arm/arm.opt | 2 +-\n gcc/config/arm/arm_mve_types.h | 2 -\n gcc/doc/sourcebuild.texi | 6 +++\n .../arm/mve/general-c++/nomve_fp_1.c | 2 +-\n .../gcc.target/arm/fp16-compile-none-1.c | 7 ---\n .../arm/mve/intrinsics/pr117814-2-f16.c | 30 +++++++++++\n .../arm/mve/intrinsics/pr117814-2-f32.c | 30 +++++++++++\n .../arm/mve/intrinsics/pr117814-3-f16.c | 21 ++++++++\n .../arm/mve/intrinsics/pr117814-3-f32.c | 21 ++++++++\n .../arm/mve/intrinsics/pr117814-4-f16.c | 23 ++++++++\n .../arm/mve/intrinsics/pr117814-f16.c | 22 ++++++++\n .../arm/mve/intrinsics/pr117814-f32.c | 22 ++++++++\n gcc/testsuite/lib/target-supports.exp | 54 +++++++++++++++++++\n 17 files changed, 242 insertions(+), 41 deletions(-)\n delete mode 100644 gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f32.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f32.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-4-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f32.c", "diff": "diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc\nindex 3bb2566f9a2f..b0bbb32644c5 100644\n--- a/gcc/config/arm/arm-builtins.cc\n+++ b/gcc/config/arm/arm-builtins.cc\n@@ -1685,9 +1685,7 @@ arm_init_fp16_builtins (void)\n arm_fp16_type_node = make_node (REAL_TYPE);\n TYPE_PRECISION (arm_fp16_type_node) = GET_MODE_PRECISION (HFmode);\n layout_type (arm_fp16_type_node);\n- if (arm_fp16_format)\n- (*lang_hooks.types.register_builtin_type) (arm_fp16_type_node,\n-\t\t\t\t\t \"__fp16\");\n+ (*lang_hooks.types.register_builtin_type) (arm_fp16_type_node, \"__fp16\");\n }\n \n void\ndiff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc\nindex 42b53cc05e77..b37c91c541bc 100644\n--- a/gcc/config/arm/arm-mve-builtins.cc\n+++ b/gcc/config/arm/arm-mve-builtins.cc\n@@ -410,8 +410,6 @@ register_builtin_types ()\n #include \"arm-mve-builtins.def\"\n for (unsigned int i = 0; i < NUM_VECTOR_TYPES; ++i)\n {\n- if (vector_types[i].requires_float && !TARGET_HAVE_MVE_FLOAT)\n-\tcontinue;\n tree eltype = scalar_types[i];\n tree vectype;\n if (eltype == boolean_type_node)\n@@ -433,18 +431,6 @@ register_builtin_types ()\n static void\n register_vector_type (vector_type_index type)\n {\n-\n- /* If the target does not have the mve.fp extension, but the type requires\n- it, then it needs to be assigned a non-dummy type so that functions\n- with those types in their signature can be registered. This allows for\n- diagnostics about the missing extension, rather than about a missing\n- function definition. */\n- if (vector_types[type].requires_float && !TARGET_HAVE_MVE_FLOAT)\n- {\n- acle_vector_types[0][type] = void_type_node;\n- return;\n- }\n-\n tree vectype = abi_vector_types[type];\n tree id = get_identifier (vector_types[type].acle_name);\n tree decl = build_decl (input_location, TYPE_DECL, id, vectype);\n@@ -470,13 +456,7 @@ register_builtin_tuple_types (vector_type_index type)\n {\n const vector_type_info* info = &vector_types[type];\n \n- /* If the target does not have the mve.fp extension, but the type requires\n- it, then it needs to be assigned a non-dummy type so that functions\n- with those types in their signature can be registered. This allows for\n- diagnostics about the missing extension, rather than about a missing\n- function definition. */\n- if (scalar_types[type] == boolean_type_node\n- || (info->requires_float && !TARGET_HAVE_MVE_FLOAT))\n+ if (scalar_types[type] == boolean_type_node)\n {\n for (unsigned int num_vectors = 2; num_vectors <= 4; num_vectors += 2)\n \tacle_vector_types[num_vectors >> 1][type] = void_type_node;\ndiff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h\nindex 5c543bf52466..d2384edb542b 100644\n--- a/gcc/config/arm/arm-opts.h\n+++ b/gcc/config/arm/arm-opts.h\n@@ -35,6 +35,7 @@\n */\n enum arm_fp16_format_type\n {\n+ ARM_FP16_FORMAT_DEFAULT = -1,\n ARM_FP16_FORMAT_NONE = 0,\n ARM_FP16_FORMAT_IEEE = 1,\n ARM_FP16_FORMAT_ALTERNATIVE = 2\ndiff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc\nindex 6df2fa02172c..5b2e5cb83469 100644\n--- a/gcc/config/arm/arm.cc\n+++ b/gcc/config/arm/arm.cc\n@@ -3923,13 +3923,19 @@ arm_option_reconfigure_globals (void)\n arm_arch_bf16 = bitmap_bit_p (arm_active_target.isa, isa_bit_bf16);\n \n arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);\n- if (arm_fp16_inst)\n+\n+ /* Set arm_fp16_format to IEEE if the target has fp16 support unless user\n+ forced ARM_FP16_FORMAT_NONE. */\n+ if (arm_fp16_inst && (arm_fp16_format != ARM_FP16_FORMAT_NONE))\n {\n if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)\n \terror (\"selected fp16 options are incompatible\");\n arm_fp16_format = ARM_FP16_FORMAT_IEEE;\n }\n \n+ if (arm_fp16_format == ARM_FP16_FORMAT_DEFAULT)\n+ arm_fp16_format = ARM_FP16_FORMAT_NONE;\n+\n arm_arch_cde = 0;\n arm_arch_cde_coproc = 0;\n int cde_bits[] = {isa_bit_cdecp0, isa_bit_cdecp1, isa_bit_cdecp2,\n@@ -29620,11 +29626,7 @@ arm_vector_mode_supported_p (machine_mode mode)\n return true;\n \n if (TARGET_HAVE_MVE\n- && (VALID_MVE_SI_MODE (mode) || VALID_MVE_PRED_MODE (mode)))\n- return true;\n-\n- if (TARGET_HAVE_MVE_FLOAT\n- && (mode == V2DFmode || mode == V4SFmode || mode == V8HFmode))\n+ && (VALID_MVE_MODE (mode) || VALID_MVE_PRED_MODE (mode)))\n return true;\n \n return false;\ndiff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt\nindex d5eeeae7eaef..caa08d120cef 100644\n--- a/gcc/config/arm/arm.opt\n+++ b/gcc/config/arm/arm.opt\n@@ -139,7 +139,7 @@ Target Var(TARGET_FLIP_THUMB) Undocumented\n Switch ARM/Thumb modes on alternating functions for compiler testing.\n \n mfp16-format=\n-Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE)\n+Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_DEFAULT)\n Specify the __fp16 floating-point format.\n \n Enum\ndiff --git a/gcc/config/arm/arm_mve_types.h b/gcc/config/arm/arm_mve_types.h\nindex 42e74666e80b..d1889c68ac53 100644\n--- a/gcc/config/arm/arm_mve_types.h\n+++ b/gcc/config/arm/arm_mve_types.h\n@@ -26,10 +26,8 @@\n #ifndef _GCC_ARM_MVE_TYPES_H\n #define _GCC_ARM_MVE_TYPES_H\n \n-#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */\n typedef __fp16 float16_t;\n typedef float float32_t;\n-#endif\n \n #pragma GCC arm \"arm_mve_types.h\"\n \ndiff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi\nindex 29742e26d8b9..e45e5cf81ae3 100644\n--- a/gcc/doc/sourcebuild.texi\n+++ b/gcc/doc/sourcebuild.texi\n@@ -2216,6 +2216,12 @@ the Half-precision floating-point instructions (HP), Floating-point Extension\n (FP) along with M-Profile Vector Extension (MVE). Some multilibs may be\n incompatible with these options.\n \n+@item arm_v8_1m_mve_nofp_ok\n+ARM target supports options to generate instructions from ARMv8.1-M\n+with the M-Profile Vector Extension (MVE) but without the\n+Half-precision floating-point instructions (HP) and Floating-point\n+Extension (FP). Some multilibs may be incompatible with these options.\n+\n @item arm_mve_hw\n Test system supports executing MVE instructions.\n \ndiff --git a/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c b/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c\nindex fd8c05b0eed4..4b91e0c6327b 100644\n--- a/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c\n+++ b/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c\n@@ -12,6 +12,6 @@\n void\n f1 (uint8x16_t v)\n {\n- vreinterpretq_f16 (v); /* { dg-error {ACLE function 'void vreinterpretq_f16\\(uint8x16_t\\)' requires ISA extension 'mve.fp'} } */\n+ vreinterpretq_f16 (v); /* { dg-error {ACLE function 'float16x8_t vreinterpretq_f16\\(uint8x16_t\\)' requires ISA extension 'mve.fp'} } */\n /* { dg-message {note: you can enable mve.fp by using the command-line option '-march', or by using the 'target' attribute or pragma} \"\" {target *-*-*} .-1 } */\n }\ndiff --git a/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c b/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c\ndeleted file mode 100644\nindex 9472249e2e2a..000000000000\n--- a/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c\n+++ /dev/null\n@@ -1,7 +0,0 @@\n-/* { dg-do compile } */\n-/* { dg-require-effective-target arm_fp16_none_ok } */\n-/* { dg-options \"-mfp16-format=none\" } */\n-\n-/* __fp16 type name is not recognized unless you explicitly enable it\n- by selecting -mfp16-format=ieee or -mfp16-format=alternative. */\n-__fp16 xx = 0.0; /* { dg-error \"unknown type name\" } */\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f16.c\nnew file mode 100644\nindex 000000000000..046cad030d7c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f16.c\n@@ -0,0 +1,30 @@\n+/* Check that we can compile if the target does not support floating-point, but\n+ we use a pragma to enable FP support locally. */\n+\n+/* { dg-require-effective-target arm_v8_1m_mve_nofp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_nofp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#pragma GCC target (\"arch=armv8.1-m.main+mve.fp\")\n+\n+/*\n+**foo:\n+**\t...\n+**\tvldrh.16\tq[0-9]+, \\[(?:ip|fp|r[0-9]+)\\](?:\t@.*|) \n+**\t...\n+*/\n+float16x8_t\n+foo (float16_t const *base)\n+{\n+ return vld1q_f16 (base);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f32.c\nnew file mode 100644\nindex 000000000000..6856e8e6a085\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f32.c\n@@ -0,0 +1,30 @@\n+/* Check that we can compile if the target does not support floating-point, but\n+ we use a pragma to enable FP support locally. */\n+\n+/* { dg-require-effective-target arm_v8_1m_mve_nofp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_nofp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#pragma GCC target (\"arch=armv8.1-m.main+mve.fp\")\n+\n+/*\n+**foo:\n+**\t...\n+**\tvldrw.32\tq[0-9]+, \\[(?:ip|fp|r[0-9]+)\\](?:\t@.*|)\n+**\t...\n+*/\n+float32x4_t\n+foo (float32_t const *base)\n+{\n+ return vld1q_f32 (base);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f16.c\nnew file mode 100644\nindex 000000000000..bcb0dd654163\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f16.c\n@@ -0,0 +1,21 @@\n+/* Check that we can compile if the target supports floating-point. */\n+\n+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_fp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+float16x8_t\n+foo (float16_t const *base)\n+{\n+ return vld1q_f16 (base);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f32.c\nnew file mode 100644\nindex 000000000000..7e02816d5055\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f32.c\n@@ -0,0 +1,21 @@\n+/* Check that we can compile if the target supports floating-point. */\n+\n+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_fp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+float32x4_t\n+foo (float32_t const *base)\n+{\n+ return vld1q_f32 (base);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-4-f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-4-f16.c\nnew file mode 100644\nindex 000000000000..b266f1b94e0c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-4-f16.c\n@@ -0,0 +1,23 @@\n+/* Check that -mfp16-format=none works. */\n+\n+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_fp } */\n+/* { dg-additional-options \"-O2 -mfp16-format=none\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+float16x8_t\n+foo (float16_t const *base)\n+{\n+ return vld1q_f16 (base);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+/* { dg-final { scan-assembler-not {eabi_attribute 38,} } } */\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f16.c\nnew file mode 100644\nindex 000000000000..88930c1a3eb6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f16.c\n@@ -0,0 +1,22 @@\n+/* Check that we get an error if the target does not support floating-point: we\n+ force +mve to cancel a possible implicit +mve.fp. */\n+\n+/* { dg-require-effective-target arm_v8_1m_mve_nofp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_nofp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+float16x8_t\n+foo (float16_t const *base)\n+{\n+ return vld1q_f16 (base); /* { dg-error {ACLE function '.*vld1q_f16.*' requires ISA extension 'mve.fp'} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f32.c\nnew file mode 100644\nindex 000000000000..814e781fa5d8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f32.c\n@@ -0,0 +1,22 @@\n+/* Check that we get an error if the target does not support floating-point: we\n+ force +mve to cancel a possible implicit +mve.fp. */\n+\n+/* { dg-require-effective-target arm_v8_1m_mve_nofp_ok } */\n+/* { dg-add-options arm_v8_1m_mve_nofp } */\n+/* { dg-additional-options \"-O2\" } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+float32x4_t\n+foo (float32_t const *base)\n+{\n+ return vld1q_f32 (base); /* { dg-error {ACLE function '.*vld1q_f32.*' requires ISA extension 'mve.fp'} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex 4ee8d12362de..504c9c27cd7a 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -6940,6 +6940,60 @@ proc add_options_for_arm_v8_1m_mve { flags } {\n return \"$flags $et_arm_v8_1m_mve_flags\"\n }\n \n+# Return 1 if the target supports ARMv8.1-M MVE without floating point\n+# instructions, 0 otherwise. The test is valid for ARM.\n+# Record the command line options needed.\n+\n+proc check_effective_target_arm_v8_1m_mve_nofp_ok_nocache { } {\n+ global et_arm_v8_1m_mve_nofp_flags\n+ set et_arm_v8_1m_mve_nofp_flags \"\"\n+\n+ if { ![istarget arm*-*-*] } {\n+\treturn 0;\n+ }\n+\n+ # Iterate through sets of options to find the compiler flags that\n+ # need to be added to the -march option.\n+ foreach flags {\n+\t\"\"\n+\t\"-mfloat-abi=softfp\"\n+\t\"-mfpu=auto -mcpu=unset -march=armv8.1-m.main+mve\"\n+\t\"-mfpu=auto -mcpu=unset -march=armv8.1-m.main+mve -mfloat-abi=softfp\"\n+ } {\n+\tif { [check_no_compiler_messages_nocache \\\n+\t\t arm_v8_1m_mve_ok object {\n+\t #if !defined (__ARM_FEATURE_MVE)\n+\t #error \"__ARM_FEATURE_MVE not defined\"\n+\t #endif\n+\t #if (__ARM_FEATURE_MVE & 2)\n+\t #error \"__ARM_FEATURE_MVE for floating point defined\"\n+\t #endif\n+\t #if __ARM_BIG_ENDIAN\n+\t #error \"MVE intrinsics are not supported in Big-Endian mode.\"\n+\t #endif\n+\t #include <arm_mve.h>\n+\t} \"$flags -mthumb\"] } {\n+\t set et_arm_v8_1m_mve_nofp_flags \"$flags -mthumb --save-temps\"\n+\t return 1\n+\t}\n+ }\n+\n+ return 0;\n+}\n+\n+proc check_effective_target_arm_v8_1m_mve_nofp_ok { } {\n+ return [check_cached_effective_target arm_v8_1m_mve_nofp_ok \\\n+\t\tcheck_effective_target_arm_v8_1m_mve_nofp_ok_nocache]\n+}\n+\n+proc add_options_for_arm_v8_1m_mve_nofp { flags } {\n+ if { ! [check_effective_target_arm_v8_1m_mve_nofp_ok] } {\n+\treturn \"$flags\"\n+ }\n+ global et_arm_v8_1m_mve_nofp_flags\n+ return \"$flags $et_arm_v8_1m_mve_nofp_flags\"\n+}\n+\n proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {\n return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \\\n \t\tcheck_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]\n", "prefixes": [ "v2", "02/14" ] }