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GET /api/patches/2226867/?format=api
{ "id": 2226867, "url": "http://patchwork.ozlabs.org/api/patches/2226867/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.3@forge-stage.sourceware.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.3@forge-stage.sourceware.org>", "list_archive_url": null, "date": "2026-04-22T19:01:37", "name": "[v2,03/14] arm: doc: Update documentation on half-precision support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "03eddaacb1c293e33389d436a82fa44ab4254bb5", "submitter": { "id": 92734, "url": "http://patchwork.ozlabs.org/api/people/92734/?format=api", "name": "Christophe Lyon via Sourceware Forge", "email": "forge-bot+clyon@forge-stage.sourceware.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.3@forge-stage.sourceware.org/mbox/", "series": [ { "id": 501104, "url": "http://patchwork.ozlabs.org/api/series/501104/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501104", "date": "2026-04-22T19:01:35", "name": "arm: [MVE intrinsics] rework vpnot, vgetq_lane, vsetq_lane, vuninitialized and scalar shifts", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501104/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226867/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226867/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org", "sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org", "server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1BK52QFDz1yD5\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 06:53:45 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 9F95B4E57160\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 20:30:36 +0000 (GMT)", "from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id 952FB409BE8D\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 19:02:46 +0000 (GMT)", "from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id 5EA2843609;\n Wed, 22 Apr 2026 19:02:46 +0000 (UTC)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 9F95B4E57160", "OpenDKIM Filter v2.11.0 sourceware.org 952FB409BE8D" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 952FB409BE8D", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 952FB409BE8D", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776884566; cv=none;\n b=xzQOq7zmOfBcM0nV9Qv6DM362l645nY8pGABEwITrA9/PNvvLsFhCYq5zbgtz7+z2Bg0YQF9emuJqOPjsl8Eg5gIGbYMLKowqjndakufyUb88dQypqFW21QPzM9vJ7R+LEnz4obwX+Br/i81j73yr1oEoWSkYMT6mqJJIUSn7zc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776884566; c=relaxed/simple;\n bh=2oe5APksRrWuHeGqAiOKKpWE7iqFvcny6ZTxp32JIlI=;\n h=From:Date:Subject:To:Message-ID;\n b=tp2LK9PD8aCP3RtML99uRYL4kOMiby2iWRN5Q2PPLgjwfLZHzFfJ7BTA/L/ZuBcjm6XNDrgjq0zKUximPKWj8bBLnClNK8kV4GnSTIv/zxZHU/k0FNafGGbMO2HLDPMGTa1PBLl+C0W4S2pf3BAd4WuiaL+Q64bqO3GnUw7cPY0=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Christophe Lyon via Sourceware Forge\n <forge-bot+clyon@forge-stage.sourceware.org>", "Date": "Wed, 22 Apr 2026 19:01:37 +0000", "Subject": "[PATCH v2 03/14] arm: doc: Update documentation on half-precision\n support", "To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>", "Cc": "sloosemore@baylibre.com", "Message-ID": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.3@forge-stage.sourceware.org>", "X-Mailer": "batrachomyomachia", "X-Pull-Request-Organization": "gcc", "X-Pull-Request-Repository": "gcc-TEST", "X-Pull-Request": "https://forge.sourceware.org/gcc/gcc-TEST/pulls/121", "References": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org>", "In-Reply-To": "\n <bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org>", "X-Patch-URL": "\n https://forge.sourceware.org/clyon/gcc-TEST/commit/360badda7fb003ef845c57b3c8eace46f0492746", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Reply-To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>,\n sloosemore@baylibre.com, clyon@gcc.gnu.org", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Christophe Lyon <christophe.lyon@linaro.org>\n\nThe previous patch makes __fp16 always available on arm (using\n-mfp16-format is no longer needed), so the documentation needs an\nupdate.\n\nIn the process, clarify the peculiarities of __fp16 on arm, and\nreorder information to make it easier to understand.\n\ngcc/ChangeLog:\n\t* doc/extend.texi (Half-precision Floating-point): __fp16 is now\n\talways available on arm. Move x86 paragraph closer to the rest of\n\tthe x86 information, and make it use present tense.\n---\n gcc/doc/extend.texi | 118 +++++++++++++++++++++++++++-----------------\n 1 file changed, 74 insertions(+), 44 deletions(-)", "diff": "diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 94b76b75565c..b8a2afb6060e 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -300,49 +300,19 @@ typedef _Complex float __attribute__((mode(IC))) _Complex_ibm128;\n @node Half-Precision\n @subsection Half-Precision Floating Point\n @cindex half-precision floating point\n-@cindex @code{__fp16} data type\n-@cindex @code{__Float16} data type\n+@cindex @code{_Float16} data type\n \n-On ARM and AArch64 targets, GCC supports half-precision (16-bit) floating\n-point via the @code{__fp16} type defined in the ARM C Language Extensions.\n-On ARM systems, you must enable this type explicitly with the\n-@option{-mfp16-format} command-line option in order to use it.\n-On x86 targets with SSE2 enabled, GCC supports half-precision (16-bit)\n-floating point via the @code{_Float16} type. For C++, x86 provides a builtin\n-type named @code{_Float16} which contains same data format as C.\n+GCC supports half-precision (16-bit) floating point on several targets.\n \n-ARM targets support two incompatible representations for half-precision\n-floating-point values. You must choose one of the representations and\n-use it consistently in your program.\n+It is recommended that portable code use the @code{_Float16} type defined\n+by ISO/IEC TS 18661-3:2015. @xref{Floating Types}.\n \n-Specifying @option{-mfp16-format=ieee} selects the IEEE 754-2008 format.\n-This format can represent normalized values in the range of @math{2^{-14}} to 65504.\n-There are 11 bits of significand precision, approximately 3\n-decimal digits.\n+Some targets have peculiarities as follows.\n \n-Specifying @option{-mfp16-format=alternative} selects the ARM\n-alternative format. This representation is similar to the IEEE\n-format, but does not support infinities or NaNs. Instead, the range\n-of exponents is extended, so that this format can represent normalized\n-values in the range of @math{2^{-14}} to 131008.\n-\n-The GCC port for AArch64 only supports the IEEE 754-2008 format, and does\n-not require use of the @option{-mfp16-format} command-line option.\n-\n-The @code{__fp16} type may only be used as an argument to intrinsics defined\n-in @code{<arm_fp16.h>}, or as a storage format. For purposes of\n-arithmetic and other operations, @code{__fp16} values in C or C++\n-expressions are automatically promoted to @code{float}.\n-\n-The ARM target provides hardware support for conversions between\n-@code{__fp16} and @code{float} values\n-as an extension to VFP and NEON (Advanced SIMD), and from ARMv8-A provides\n-hardware support for conversions between @code{__fp16} and @code{double}\n-values. GCC generates code using these hardware instructions if you\n-compile with options to select an FPU that provides them;\n-for example, @option{-mfpu=neon-fp16 -mfloat-abi=softfp},\n-in addition to the @option{-mfp16-format} option to select\n-a half-precision format.\n+@cindex @code{__fp16} data type\n+On Arm and AArch64 targets, GCC supports half-precision (16-bit)\n+floating point via the @code{__fp16} type defined in the Arm\n+C-Language Extensions (ACLE).\n \n Language-level support for the @code{__fp16} data type is\n independent of whether GCC generates code using hardware floating-point\n@@ -350,17 +320,77 @@ instructions. In cases where hardware support is not specified, GCC\n implements conversions between @code{__fp16} and other types as library\n calls.\n \n-It is recommended that portable code use the @code{_Float16} type defined\n-by ISO/IEC TS 18661-3:2015. @xref{Floating Types}.\n+Arm targets support two mutually incompatible half-precision\n+floating-point formats:\n+\n+@itemize @bullet\n+@item\n+A format that implements IEEE 754-2008 16-bit floating point types,\n+enabled with the @option{-mfp16-format=ieee} command-line option; this\n+format can represent normalized values in the range of @math{2^{-14}}\n+to 65504. There are 11 bits of significand precision, approximately 3\n+decimal digits.\n+\n+@item\n+An alternative format that sacrifices NaNs and infinity values, but\n+has a larger range of values that can be represented: @math{2^{-14}}\n+to 131008. This is enabled with the\n+@option{-mfp16-format=alternative} option.\n+@end itemize\n+\n+You must choose one of the formats and use it consistently in your\n+program.\n+\n+GCC only supports the @samp{alternative} format on implementations\n+that support it in hardware; there is no support for conversions to\n+and from this format using library functions. Furthermore, you cannot\n+link together code compiled with one format and code compiled for the\n+other. GCC also supports the @option{-mfp16-format=none} option,\n+which disables all support for half-precision floating-point types.\n+Code compiled with this option can be linked safely with code compiled\n+for either format.\n+\n+The Arm architecture extension @code{FEAT_FP16} (enabled, for example,\n+with @option{-march=armv8.2-a+fp16}, or\n+@option{-march=armv8.1-m.main+mve.fp}) defines data processing\n+instructions that only support the @samp{ieee} format. The compiler\n+rejects attempts to use the @samp{alternative} format when this\n+architecture extension is enabled.\n+\n+Note that the ACLE has deprecated use of the @samp{alternative} format\n+and recommends that only the @samp{ieee} format be used.\n+\n+The default is to compile with @option{-mfp16-format=ieee}.\n+\n+In C and C++ there are two related data types:\n+@itemize @bullet\n+@item\n+\n+@code{__fp16}, as defined by the Arm C-Language Extensions (ACLE).\n+This can be used to hold either format;\n+\n+@item\n+@code{_Float16}, which is defined by ISO/IEC TS 18661-3:2015. This is\n+only defined when the format selected is @samp{ieee}.\n+@end itemize\n+\n+The GCC port for AArch64 only supports the IEEE 754-2008 format, and\n+does not have the @option{-mfp16-format} command-line option.\n+\n+\n+On x86 targets with SSE2 enabled, GCC supports half-precision (16-bit)\n+floating point via the @code{_Float16} type. For C++, x86 provides a builtin\n+type named @code{_Float16} which contains same data format as C.\n+\n \n On x86 targets with SSE2 enabled, without @option{-mavx512fp16},\n-all operations will be emulated by software emulation and the @code{float}\n+all operations are emulated by software emulation and the @code{float}\n instructions. The default behavior for @code{FLT_EVAL_METHOD} is to keep the\n intermediate result of the operation as 32-bit precision. This may lead to\n inconsistent behavior between software emulation and AVX512-FP16 instructions.\n-Using @option{-fexcess-precision=16} will force round back after each operation.\n+Using @option{-fexcess-precision=16} forces round back after each operation.\n \n-Using @option{-mavx512fp16} will generate AVX512-FP16 instructions instead of\n+Using @option{-mavx512fp16} generates AVX512-FP16 instructions instead of\n software emulation. The default behavior of @code{FLT_EVAL_METHOD} is to round\n after each operation. The same is true with @option{-fexcess-precision=standard}\n and @option{-mfpmath=sse}. If there is no @option{-mfpmath=sse},\n", "prefixes": [ "v2", "03/14" ] }