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GET /api/patches/2226865/?format=api
{ "id": 2226865, "url": "http://patchwork.ozlabs.org/api/patches/2226865/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-5-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422204335.23116-5-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T20:43:32", "name": "[v2,4/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ssidsize\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "faa2e41cfa4d02455812bdca936f87a3f0617f7f", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-5-nathanc@nvidia.com/mbox/", "series": [ { "id": 501105, "url": "http://patchwork.ozlabs.org/api/series/501105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105", "date": "2026-04-22T20:43:28", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501105/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226865/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226865/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=i6OJFDK3;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 22 Apr 2026 16:44:17 -0400", "from CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14)\n by SA1PR12MB7368.namprd12.prod.outlook.com (2603:10b6:806:2b7::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.8; Wed, 22 Apr\n 2026 20:43:56 +0000", "from CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e]) by CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e%6]) with mapi id 15.20.9846.016; Wed, 22 Apr 2026\n 20:43:56 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=ihPg3EZQ0I48cXRKIfXNls+9bDhJnr1OvF+Q6VvT+UJE8l6dzRljdHw6Kzs0y8goi+yrsiohNiuyIdtfM8xAI1vHeqDswDyNxTdK+d27N8N1L47nZRhpdH3wgWqjNTYV0J06+C1iCSnyH51bHcRZl71axB/pMSbWo8j3kwrs4i9cPqUu5JYkcPqkRM2v2+MibtNgWJ/MCaP9bMRZ6ENkOycazF3w5mPT1BvGcW61sTByyXdepAPUmPnQyMUt9qsDXejI18vg2jc665538DeoVQ2QdnVJ2tJ3B86J/Nc3ju3JCXO29CyLWtOGHEWqu3+RU7rAPh58z+er6r8HShzhNw==", "ARC-Message-Signature": "i=1; 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Derive host values using IOMMU_GET_HW_INFO,\nretrieving SSID size from IDR1. When the auto SSID size is resolved\nto a non-zero value, PASID capability is advertised to the vIOMMU\nand accelerated use cases such as Shared Virtual Addressing (SVA)\nare supported.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 18 ++++++++++++++++--\n hw/arm/smmuv3.c | 20 ++++++++++----------\n 2 files changed, 26 insertions(+), 12 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 98c2cdcb5e..d13d15a11d 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -62,6 +62,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n FIELD_EX32(info->idr[3], IDR3, RIL));\n }\n \n+ if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n+ /* Store for get_viommu_flags() to determine PASID support */\n+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,\n+ FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -822,6 +828,13 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque,\n }\n }\n \n+static inline bool smmuv3_pasid_supported(SMMUv3State *s)\n+{\n+ return s->ssidsize > SSID_SIZE_MODE_0 ||\n+ (s->ssidsize == SSID_SIZE_MODE_AUTO &&\n+ FIELD_EX32(s->idr[1], IDR1, SSIDSIZE));\n+}\n+\n static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)\n {\n /*\n@@ -834,7 +847,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)\n SMMUState *bs = opaque;\n SMMUv3State *s = ARM_SMMUV3(bs);\n \n- if (s->ssidsize > SSID_SIZE_MODE_0) {\n+ if (smmuv3_pasid_supported(s)) {\n flags |= VIOMMU_FLAG_PASID_SUPPORTED;\n }\n return flags;\n@@ -974,7 +987,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n smmuv3_accel_as_init(s);\n \n if (s->ats == ON_OFF_AUTO_AUTO ||\n- s->ril == ON_OFF_AUTO_AUTO) {\n+ s->ril == ON_OFF_AUTO_AUTO ||\n+ s->ssidsize == SSID_SIZE_MODE_AUTO) {\n s->s_accel->auto_mode = true;\n }\n \ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex b7aa4122eb..07025245e2 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -626,7 +626,10 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,\n }\n \n /* Multiple context descriptors require SubstreamID support */\n- if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {\n+ if ((s->ssidsize == SSID_SIZE_MODE_0 ||\n+ (s->ssidsize == SSID_SIZE_MODE_AUTO &&\n+ !FIELD_EX32(s->idr[1], IDR1, SSIDSIZE))) &&\n+ STE_S1CDMAX(ste) != 0) {\n qemu_log_mask(LOG_UNIMP,\n \"SMMUv3: multiple S1 context descriptors require SubstreamID support. \"\n \"Configure ssidsize > 0 (requires accel=on)\\n\");\n@@ -1972,10 +1975,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n- error_setg(errp, \"ssidsize auto mode is not supported\");\n- return false;\n- }\n if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {\n error_setg(errp, \"QEMU SMMUv3 model only implements 44 and 48 bit\"\n \"OAS; other OasMode values are not supported\");\n@@ -1996,7 +1995,8 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n return false;\n }\n if (s->ssidsize > SSID_SIZE_MODE_0) {\n- error_setg(errp, \"ssidsize can only be set if accel=on\");\n+ error_setg(errp, \"ssidsize can only be greater than 0 \"\n+ \"bits if accel=on\");\n return false;\n }\n return true;\n@@ -2177,11 +2177,11 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"are 44 or 48 bits. Defaults to 44 bits. oas=auto is not \"\n \"supported.\");\n object_class_property_set_description(klass, \"ssidsize\",\n- \"Number of bits used to represent SubstreamIDs (SSIDs). \"\n+ \"Set number of bits used to represent SubstreamIDs (SSIDs). \"\n+ \"Valid values are 0-20 and auto. Defaults to 0. \"\n \"A value of N allows SSIDs in the range [0 .. 2^N - 1]. \"\n- \"Valid range is 0-20, where 0 disables SubstreamID support. \"\n- \"Defaults to 0. A value greater than 0 is required to enable \"\n- \"PASID support. ssidsize=auto is not supported.\");\n+ \"A value of 0 disables SubstreamID support. A value greater \"\n+ \"than 0 is required to enable PASID support.\");\n }\n \n static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,\n", "prefixes": [ "v2", "4/7" ] }