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GET /api/patches/2226863/?format=api
{ "id": 2226863, "url": "http://patchwork.ozlabs.org/api/patches/2226863/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-4-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422204335.23116-4-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T20:43:31", "name": "[v2,3/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ril\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "91ed48eea37d416b3f21aa5a51d299b39f3587a4", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-4-nathanc@nvidia.com/mbox/", "series": [ { "id": 501105, "url": "http://patchwork.ozlabs.org/api/series/501105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105", "date": "2026-04-22T20:43:28", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501105/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226863/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226863/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=TghO4neK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 22 Apr 2026 16:44:18 -0400", "from CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14)\n by SA1PR12MB7368.namprd12.prod.outlook.com (2603:10b6:806:2b7::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.8; Wed, 22 Apr\n 2026 20:43:50 +0000", "from CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e]) by CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e%6]) with mapi id 15.20.9846.016; Wed, 22 Apr 2026\n 20:43:50 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=ZwbuIW3Es7/fzHgHrgAjQ+jTC2mJBkIqh4ZWdNHqabOsESXE1qjsAOGBfKuHmWGd6/KyghF7W+8XcFf2J7wHzcm8YE+Q3r0x7QKaug+KIgc6Jr0PrToBub2BPIpYDL1PNR/+JnQtz41V4BRu0HEVPi4eyA9z+vNEVWpBfDUsmcB2ai9qeD9kyOFvSzcKKLAjlv0Pdfikt56alAGz3X4qO2jVmc4HvlwxW6H9mllJXBSc2ut4X7YOXQmCZrFqMlcA0LRO+ACgQ/c8ETdUOM9TqUsaRcrJSZm2NnBxvZvQWL6vsUUyzOVQX1rt/E+/V7dON69q1cWv6Tdw7h9Xi2ItzQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=6II0V/ud9FsVOLFHcitMDxxX7hBgvG10QumQ4ju5kBc=;\n b=rNesCzP5OzeLVCVAPgP3s2PNynOpWRw4dTCxmpeYPSd1ue9dQ8SZcw0ALJeSHQR+WeW1k1Do96/1jM+aozyikyw1vo/njxwMiLgNtX+NPFyg/kSuwOPF2ua5anDk37sCdFGRXUXcetKpZS8+TTaYxoaDHEeD/U/TA3AZcrgdUlJxS3gUzT+WPargSPrU6iX28GIvb7jso7+lTw2t7vSDYHfx1sDyng8WyOToninQI8aPN1K0EQGYTXQRfbAyoCmhZhg3kZoq8zmGqKtsThWaYYhiY9sIKcoIYKFzVSA5unS0FB4BqpJtlCv/9Vrf8YcO1Q44IUH04muoiUpZmeE5CQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=6II0V/ud9FsVOLFHcitMDxxX7hBgvG10QumQ4ju5kBc=;\n b=TghO4neKpkl5b8OMdF43j756BYLbtpQteqdmBYKqhFf3cFDCwwap7nfvL/iCQ+OOJuU1kkkDI8tnbaeoAPEkAapRbqvrTOTbzbDbzhazvRlp3iRDYCpFERhRWtDtfu6t0Ud9bX5l03VAyR8jgJpEcskWUuzqnMaEYF9Ooc8C8tlQb4NaZVF1KJ52yhw7+7p4EH4bjXhdQzGoU44Ra2H3m8/+YX/PoTx/hz2a56VXz/YpbcIZnyGQ4QXUxqsJkYv0h1HIbfCU+5NuqKTIkTFUWKD+qw/bWuYUVeCHesFj55DpteMymrYgNBk6xjz7HuXrWLtDJE+OgN3rz+rAcVwuhg==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Eric Auger <eric.auger@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH v2 3/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ril\"", "Date": "Wed, 22 Apr 2026 13:43:31 -0700", "Message-ID": "<20260422204335.23116-4-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260422204335.23116-1-nathanc@nvidia.com>", "References": "<20260422204335.23116-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR03CA0229.namprd03.prod.outlook.com\n (2603:10b6:a03:39f::24) To CY3PR12MB9555.namprd12.prod.outlook.com\n (2603:10b6:930:10a::14)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY3PR12MB9555:EE_|SA1PR12MB7368:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d533467b-1c30-42c4-e499-08dea0afdbc4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n If1qPlOF4ISJYZaHwfDXGnfPz+vVgxrR/e6yMmFoQ7TtMOY017wmToibrKNBIz7wQq0QZJYwaIIl1pYudKh1pcccov1vg5kFonOa6S8POQ7Pnau8g0ipQUL3sc3XJLRh44KuesPgZ+Z41EQ7SOtXGYCXghDG4TvTF0Wmthhj/8hTuLJ/Xfyk1EH4G9V09kEQoW+oW7G9vqX2NvbZ3fPqcwClEd5WjDbs2bqBLs1JscleBVTIxAmPchKFYkTvOEI3EBeCL7M/5e1ZL+4tap4TRR7ge0U7MFNhDDkfwZmc0qJh4qLl5FPW8Z9dLm8KVyIBfUUYGiUzH3QRL+5dajBHhrH/O3I45wKzfgyOrK2ZYXJQYfweCfeFfgS2YaI3scEvHp7JPeqitrxfV2qeN/PrUq11qE1nSgz9PO6sgpZyBKuqFWmTMKEr39T+xgdmRAiWX+IQkivfb9Ot0OoyD9MRql+jUyiR4y1HhXHgvOCz+jS5wK3U9R4SlwmZumMMdTu6wXGZ7T1iZPFU0ECSt6i8jMwLMXO5abT+AXvkf18Y4nAFPmvDu9nGQXDkXB0y62vyekkAInwWQUfaWyQNGIgmh8ejIH+4Dv7jLu6eF1rwgGn02lwEKlIJIx7cC+1jIOoHt1HPGnxKXPJKb3mCoOdzndyW2+O4m2AK3yw7NIYuLdYBugLTHFrXIFh/8Sve8dRvVuElCiWlbZtj7pEZe0EgWFzZTWlfhe8/6x6pBoHKzN8=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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Derive host values using\nIOMMU_GET_HW_INFO, retrieving RIL capability from IDR3.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 8 +++++++-\n hw/arm/smmuv3.c | 10 ++++------\n 2 files changed, 11 insertions(+), 7 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex b42d189d29..98c2cdcb5e 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -57,6 +57,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n FIELD_EX32(info->idr[0], IDR0, ATS));\n }\n \n+ if (s->ril == ON_OFF_AUTO_AUTO) {\n+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL,\n+ FIELD_EX32(info->idr[3], IDR3, RIL));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -968,7 +973,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n bs->iommu_ops = &smmuv3_accel_ops;\n smmuv3_accel_as_init(s);\n \n- if (s->ats == ON_OFF_AUTO_AUTO) {\n+ if (s->ats == ON_OFF_AUTO_AUTO ||\n+ s->ril == ON_OFF_AUTO_AUTO) {\n s->s_accel->auto_mode = true;\n }\n \ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 5671649fee..b7aa4122eb 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1972,10 +1972,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->ril == ON_OFF_AUTO_AUTO) {\n- error_setg(errp, \"ril auto mode is not supported\");\n- return false;\n- }\n if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n error_setg(errp, \"ssidsize auto mode is not supported\");\n return false;\n@@ -2168,8 +2164,10 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Enable SMMUv3 accelerator support. Allows host SMMUv3 to be \"\n \"configured in nested mode for vfio-pci dev assignment\");\n object_class_property_set_description(klass, \"ril\",\n- \"Disable range invalidation support (for accel=on). ril=auto \"\n- \"is not supported.\");\n+ \"Enable/disable range invalidation support (for accel=on). \"\n+ \"Valid values are on, off, and auto. Defaults to on. \"\n+ \"Please enable if host platform supports RIL, and disable if \"\n+ \"host platform does not support RIL.\");\n object_class_property_set_description(klass, \"ats\",\n \"Enable/disable ATS support (for accel=on). \"\n \"Valid values are on, off, and auto. Defaults to off. \"\n", "prefixes": [ "v2", "3/7" ] }