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GET /api/patches/2226862/?format=api
{ "id": 2226862, "url": "http://patchwork.ozlabs.org/api/patches/2226862/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-6-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422204335.23116-6-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T20:43:33", "name": "[v2,5/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"oas\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b79979f107aa9a3807677a3616ce42d03f6ae90a", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-6-nathanc@nvidia.com/mbox/", "series": [ { "id": 501105, "url": "http://patchwork.ozlabs.org/api/series/501105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105", "date": "2026-04-22T20:43:28", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501105/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226862/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226862/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=SXxSQZqo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 22 Apr 2026 16:44:21 -0400", "from CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14)\n by SA1PR12MB7368.namprd12.prod.outlook.com (2603:10b6:806:2b7::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.8; Wed, 22 Apr\n 2026 20:43:58 +0000", "from CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e]) by CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e%6]) with mapi id 15.20.9846.016; Wed, 22 Apr 2026\n 20:43:58 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=aHVLAtJ6iYEiuaBMuD3AygYop1rTq43w9WKxRsGEeia2bJOax7t+ZwYyrPGc4gv4T2Na4f7N8YQrfczxLiyFcRUUfRNhC5mD/F9g8Vkd0xHTBlTEck0Qyn2+JqUD+8KllF/M3/bAJ6UHIMx0HZgLKfzg5hwKXajdHK9RqvCmWL2MxpSLDeZSp6jp7SESB4g9ADBNLDPYf3l+O+EWL9Hc6TL13croFLJ7x32kkJP7NI9faFOVJhqO3OHBtel/st2TDYkf7aoPYVy1wZff7LsOnzWrxYiUEE07sI5IkrHNbWmpy8w7WHIS7hZX2IaaOroEJh6QoogF05S9fheZo/ft/Q==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=B++aQLhUTz4Ffo+zFAUhsq3Jls/PqCHMEqF/PwDmVNA=;\n b=Bi+KjqPNFKxeontxL9o+T8/W3M8JGd7XvbDqKsbAKGCxdZg6qw/WBXcl5KV1E/LX0B1rvz4PMxnex3XBvsGOwfL+6V3/NVK4p9iSgFrbY3r/6LJzemHm+/s/hj3B5O3+b0yJP7nYuiQaiywtR5Jchi4gaIoYayQvuM5fFF0Z3f/t92W7Mg9zuO72t0vgdP35/oHfwDTMzaNN4T1X+9PY69nMxxx0c8N17EG81NUCVwb9nmY6cA/cVL4w3K+LL4rdB1kXsSngZnJfIPW/v9e865fb8lSpEcma2zWKnwiSi7qHJ9PO+PbH+801SWT2pl6VErBSejic7cxmkK8sKJxgdw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=B++aQLhUTz4Ffo+zFAUhsq3Jls/PqCHMEqF/PwDmVNA=;\n b=SXxSQZqorBHXWq+6IPxKl3GfiFJUf14m62WRM5xhumSke9IzqZiFlu6QtyeVZdJJjdAKiLK9TKYU+shXbwBFFyetl5je74+tBhLgxYK0+kfERT1Zz4OBuiV/LWid4k+fvv7oQZeQOWn/vbz2Txk0T3Jdi3mSFqVMdcECb0MusG4ehHXv1nV0BqwXKdMMBirKUer2tiIwezSyeDrg86UPg5cvgncrrlf2KcaJ7NI53Ur3s023o4hewP7bcQuTuH4nSLKMzcOqgFcBCCYHxYmTlO9v/kGhSB0MaatVulTVBfHCyMspmeQcQMPTyK/hB+V8O2VRmIeRJ1Damxsl9X0qSA==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Eric Auger <eric.auger@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH v2 5/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"oas\"", "Date": "Wed, 22 Apr 2026 13:43:33 -0700", "Message-ID": "<20260422204335.23116-6-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260422204335.23116-1-nathanc@nvidia.com>", "References": "<20260422204335.23116-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BY1P220CA0019.NAMP220.PROD.OUTLOOK.COM\n (2603:10b6:a03:5c3::15) To CY3PR12MB9555.namprd12.prod.outlook.com\n (2603:10b6:930:10a::14)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY3PR12MB9555:EE_|SA1PR12MB7368:EE_", "X-MS-Office365-Filtering-Correlation-Id": "726ffc82-71b5-4a07-b81e-08dea0afe0a6", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n PfAXYG3+LtaevURC4mLxIRTTDuAt0Qajj7h3RoLOZjT2YJBcd34d9ri90ITt0ANZ84ubmP9bgU0adCRTrMFZ4325JK6Js6fthEzQSTfySPYfStSKp/qmbBkspPF9Pc1YGC4R75yitJVojqGGel7WUdORf7GbVaV8AqLecAD5oCXfIKyj9eblFY/jIvuAzEp+M+yRU/61Dxbp2qrWU9QJRbJtXCmelbPhBoOqgnvchXnjGxNiCAOHsejP5gMR4qYLpuf/3tES6LxaS7xoq6oOc2g9hS8DLKz/oa4KYz4uwWROVbsNEPB18orIAzEVFPs5NLOFURT9d48pTPtBGwBTGmcVknn5WUTsOQ4/Z6AJk6ySIyk/By/ft7OxM8JdGXZs+wG0xmoDNzDVEYfZFYUGApdPaN7AkmLgTq3NX9pCEgG9R55OL3WOJQaawXgh6eI6nWKlvpxAh9yVXooQjmJU0FEsxUYL6lmvsxD4hwzkektTCdoiRjuOVWhPUfjpHsBik9DwWPxSoLvTvurZFBXHwVyf+IWYkTXl4c+GzSaPPV/gomH+WDVGUz9QZOgC/63VpBTDQ++WIcvR5MkMOV39yAQXHYCeTmNQaETJuPA4p7sY0zQSIvtG2UNaCF2NSc1CUvPH3BsIATNjjhjCqPVaiLA1EVr8CH9+TqW/J/pVUU20RhFkGXApnt+b0ylOCykhYZe6ZWKA7H70RRRO7XGETwVzUgCNb+wP0RqzldNjecc=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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Derive host values using IOMMU_GET_HW_INFO, retrieving\nOAS from IDR5.\n\nThis keeps the OAS value advertised by the virtual SMMU compatible with\nthe capabilities of the host SMMUv3, so that the intermediate physical\naddresses (IPA) consumed by host SMMU for stage-2 translation do not\nexceed the host's max supported IPA size.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 8 +++++++-\n hw/arm/smmuv3.c | 15 ++++++++-------\n 2 files changed, 15 insertions(+), 8 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex d13d15a11d..f45e268bde 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -68,6 +68,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));\n }\n \n+ if (s->oas == OAS_MODE_AUTO) {\n+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS,\n+ FIELD_EX32(info->idr[5], IDR5, OAS));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -988,7 +993,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n \n if (s->ats == ON_OFF_AUTO_AUTO ||\n s->ril == ON_OFF_AUTO_AUTO ||\n- s->ssidsize == SSID_SIZE_MODE_AUTO) {\n+ s->ssidsize == SSID_SIZE_MODE_AUTO ||\n+ s->oas == OAS_MODE_AUTO) {\n s->s_accel->auto_mode = true;\n }\n \ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 07025245e2..39a6f72938 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1975,9 +1975,11 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {\n- error_setg(errp, \"QEMU SMMUv3 model only implements 44 and 48 bit\"\n- \"OAS; other OasMode values are not supported\");\n+ if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48 &&\n+ s->oas != OAS_MODE_AUTO) {\n+ error_setg(errp, \"QEMU SMMUv3 model only implements auto, \"\n+ \"44 bit, or 48 bit OAS. Other OasMode values are \"\n+ \"not supported.\");\n return false;\n }\n \n@@ -1991,7 +1993,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n return false;\n }\n if (s->oas > OAS_MODE_44) {\n- error_setg(errp, \"OAS must be 44 bits when accel=off\");\n+ error_setg(errp, \"oas must be 44 bits when accel=off\");\n return false;\n }\n if (s->ssidsize > SSID_SIZE_MODE_0) {\n@@ -2173,9 +2175,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Valid values are on, off, and auto. Defaults to off. \"\n \"Please ensure host platform supports ATS before enabling.\");\n object_class_property_set_description(klass, \"oas\",\n- \"Specify Output Address Size (for accel=on). Supported values \"\n- \"are 44 or 48 bits. Defaults to 44 bits. oas=auto is not \"\n- \"supported.\");\n+ \"Set Output Address Size in bits (for accel=on). \"\n+ \"Valid values are 44, 48, and auto. Defaults to 44 bits.\");\n object_class_property_set_description(klass, \"ssidsize\",\n \"Set number of bits used to represent SubstreamIDs (SSIDs). \"\n \"Valid values are 0-20 and auto. Defaults to 0. \"\n", "prefixes": [ "v2", "5/7" ] }