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GET /api/patches/2226861/?format=api
{ "id": 2226861, "url": "http://patchwork.ozlabs.org/api/patches/2226861/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-2-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422204335.23116-2-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T20:43:29", "name": "[v2,1/7] hw/arm/smmuv3-accel: Add helper for resolving auto parameters", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "12371b6e1b879b98a9b5731aebb98b3947a59a93", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-2-nathanc@nvidia.com/mbox/", "series": [ { "id": 501105, "url": "http://patchwork.ozlabs.org/api/series/501105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105", "date": "2026-04-22T20:43:28", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501105/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226861/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226861/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=a8Rjobwx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 22 Apr 2026 16:44:12 -0400", "from CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14)\n by SA1PR12MB7368.namprd12.prod.outlook.com (2603:10b6:806:2b7::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.8; Wed, 22 Apr\n 2026 20:43:48 +0000", "from CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e]) by CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e%6]) with mapi id 15.20.9846.016; Wed, 22 Apr 2026\n 20:43:47 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=UgiJ6sBqPfvI807ne9JwBNa1ymZQN1DYzh8ExCdV1v5GQY5ByMj7To24U7Hzb7BJmtd3vMhHHL1Gfork4gh3nKSQkexjVhm8foQrEGPn5IFM87tAXAuny0wzRYRAH4N/cwdu4YYGZv2olxlU2I2yW3RJrdUdEshw2T1S2U8j7D+c4t8SKXg+yu+ufHv4dFFF7/vpxxDQNsRpYPp/MlvYkPJZ3EtBR34nGLj1X9uuMGVFeuHV7Ndd1kbBDZbsamJ6XDrf0ixHVGpK35BFEaA41acANnZ61dwPnR10JYzw8TsEc6jXztCX2KaXEmkX1bys1w2f7Q1ov6dZ5r5AZDPcuw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=1OwSurik4J4X9c9HXqS7hHFNdlb3HuQJULq3X5TmB2g=;\n b=KKtG0gv6UmAqvfrER1Zsh51sOfRNDMS0nwOmfKqSnZ0kKl8xzJEBSoGyGJpXZhcFjc25X1lL0IEeWbxM3spnujZDeZPKo+WlZ5L2KURl3S0gaaHSwfPI27Txbbbbz+nlbFEPIUCzfhDTT6Bm5ZDtngIvXyhQvi5cBrQfpPBe6wHoR0QZsKT209iWMyeUSX8OtgM4skeCD6HLvJBe9mRpDb3kvxGlDrOjn8I1gnv7zyDAI7S7jL+yVOjT65XCKb+8ri3hK5evnqX5iDoSQBmiL4+ezwZVqUKH42z4VvfaT9AH9lyDnrKRMJft4t3YJ4xdlPKj41b0dyFRNireyppXiA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=1OwSurik4J4X9c9HXqS7hHFNdlb3HuQJULq3X5TmB2g=;\n b=a8Rjobwx+tc9kzZzl34I+CTo02KcjW/W2wTza0ZLS3M44E8qXXGAchtf/DnN2zirUHUdpmxhg7KYpfpTciHAp3VWEGWzlJ8PTPJC1I9AnIwohTGvVsDOpK78npaohoykTU+fyWZQOfZCk5DZQwxoHlPrquQWyRgSXkOFwnVbHC7WFhYJH+kq3Z2G9Ochyi1J2mgJHu7H7Oc3vv5GujsyQM/uqGhJAA/X2ZSdNgZ9odhoSftC11X6dWEMvhWy7KmpRkXF2bxhHFWALVgAtSahHcekC+bNYwbxrvvXjtFmncyXF3043UOJd4YbGDm4TXGbT1M3oBvsJI6/3Xn/Nth7aw==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Eric Auger <eric.auger@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH v2 1/7] hw/arm/smmuv3-accel: Add helper for resolving auto\n parameters", "Date": "Wed, 22 Apr 2026 13:43:29 -0700", "Message-ID": "<20260422204335.23116-2-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260422204335.23116-1-nathanc@nvidia.com>", "References": "<20260422204335.23116-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR05CA0124.namprd05.prod.outlook.com\n (2603:10b6:a03:33d::9) To CY3PR12MB9555.namprd12.prod.outlook.com\n (2603:10b6:930:10a::14)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY3PR12MB9555:EE_|SA1PR12MB7368:EE_", "X-MS-Office365-Filtering-Correlation-Id": "763a3704-28ec-4cb4-5a79-08dea0afd9ed", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n eH1G/FwZavdsecDB0SG90U/WFnXpN78jNwAEepQ5BGDD9IF8i9Zvb3VUQeVzjnqd4+wTSn4shttdu+7SXKGM2FVYrzY52VMsZiZQKKxg6vKClOrZ1wgaAO5XTHf0AooHBjnZ/iAv+HaLtVMaZGaNB2dNQSy+kg5fgLS4LQDS8IVfTGajoJAClkCRuT23Vu2/LT5r+C0sI9ugbxHBgE/Iep+S/2xIy7AwrYpFUxAK+WQXnI5Vt4/YEQVwD3BWgxchkaDHa8qR0KedBRHTf7bU069XZV8I/PkTls1/T1znpoh+sm9O2bs63yIMkYl/+YgRZvfjNIiPNM5TFYSJW0dmew60qqsnhZg7K7lIEfA+cWIeA83W8v6/zv3DzDSgIo1WiUMEcaLH96BDR0wl6tCXOFzm2ZOrntBWmhU9KoN7olgD0md3mF6LBx/X+RNnlNwna+P+u1V3BpL8zJdsIyjWrTtB6rW/1XUu3IAtmajJ8e24O1JH6F8p/ZPKBg1plyiG1+xlRvUyx9JxePsTxt6d+w2/8y5p2iJJYhmM/WCPQF7HdQSlouJ3k9XKxALifjbzJv50nUCap/Q1X8xwJKGr83/XVyekmBnEu3qx0dSmSv5zyKYQpS4xMoKHz5SMezCCbD6/Mbrln+IVlWvJaiVjjJPTENUwSM/MFCeZmemkE8sqi819kC7Rf3rWG7bMFzEU9XdYY2HXPKfh/BFZn0sKtNKmi0LohxCFBYp3/2EmboY=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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This helper function allows\nproperties such as ats, ril, ssidsize, and oas support to be resolved\nfrom host IOMMU capabilities via IOMMU_GET_HW_INFO.\n\nThe later commits in this series set the auto_mode flag to true when\nan accel SMMUv3 property value is explicitly set to 'auto', or if the\nproperty value is not set and defaults to auto mode.\n\nSetting these property values to 'auto' requires at least one\ncold-plugged device to retrieve and finalise these properties. If the\nauto_mode flag is true, register a machine_init_done notifier to\nverify this requirement and fail boot if it is not met.\n\nHot-plugged devices into an accel SMMUv3-associated bus will re-use\nthe resolved host values from the initial cold-plug.\n\nSubsequent patches will make use of this helper to resolve 'auto' to\nwhat is reported by host IOMMU capabilities.\n\nSuggested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 43 +++++++++++++++++++++++++++++++++++++++++\n hw/arm/smmuv3-accel.h | 2 ++\n include/hw/arm/smmuv3.h | 2 ++\n 3 files changed, 47 insertions(+)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 65c2f44880..8b3bbf3ef6 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -18,6 +18,7 @@\n \n #include \"smmuv3-internal.h\"\n #include \"smmuv3-accel.h\"\n+#include \"system/system.h\"\n \n /*\n * The root region aliases the global system memory, and shared_as_sysmem\n@@ -35,11 +36,32 @@ static int smmuv3_oas_bits(uint32_t oas)\n return map[oas];\n }\n \n+static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n+ struct iommu_hw_info_arm_smmuv3 *info) {\n+ SMMUv3AccelState *accel = s->s_accel;\n+\n+ /*\n+ * Return if 'auto' was not set for any accel SMMUv3 property, or\n+ * if property values were already resolved from a previous call\n+ * to this function (e.g. if this function was called again after\n+ * VM boot during device hot plug). We do not accept new property\n+ * values in this case where auto_finalised == true, and we re-use\n+ * the values determined from the initial cold plug.\n+ */\n+ if (!accel->auto_mode || accel->auto_finalised) {\n+ return;\n+ }\n+\n+ accel->auto_finalised = true;\n+}\n+\n static bool\n smmuv3_accel_check_hw_compatible(SMMUv3State *s,\n struct iommu_hw_info_arm_smmuv3 *info,\n Error **errp)\n {\n+ smmuv3_accel_auto_finalise(s, info);\n+\n /* QEMU SMMUv3 supports both linear and 2-level stream tables */\n if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=\n FIELD_EX32(s->idr[0], IDR0, STLEVEL)) {\n@@ -917,6 +939,22 @@ static void smmuv3_accel_as_init(SMMUv3State *s)\n address_space_init(shared_as_sysmem, &root, \"smmuv3-accel-as-sysmem\");\n }\n \n+static void smmuv3_machine_done(Notifier *notifier, void *data)\n+{\n+ SMMUv3State *s = container_of(notifier, SMMUv3State, machine_done);\n+ SMMUv3AccelState *accel = s->s_accel;\n+\n+ if (!s->accel) {\n+ return;\n+ }\n+\n+ if (accel->auto_mode && !accel->auto_finalised) {\n+ error_report(\"arm-smmuv3 accel=on with 'auto' properties requires \"\n+ \"at least one cold-plugged VFIO device\");\n+ exit(1);\n+ }\n+}\n+\n void smmuv3_accel_init(SMMUv3State *s)\n {\n SMMUState *bs = ARM_SMMU(s);\n@@ -924,4 +962,9 @@ void smmuv3_accel_init(SMMUv3State *s)\n s->s_accel = g_new0(SMMUv3AccelState, 1);\n bs->iommu_ops = &smmuv3_accel_ops;\n smmuv3_accel_as_init(s);\n+\n+ if (s->s_accel->auto_mode) {\n+ s->machine_done.notify = smmuv3_machine_done;\n+ qemu_add_machine_init_done_notifier(&s->machine_done);\n+ }\n }\ndiff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex dba6c71de5..3c1cd55714 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -26,6 +26,8 @@ typedef struct SMMUv3AccelState {\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n+ bool auto_mode;\n+ bool auto_finalised;\n } SMMUv3AccelState;\n \n typedef struct SMMUS1Hwpt {\ndiff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex 82f18eb090..fe0493c1aa 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -74,6 +74,8 @@ struct SMMUv3State {\n OnOffAuto ats;\n OasMode oas;\n SsidSizeMode ssidsize;\n+\n+ Notifier machine_done;\n };\n \n typedef enum {\n", "prefixes": [ "v2", "1/7" ] }