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GET /api/patches/2226860/?format=api
{ "id": 2226860, "url": "http://patchwork.ozlabs.org/api/patches/2226860/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-3-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422204335.23116-3-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T20:43:30", "name": "[v2,2/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ats\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "712e6bc50d8a95b405fe05c8509b32324fa32500", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-3-nathanc@nvidia.com/mbox/", "series": [ { "id": 501105, "url": "http://patchwork.ozlabs.org/api/series/501105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105", "date": "2026-04-22T20:43:28", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501105/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226860/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226860/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=JUrNNDsx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 22 Apr 2026 16:44:14 -0400", "from CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14)\n by SA1PR12MB7368.namprd12.prod.outlook.com (2603:10b6:806:2b7::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.8; Wed, 22 Apr\n 2026 20:43:48 +0000", "from CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e]) by CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e%6]) with mapi id 15.20.9846.016; Wed, 22 Apr 2026\n 20:43:48 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=XaIQP6+pTjlu7wzPiqGJQyCG138+rFQgNYy0AQJI0St1F465Q3jnbHADP1u4JgPlC7lsZHZkYaLpAw8Lvy0RCvcyDWmh8T9eqalte5Rq6WqmqbStzFfXTc/RQrb43frw+QfqClQxMfynSBHRjZsJ+3zf23xd6dyossIPpbgvydWxG5cJ1wcY8y+wPI1VNo1zcnJOP16VVtzPl6cJD9omQwqkktR1jStVaNs6yELKV6buQNgazAg4sa84OGhN/MYzGKhgKenZvK4D5oXAmg926qAcirltFJj0a6RTmt3iUu+4BoKIPZfrT4lISG/mgajSewSngUQchknooJicr1vOpA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=pNQMk8199xNjxz/6z3c9BTg4hsIU2uR430Nbf/7d8rY=;\n b=bUL6ecziqMN/TbLhCZcMbUEiwjdVWa18o2VrQL8l7StRXBuDwS6gL6CtMM5JrQSl+Ao4m+eFMymzfA0YgFX95MDIJpqXu6hDiH90pG012H+lOUmTzHeDaBG3/K/rhhvip3J/K7FjFNt02Q9L4H09/4vGUCr+HJtP0f4fqssM9Cs6EekByyebirI/2cZO/eVtypbAbcTE55AVbfZMfjzolO+iDe275LR98ryIb7nVX6tNbT0p0EeY7Wu1G72JxdYUSApNprcvmiHYelqNXKD+5yXDOz/cwALftCM5jLIT2wj4jx6Ra5Q5gYPuIktbkpDty4yusPH4ITack9BhiouB2A==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=pNQMk8199xNjxz/6z3c9BTg4hsIU2uR430Nbf/7d8rY=;\n b=JUrNNDsxTWeDb25LuVfwqg5WzRrod4KWGeI5NEJpV6EjKlv8LAwRT88wLxGkQEvNc1yVBwVsKtR/Dv2SOJp5B9T7oB7ROiDMHgVSwmlTca3ouFalzpgaVlkLMxtVODdpT+YX2NmmSlX11bboW6PHAINT6CeSP9YwtPPxl5diVk2N7LSAytSLwSq1MQBOwfChNWSIQgErtQKsOvJrwHNXoKCSK2AE2E3HWO9AQigcFTuD2nu+traEjIa3ePnKpNTTNjSml17cyuWln8NybzwD6a87qLUjNiBL+T/NJ2ldWwIjw/4FJHJ1d/1XXbZp+BC1elaSwCr3/UIYHCiY40mVcw==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Eric Auger <eric.auger@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH v2 2/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ats\"", "Date": "Wed, 22 Apr 2026 13:43:30 -0700", "Message-ID": "<20260422204335.23116-3-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260422204335.23116-1-nathanc@nvidia.com>", "References": "<20260422204335.23116-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR13CA0178.namprd13.prod.outlook.com\n (2603:10b6:a03:2c7::33) To CY3PR12MB9555.namprd12.prod.outlook.com\n (2603:10b6:930:10a::14)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY3PR12MB9555:EE_|SA1PR12MB7368:EE_", "X-MS-Office365-Filtering-Correlation-Id": "54c010ff-9c28-4de2-5887-08dea0afdad4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n HBgFhrJbOj0ggQuyx6ikLMOPBoEZb3qesUPg5V8F1VGUmlFbYQ2vRBER8eRlijOmorKDWC9OrD3pBJ4v1zEoHFVSHXduMwDsqW0e2oMtWyDi4G8k1Bjuo2CNnWk+5MUjueTdTkkPYxryoOgmlkps5upLmzT3zNHvPVBHQhamE7mO8ooY2vRv5N6YD+FTgPYGn/TZ5gY1QdwOTp5nzMDavAdY/IMIQaC0FlRETaZ4XNJvcHC9XCK1izS47Q9k6XjLjrmaISxEJee+iXwCPAL6Nrxef3TTfBNrqI/3CUXDj/p+yLVWYhMg9C/y6Om4C5mxnpOe900D1W1lBtGegPkPzY6Q0UyozX7AQ70EsMDrQa8f3i7F73XAdktuMXS7+a8IOsZ+SvP3Ib3GRWn4+rytF8nxGfwWFC+RRA9hgZ+zUMPkxJTUodtBEcu3Wpb5VChEJJ0W+Ic0kGAsY8IEtCjTMQFin4K0jbjij2zf+WV/9lQX/Dwzu9YK/2GoMSWL9ACFjfHDbZ/7OL244gRzEhyxkb1h++lDNGdI29DHBtz91t1LKw25KAV+l4/VZA6klvQs3aIysGt1FmTFgz0JISgGBT3BZYmLCZivM1NbFwG8ixLAtYYB1zjyYBCbK8ARo+wy2MdPHeJ54EZ+MwBhnpXA18fBk7YmOTbt5xR/iQTB7bESYHET6yLCB/QdAQYr30dsfqUOHDR9X/Agll4m3P5ReFe0Hpsaw9p4EJ+d9nKJMVI=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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Derive host values using\nIOMMU_GET_HW_INFO, retrieving ATS capability from IDR0.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 9 +++++++++\n hw/arm/smmuv3.c | 10 +++-------\n 2 files changed, 12 insertions(+), 7 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 8b3bbf3ef6..b42d189d29 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -52,6 +52,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n return;\n }\n \n+ if (s->ats == ON_OFF_AUTO_AUTO) {\n+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS,\n+ FIELD_EX32(info->idr[0], IDR0, ATS));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -963,6 +968,10 @@ void smmuv3_accel_init(SMMUv3State *s)\n bs->iommu_ops = &smmuv3_accel_ops;\n smmuv3_accel_as_init(s);\n \n+ if (s->ats == ON_OFF_AUTO_AUTO) {\n+ s->s_accel->auto_mode = true;\n+ }\n+\n if (s->s_accel->auto_mode) {\n s->machine_done.notify = smmuv3_machine_done;\n qemu_add_machine_init_done_notifier(&s->machine_done);\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 7fead1c3cf..5671649fee 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1972,10 +1972,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->ats == ON_OFF_AUTO_AUTO) {\n- error_setg(errp, \"ats auto mode is not supported\");\n- return false;\n- }\n if (s->ril == ON_OFF_AUTO_AUTO) {\n error_setg(errp, \"ril auto mode is not supported\");\n return false;\n@@ -2175,9 +2171,9 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Disable range invalidation support (for accel=on). ril=auto \"\n \"is not supported.\");\n object_class_property_set_description(klass, \"ats\",\n- \"Enable/disable ATS support (for accel=on). Please ensure host \"\n- \"platform has ATS support before enabling this. ats=auto is not \"\n- \"supported.\");\n+ \"Enable/disable ATS support (for accel=on). \"\n+ \"Valid values are on, off, and auto. Defaults to off. \"\n+ \"Please ensure host platform supports ATS before enabling.\");\n object_class_property_set_description(klass, \"oas\",\n \"Specify Output Address Size (for accel=on). Supported values \"\n \"are 44 or 48 bits. Defaults to 44 bits. oas=auto is not \"\n", "prefixes": [ "v2", "2/7" ] }