Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2226859/?format=api
{ "id": 2226859, "url": "http://patchwork.ozlabs.org/api/patches/2226859/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-7-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422204335.23116-7-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T20:43:34", "name": "[v2,6/7] hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "417f90eb8ab3094b4fcda441e82bf054e3004bc6", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-7-nathanc@nvidia.com/mbox/", "series": [ { "id": 501105, "url": "http://patchwork.ozlabs.org/api/series/501105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105", "date": "2026-04-22T20:43:28", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501105/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226859/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226859/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=hF/MIBlC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1B7F1dzrz1yHy\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 06:45:11 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFeR4-0000Zi-Fg; Wed, 22 Apr 2026 16:44:38 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <nathanc@nvidia.com>)\n id 1wFeQn-0000Ty-H4; Wed, 22 Apr 2026 16:44:21 -0400", "from mail-westcentralusazlp170100005.outbound.protection.outlook.com\n ([2a01:111:f403:c112::5] helo=CY7PR03CU001.outbound.protection.outlook.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <nathanc@nvidia.com>)\n id 1wFeQl-0006xi-Us; Wed, 22 Apr 2026 16:44:21 -0400", "from CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14)\n by SA1PR12MB7368.namprd12.prod.outlook.com (2603:10b6:806:2b7::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.8; Wed, 22 Apr\n 2026 20:44:00 +0000", "from CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e]) by CY3PR12MB9555.namprd12.prod.outlook.com\n ([fe80::fdb2:266d:ee2b:8d1e%6]) with mapi id 15.20.9846.016; Wed, 22 Apr 2026\n 20:44:00 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=KkjG3uiq6Qlgv3gUAFRFh+NQ1cO3or52bLjCYOfIcGyjFZmAa+SvTGXB4Ec0fjiyJMjdyVMWwyJDnJmBosAA13+s8Z7BiCdvYa6lfyiGBNdLrAZAMXWFWUjmlgzsgG4+uAHy1Yb4bbmOIhtfO2BHQ/5hvsSScau1wxNjSNkkIqAQPsbZX773Jr31h9nCrIXLugpQ8/PZMunu51uSLbFaoMWfDX2GbZzduA27kQNaHoS68sHzAPTcZ9Pg1nl+eXD6zKfT12PNmPfxUvkifzbx6RFCz76ErmALbi3Vq+zS4Rt1AhQxjTL1M/6KGLJvMNTNnOMlSpttGEMupOqm7RecUQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=7PgZDhLNAJ1sqFiaj4DAHfpXU8tlTv755bTEwWXqX6E=;\n b=FkQ++77DIf4eiHucpnDAXC2VaV3MZyf/5z8d8rxqGQ2HOZnJaX4CA/8n0iC1z+I37ToMLNVIox/9st8+Kf2DGlsYrtWwu/qhrd3h7XdC9dtnog6j6KvRUbpmgjli1ivtMYwoTc3clwdQuePcYrfOW37F/+v/t2OH9FpWpBpbVP3wrR7C8pOONA3nB9kt13MXz3wAHJJT4S6J5jqCx6eedRCIzy6kgcobfT8MncH8cFjpMh5m3bfUaKsyVvSr1DxDOFS49hBP7vJCVwvD5xINdoP9mcpskOT3I/tC4YSInMXGHtuQIeqxyQerpxLZp+bzxB6fjhvBPzL62dswIsSwWg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=7PgZDhLNAJ1sqFiaj4DAHfpXU8tlTv755bTEwWXqX6E=;\n b=hF/MIBlCFXqRhZDkNKCngzj4h8itOnj33gkMLekpd4v2YBfNLwMFcy3z7fYozgPUGBP3EpWfXASaveHD9o2pRCcASIrTmaFKt+RiM+teh4yn2nlUy3O+2gm/Csu4MlzFbZxzEPFvh4DQEm/JcluT/Q0VH024D376wrrR7k+ILeV3FWA9FOoNbu0gGFZIiMckPcM7tgT7zZpBIo7+5Aovs/4ZEVyVvWZENkwPJp9Zy3TfJz35aSnTus5mJIbKjkYFhWtm52NDAOPzSomWBMj5I1DtvrFWf6Pi2g5l4mSebP+uoPp4SFOeY5vG55inlmoej6GvnUCmGDuvpigGpV1WbQ==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Eric Auger <eric.auger@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH v2 6/7] hw/arm/smmuv3: Set default ats, ril, ssidsize,\n oas to auto", "Date": "Wed, 22 Apr 2026 13:43:34 -0700", "Message-ID": "<20260422204335.23116-7-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260422204335.23116-1-nathanc@nvidia.com>", "References": "<20260422204335.23116-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR05CA0133.namprd05.prod.outlook.com\n (2603:10b6:a03:33d::18) To CY3PR12MB9555.namprd12.prod.outlook.com\n (2603:10b6:930:10a::14)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY3PR12MB9555:EE_|SA1PR12MB7368:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2b29f64b-dd7a-4bdf-b0eb-08dea0afe198", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n Lh8cq8neAGXahBdjOQGioEeWtATJszLEopztswxdx5ElxgV1XEsMvfMdV3DvC6AJV5nTom9fiRP+DSxfSglO6usVDAtHg+lRQ6q4lJ0cF9jKv9qK4WEX2tWURqcP3Nv41K9fmCxXlw8rregRW8N1GF10poZpYTrMhJjhzSrGWiSRYx2j09lLCmobWduzxF1urJdUWPADwhh40dePVQ6AD4/qBxbXIV+H9JoCWu9HhcKq44+Lo+QHitv/4UWrMckpKCLXMgm9mZz6liz/jtQhiadkvn2d+ZXA8FcZPGgJEsOSDHyYPIKLgWBJj715u0rEgqNbRSt85eTAAA/fVTR/qvbvM0c2IO+7onMc7YDuQQACuAexpUcadfAS3DHQc0k3XG4soJYQXab6exaCdLSTNzrUxrHst/zQwhfMjUg/mPMBfAAG2JNOq4GZvAKhvJd2pgS5/TdJzGkVAiMgxilaBlr7pfJ8X6qw9+O3u/2R2LmdUer+ZkwUkNKc6BBeiZnfn1F3kiN+25Sn2jLjoz7juXcUNVi3qtkOQ4Jm7XsfuL7wkwh4U+82w0aqScE3P+nariokV4GFkSCc+ebBarQ8XI5Es81BZpMPeHQWQS7qz3+QCdWj3e1iNqMqSywXyJ+MHjyrOqbxzloCNuQzqRIkeIpzCzTxgY411Ssuv+MPR1fA9auZV0DbWFPoxY1YdQK5FaXs07WmFAcXfGLUa9zEFGsZA6Q/GtMgE1vxmFsnFkI=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:CY3PR12MB9555.namprd12.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230040)(1800799024)(366016)(376014)(56012099003)(22082099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n D+u+mez+u4aw55aDbYzhfX0NsXEXF/A07I0YFZvDJ2+078r35pM7vkXktzowUAxNAO9/YQuSPi/0Ws9nua+h9ODLK8NSKkNix8pCIfQs3JqdSKr0N9XySuXtGDZyw4s425amVVwNyoKW+JmMvQP0yQagKu9gt0H89S6JyACVmOUruAQGlx6U7NRmGApOM/tD4+WmCi569+ujBEYuqsMtbO+b2jFmuFaRzofkthQLAv0ZILaX2fru+Ozg1YDEkueqemzDo4l8iGUYeLD9D2520tWW+cn90KNrPFcwmTiSYEwpIHyQ2VyTCZPq/BZyq4gOpZ6zwh2MfDbIAZHoEPX8IM7EocTzkOawVmbJN9wBJ+ee+RBORc0PAiKjNkkMHI5cZXxfJcN8QBlYKuJ0FwI2VcbjFXTdr5/51RMQych4xAovS1/u+m5gyKhvnavrxdnoCedJNy3WR+WBz45dJC1ID6BsJo3hv2N2+j18MhHNx9U5o2V78ztc6KcXeADalm4Q5yFt5RIli9PqzZzbirgjgn4ubhRWSU9H/hTA+2ng2oac4a81PXFCvfTd08c5Jdz+WVnCV74U439COnVF+tzhMWf92YtIOdZjP/gQt6y+5KEvdSPD7nTcJ8MI5EK+dA7EiGwrCdypkeUjLaY3a9ipI+bVw97GS4jU0nu/3224AAIQ0ryycHJurLoxHxyYFuq7H4t9hH90zgKiffxZqA4uK3mivaaV1wvFtfUmj4CfmhKFdrhce1sInI6Rsq4xL60VcVIQTU+bMgk6AcyulFqoeqXZfwaLHGRAIgX0UwUeS2M8DtL8FV5M2YnY5YoofXDMemm8x3iWSDAJGoamNSp1t8TxhfkgZgJDjnmrSEPX18I67M9di3rlknRfFiNByNlgvloVb1AVitQ2OG1pBozc37sBsQXZo7nhzMO3twnkIR/imlON8p7cbDcttpWwVOgWBkhgjXCDJWvvzRzrURX1BQoR2GotqgNG0G+g79vGDZE7FFJF1tBdWwoPvGbkKdO1QHVdE7N2BUp5vyCxlkgqsCqeCwGqYlpU0K9PLz5cu/yDEIvudhoYBDNQuIUGipbLIo93f+XwYVmvxxDx/zhff0lJ8eXWj1L+ubNTLR82SJ/XoO2APVfpV2vS7nRDZG9hLNY9S+GOFpyL4lFzDgFt1e2TzeogKdyY989cWVY2ZE03tprkkWdgoTZzN4kOd8b1vISoLdauSvA1cE3T2/nYETNmlVBNWxuL0/CoYJox5b3zsPFCqvalX/prR9KmlNaR8Rq1/ulVDZjp7VE5qhe1jKUnkp4Dml73Lr8eMuG8NCTAkH4LguePP23+eF+kzOkv6kznMP11Qf+hFU0EDqPVnBfSqh/dGr9e4eQlfMczva2x3NXUBUXRQqeIDcKUud8dYLEtkNP3vOkrSDoyHLH2msw6NudRDGIr9saRl2pe9rO2Q+6AZ1IvXOmwVnvrFlOm5XNThTJatbPUw105hiO5/nyY1iryzOQZ3NVqTuc1ZzYg52rp3On+T45UEICI6ZXaQbd/ClKirYDRiMXV3k8YQ66e+6PMxULk3rGsd/lpZvKGJvj+q3mQHDKKBQzmu2Euo5WAj80y3O9lE8otWawGKPNs9xSR+k1KzLNlDDsUnn5bap1fm6xKUF6XJjwEu8ibYahPECwMg0qu2WH7fOriV96Pi+6A61qYsiU4CjypDp842an20zYjZKdziiV/Ttz+yRBZL5hpTsdy4MSaSwSZGg==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2b29f64b-dd7a-4bdf-b0eb-08dea0afe198", "X-MS-Exchange-CrossTenant-AuthSource": "CY3PR12MB9555.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Apr 2026 20:43:59.8887 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 6GswAjToIZwfLqUz+PoqdgYnDDcV2+8s3Jhgcdveyf+hi81rI1Jv4QcGxzJTwpqfayPEo03zIv51qVtijoHZEg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB7368", "Received-SPF": "permerror client-ip=2a01:111:f403:c112::5;\n envelope-from=nathanc@nvidia.com;\n helo=CY7PR03CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Set the default value of ATS, RIL, SSIDSIZE, and OAS to auto, in order\nto match the host IOMMU properties when accel=on.\n\nIf accel=off and these property values are set to auto, the default\nproperty values defined in smmuv3_init_id_regs() for OAS and RIL will\nremain unchanged, while SSIDSIZE and ATS values will remain initialized\nat 0.\n\nIntroduce a new compat for the changed defaults.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3.c | 14 +++++++-------\n hw/core/machine.c | 8 ++++++++\n 2 files changed, 15 insertions(+), 7 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 39a6f72938..e8ca6be34a 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -2135,11 +2135,11 @@ static const Property smmuv3_properties[] = {\n /* GPA of MSI doorbell, for SMMUv3 accel use. */\n DEFINE_PROP_UINT64(\"msi-gpa\", SMMUv3State, msi_gpa, 0),\n /* RIL can be turned off for accel cases */\n- DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_ON),\n- DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_OFF),\n- DEFINE_PROP_OAS_MODE(\"oas\", SMMUv3State, oas, OAS_MODE_44),\n+ DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_AUTO),\n+ DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_AUTO),\n+ DEFINE_PROP_OAS_MODE(\"oas\", SMMUv3State, oas, OAS_MODE_AUTO),\n DEFINE_PROP_SSIDSIZE_MODE(\"ssidsize\", SMMUv3State, ssidsize,\n- SSID_SIZE_MODE_0),\n+ SSID_SIZE_MODE_AUTO),\n };\n \n static void smmuv3_instance_init(Object *obj)\n@@ -2167,7 +2167,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"configured in nested mode for vfio-pci dev assignment\");\n object_class_property_set_description(klass, \"ril\",\n \"Enable/disable range invalidation support (for accel=on). \"\n- \"Valid values are on, off, and auto. Defaults to on. \"\n+ \"Valid values are on, off, and auto. Defaults to auto. \"\n \"Please enable if host platform supports RIL, and disable if \"\n \"host platform does not support RIL.\");\n object_class_property_set_description(klass, \"ats\",\n@@ -2176,10 +2176,10 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Please ensure host platform supports ATS before enabling.\");\n object_class_property_set_description(klass, \"oas\",\n \"Set Output Address Size in bits (for accel=on). \"\n- \"Valid values are 44, 48, and auto. Defaults to 44 bits.\");\n+ \"Valid values are 44, 48, and auto. Defaults to auto.\");\n object_class_property_set_description(klass, \"ssidsize\",\n \"Set number of bits used to represent SubstreamIDs (SSIDs). \"\n- \"Valid values are 0-20 and auto. Defaults to 0. \"\n+ \"Valid values are 0-20 and auto. Defaults to auto. \"\n \"A value of N allows SSIDs in the range [0 .. 2^N - 1]. \"\n \"A value of 0 disables SubstreamID support. A value greater \"\n \"than 0 is required to enable PASID support.\");\ndiff --git a/hw/core/machine.c b/hw/core/machine.c\nindex 0aa77a57e9..a668bb2ec3 100644\n--- a/hw/core/machine.c\n+++ b/hw/core/machine.c\n@@ -37,6 +37,14 @@\n #include \"hw/virtio/virtio-iommu.h\"\n #include \"hw/acpi/generic_event_device.h\"\n #include \"qemu/audio.h\"\n+#include \"hw/arm/smmuv3.h\"\n+\n+GlobalProperty hw_compat_11_0[] = {\n+ { TYPE_ARM_SMMUV3, \"ats\", \"off\" },\n+ { TYPE_ARM_SMMUV3, \"ril\", \"on\" },\n+ { TYPE_ARM_SMMUV3, \"ssidsize\", \"0\" },\n+ { TYPE_ARM_SMMUV3, \"oas\", \"44\" },\n+};\n \n GlobalProperty hw_compat_10_2[] = {\n { \"scsi-block\", \"migrate-pr\", \"off\" },\n", "prefixes": [ "v2", "6/7" ] }