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GET /api/patches/2226829/?format=api
{ "id": 2226829, "url": "http://patchwork.ozlabs.org/api/patches/2226829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422195746.88865-33-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422195746.88865-33-philmd@linaro.org>", "list_archive_url": null, "date": "2026-04-22T19:57:30", "name": "[PULL,32/48] hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fa957efdc46f8ad2ea87252bb9f0f61e68ccc628", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422195746.88865-33-philmd@linaro.org/mbox/", "series": [ { "id": 501099, "url": "http://patchwork.ozlabs.org/api/series/501099/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501099", "date": "2026-04-22T19:56:59", "name": "[PULL,01/48] hw/avr: Build as common unit files", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501099/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226829/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226829/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=BqMc0Rvi;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohammadfaiz Bawa <mbawa@redhat.com>\n\nAdd a ppi_base parameter to tpm_build_ppi_acpi() instead of\nhardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where\nPPI memory is dynamically allocated by the platform bus and the\naddress is not known at compile time.\n\nUpdate the x86 callers (ISA TIS and CRB) to pass TPM_PPI_ADDR_BASE\nexplicitly. No behavioral change.\n\nReviewed-by: Stefan Berger <stefanb@linux.ibm.com>\nSigned-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-ID: <20260327173209.148180-3-mbawa@redhat.com>\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n include/hw/acpi/tpm.h | 3 ++-\n hw/acpi/tpm.c | 8 ++++----\n hw/i386/acpi-build.c | 2 +-\n hw/tpm/tpm_tis_isa.c | 2 +-\n 4 files changed, 8 insertions(+), 7 deletions(-)", "diff": "diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h\nindex d2bf6637c54..2ab186a7455 100644\n--- a/include/hw/acpi/tpm.h\n+++ b/include/hw/acpi/tpm.h\n@@ -20,6 +20,7 @@\n #include \"hw/core/registerfields.h\"\n #include \"hw/acpi/aml-build.h\"\n #include \"system/tpm.h\"\n+#include \"exec/hwaddr.h\"\n \n #ifdef CONFIG_TPM\n \n@@ -250,7 +251,7 @@ REG32(CRB_DATA_BUFFER, 0x80)\n */\n #define TPM_I2C_INT_ENABLE_MASK 0x0\n \n-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);\n+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base);\n \n #endif /* CONFIG_TPM */\n \ndiff --git a/hw/acpi/tpm.c b/hw/acpi/tpm.c\nindex 5fe95f2e3f1..e703775984a 100644\n--- a/hw/acpi/tpm.c\n+++ b/hw/acpi/tpm.c\n@@ -20,7 +20,7 @@\n #include \"qapi/error.h\"\n #include \"hw/acpi/tpm.h\"\n \n-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)\n {\n Aml *method, *field, *ifctx, *ifctx2, *ifctx3, *func_mask,\n *not_implemented, *pak, *tpm2, *tpm3, *pprm, *pprq, *zero, *one;\n@@ -40,7 +40,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n */\n aml_append(dev,\n aml_operation_region(\"TPP2\", AML_SYSTEM_MEMORY,\n- aml_int(TPM_PPI_ADDR_BASE + 0x100),\n+ aml_int(ppi_base + 0x100),\n 0x5A));\n field = aml_field(\"TPP2\", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);\n aml_append(field, aml_named_field(\"PPIN\", 8));\n@@ -56,7 +56,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n aml_append(dev,\n aml_operation_region(\n \"TPP3\", AML_SYSTEM_MEMORY,\n- aml_int(TPM_PPI_ADDR_BASE +\n+ aml_int(ppi_base +\n 0x15a /* movv, docs/specs/tpm.rst */),\n 0x1));\n field = aml_field(\"TPP3\", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);\n@@ -78,7 +78,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n \n aml_append(method,\n aml_operation_region(\"TPP1\", AML_SYSTEM_MEMORY,\n- aml_add(aml_int(TPM_PPI_ADDR_BASE), op, NULL), 0x1));\n+ aml_add(aml_int(ppi_base), op, NULL), 0x1));\n field = aml_field(\"TPP1\", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);\n aml_append(field, aml_named_field(\"TPPF\", 8));\n aml_append(method, field);\ndiff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c\nindex 4f01e2c476e..0d7c83d5e96 100644\n--- a/hw/i386/acpi-build.c\n+++ b/hw/i386/acpi-build.c\n@@ -1219,7 +1219,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,\n aml_append(dev, aml_name_decl(\"_STA\", aml_int(0xf)));\n aml_append(dev, aml_name_decl(\"_UID\", aml_int(1)));\n \n- tpm_build_ppi_acpi(tpm, dev);\n+ tpm_build_ppi_acpi(tpm, dev, TPM_PPI_ADDR_BASE);\n \n aml_append(sb_scope, dev);\n }\ndiff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c\nindex 1ca403241de..2b1267133ac 100644\n--- a/hw/tpm/tpm_tis_isa.c\n+++ b/hw/tpm/tpm_tis_isa.c\n@@ -159,7 +159,7 @@ static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)\n */\n /* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */\n aml_append(dev, aml_name_decl(\"_CRS\", crs));\n- tpm_build_ppi_acpi(ti, dev);\n+ tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE);\n aml_append(scope, dev);\n }\n \n", "prefixes": [ "PULL", "32/48" ] }