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GET /api/patches/2226719/?format=api
{ "id": 2226719, "url": "http://patchwork.ozlabs.org/api/patches/2226719/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuomp93t2.gcc.gcc-TEST.clyon.62.1.1@forge-stage.sourceware.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bmm.hhuomp93t2.gcc.gcc-TEST.clyon.62.1.1@forge-stage.sourceware.org>", "list_archive_url": null, "date": "2026-04-22T18:31:10", "name": "[v1,1/2] testsuite: arm: remove arm32 check from a few effective-targets", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cf4344df877dad507f9165480b6c9870aa417fa7", "submitter": { "id": 92734, "url": "http://patchwork.ozlabs.org/api/people/92734/?format=api", "name": "Christophe Lyon via Sourceware Forge", "email": "forge-bot+clyon@forge-stage.sourceware.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuomp93t2.gcc.gcc-TEST.clyon.62.1.1@forge-stage.sourceware.org/mbox/", "series": [ { "id": 501082, "url": "http://patchwork.ozlabs.org/api/series/501082/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501082", "date": "2026-04-22T18:31:11", "name": "testsuite: arm: Remove arm32 check and fix arm_v8_neon_ok flags", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501082/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226719/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226719/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org", "sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org", "server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g17Zq61Bkz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 04:50:27 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 0ECD8416286E\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 18:50:26 +0000 (GMT)", "from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id ACE944BBCDC9\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 18:32:29 +0000 (GMT)", "from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id 8894E434CD\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 18:32:29 +0000 (UTC)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 0ECD8416286E", "OpenDKIM Filter v2.11.0 sourceware.org ACE944BBCDC9" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org ACE944BBCDC9", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org ACE944BBCDC9", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776882749; cv=none;\n b=w+xx5/7ZMQNfSHpl4EPiAB0eoqIapJZaSrOqC6pdOhoboeAv3KM3dKoJsERLCPgjG8L9Hkm9LyFAGHGg9mGIzSPm0lYJwFkRc43Q2qVVKR+THs1H3Bn9F8M1Rh9OaeSxLqE2dnwyjckyrbR2QV60qbfQSYle1xGqWgK9rDcaUeo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776882749; c=relaxed/simple;\n bh=nLB+y6sPq31UzvV4vND/aPbMCwLh9VHeLsoENblsbYY=;\n h=From:Date:Subject:To:Message-ID;\n b=hDwsMxW6NYqWoz78mLPdtC9rR9XAburD9JzrclxX8M5KOrdgLPvnG1BgY3nPYm2gxrrL96+j67Eibej1zlkakayTzEAtgqCUpZK+MEHxjgQZJ9brtNlF6FEjoIiRkFiRGVOUw+lcuv+Bn2PD+b7l97t4TUr9SJGWOuV8adAfSN0=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Christophe Lyon via Sourceware Forge\n <forge-bot+clyon@forge-stage.sourceware.org>", "Date": "Wed, 22 Apr 2026 18:31:10 +0000", "Subject": "[PATCH v1 1/2] testsuite: arm: remove arm32 check from a few\n effective-targets", "To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>", "Message-ID": "\n <bmm.hhuomp93t2.gcc.gcc-TEST.clyon.62.1.1@forge-stage.sourceware.org>", "X-Mailer": "batrachomyomachia", "X-Pull-Request-Organization": "gcc", "X-Pull-Request-Repository": "gcc-TEST", "X-Pull-Request": "https://forge.sourceware.org/gcc/gcc-TEST/pulls/62", "References": "\n <bmm.hhuomp93t2.gcc.gcc-TEST.clyon.62.1.0@forge-stage.sourceware.org>", "In-Reply-To": "\n <bmm.hhuomp93t2.gcc.gcc-TEST.clyon.62.1.0@forge-stage.sourceware.org>", "X-Patch-URL": "\n https://forge.sourceware.org/clyon/gcc-TEST/commit/d2060316a3ee11188cd6459372acea45706f1faa", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Reply-To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>,\n clyon@gcc.gnu.org", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Christophe Lyon <christophe.lyon@linaro.org>\n\nA few arm effective-targets call check_effective_target_arm32 even\nthough they would force a -march=XXX flag which supports Arm and/or\nThumb-2, thus making the arm32 check useless. This has an impact when\nthe toolchain is configured with a default -march or -mcpu which\nsupports Thumb-1 only: in such a case, arm32 is false and we skip many\ntests, thus reducing coverage.\n\nThis patch removes the call to check_effective_target_arm32 where it\nis useless, enabling about 2000 tests.\n\nIn addition, add an early exit if the target is not an arm one, thus\nsaving a few compilation cycles where not needed. In all callers of\narm_neon_ok, remove the now useless \"istarget arm*-*-*.\n\ngcc/testsuite/ChangeLog:\n\n\t* lib/target-supports.exp\n\t(check_effective_target_arm_neon_ok_nocache): Remove arm32 check.\n\t(check_effective_target_arm_neon_fp16_ok_nocache): Likewise.\n\t(check_effective_target_arm_neon_softfp_fp16_ok_nocache): Likewise.\n\t(check_effective_target_arm_v8_neon_ok_nocache): Likewise.\n\t(check_effective_target_arm_neonv2_ok_nocache): Likewise.\n\t(check_effective_target_vect_pack_trunc): Remove istarget arm*-*-*\n\tcheck.\n\t(check_effective_target_vect_unpack): Likewise.\n\t(check_effective_target_vect_condition): Likewise.\n\t(check_effective_target_vect_cond_mixed): Likewise.\n\t(available_vector_sizes): Likewise.\n---\n gcc/testsuite/lib/target-supports.exp | 85 ++++++++++++---------------\n 1 file changed, 39 insertions(+), 46 deletions(-)", "diff": "diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex e8f888525917..d1d7a12acfce 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -5537,25 +5537,26 @@ proc add_options_for_arm_vfp3 { flags } {\n # best options to add.\n \n proc check_effective_target_arm_neon_ok_nocache { } {\n+ if { ![istarget arm*-*-*] } {\n+\treturn 0\n+ }\n global et_arm_neon_flags\n set et_arm_neon_flags \"\"\n- if { [check_effective_target_arm32] } {\n-\tforeach flags {\"\" \"-mfloat-abi=softfp\" \"-mfpu=neon\" \"-mfpu=neon -mfloat-abi=softfp\" \"-mfpu=neon -mfloat-abi=softfp -mcpu=unset -march=armv7-a\" \"-mfloat-abi=hard\" \"-mfpu=neon -mfloat-abi=hard\" \"-mfpu=neon -mfloat-abi=hard -mcpu=unset -march=armv7-a\"} {\n-\t if { [check_no_compiler_messages_nocache arm_neon_ok object {\n-\t\t#include <arm_neon.h>\n-\t\tint dummy;\n-\t\t#ifndef __ARM_NEON__\n-\t\t#error not NEON\n-\t\t#endif\n-\t\t/* Avoid the case where a test adds -mfpu=neon, but the toolchain is\n-\t\t configured for -mcpu=arm926ej-s, for example. */\n-\t\t#if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M'\n-\t\t#error Architecture does not support NEON.\n-\t\t#endif\n-\t } \"$flags\"] } {\n-\t\tset et_arm_neon_flags $flags\n-\t\treturn 1\n-\t }\n+ foreach flags {\"\" \"-mfloat-abi=softfp\" \"-mfpu=neon\" \"-mfpu=neon -mfloat-abi=softfp\" \"-mfpu=neon -mfloat-abi=softfp -mcpu=unset -march=armv7-a\" \"-mfloat-abi=hard\" \"-mfpu=neon -mfloat-abi=hard\" \"-mfpu=neon -mfloat-abi=hard -mcpu=unset -march=armv7-a\"} {\n+\tif { [check_no_compiler_messages_nocache arm_neon_ok object {\n+\t #include <arm_neon.h>\n+\t int dummy;\n+\t #ifndef __ARM_NEON__\n+\t #error not NEON\n+\t #endif\n+\t /* Avoid the case where a test adds -mfpu=neon, but the toolchain is\n+\t configured for -mcpu=arm926ej-s, for example. */\n+\t #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M'\n+\t #error Architecture does not support NEON.\n+\t #endif\n+\t} \"$flags\"] } {\n+\t set et_arm_neon_flags $flags\n+\t return 1\n \t}\n }\n \n@@ -5741,8 +5742,7 @@ proc check_effective_target_arm_neon_fp16_ok_nocache { } {\n global et_arm_neon_fp16_flags\n global et_arm_neon_flags\n set et_arm_neon_fp16_flags \"\"\n- if { [check_effective_target_arm32]\n-\t && [check_effective_target_arm_neon_ok] } {\n+ if { [check_effective_target_arm_neon_ok] } {\n \tforeach flags {\"\" \"-mfloat-abi=softfp\" \"-mfpu=neon-fp16\"\n \t\t \"-mfpu=neon-fp16 -mfloat-abi=softfp\"\n \t\t \"-mfp16-format=ieee\"\n@@ -5780,8 +5780,7 @@ proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } {\n global et_arm_neon_softfp_fp16_flags\n global et_arm_neon_flags\n set et_arm_neon_softfp_fp16_flags \"\"\n- if { [check_effective_target_arm32]\n-\t && [check_effective_target_arm_neon_ok] } {\n+ if { [check_effective_target_arm_neon_ok] } {\n \tforeach flags {\"-mfpu=neon-fp16 -mfloat-abi=softfp\"\n \t\t \"-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee\"} {\n \t if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object {\n@@ -5924,22 +5923,20 @@ proc check_effective_target_arm_fp16_none_ok { } {\n proc check_effective_target_arm_v8_neon_ok_nocache { } {\n global et_arm_v8_neon_flags\n set et_arm_v8_neon_flags \"\"\n- if { [check_effective_target_arm32] } {\n-\tforeach flags {\"\" \"-mfloat-abi=softfp\" \"-mfpu=neon-fp-armv8\" \"-mfpu=neon-fp-armv8 -mfloat-abi=softfp\"} {\n-\t if { [check_no_compiler_messages_nocache arm_v8_neon_ok object {\n-\t\t#if __ARM_ARCH < 8\n-\t\t#error not armv8 or later\n-\t\t#endif\n-\t\t#include \"arm_neon.h\"\n-\t\tvoid\n-\t\tfoo ()\n-\t\t{\n-\t\t __asm__ volatile (\"vrintn.f32 q0, q0\");\n-\t\t}\n-\t } \"$flags -mcpu=unset -march=armv8-a\"] } {\n-\t\tset et_arm_v8_neon_flags $flags\n-\t\treturn 1\n+ foreach flags {\"\" \"-mfloat-abi=softfp\" \"-mfpu=neon-fp-armv8\" \"-mfpu=neon-fp-armv8 -mfloat-abi=softfp\"} {\n+\tif { [check_no_compiler_messages_nocache arm_v8_neon_ok object {\n+\t #if __ARM_ARCH < 8\n+\t #error not armv8 or later\n+\t #endif\n+\t #include \"arm_neon.h\"\n+\t void\n+\t foo ()\n+\t {\n+\t\t__asm__ volatile (\"vrintn.f32 q0, q0\");\n \t }\n+\t} \"$flags -mcpu=unset -march=armv8-a\"] } {\n+\t set et_arm_v8_neon_flags $flags\n+\t return 1\n \t}\n }\n \n@@ -5960,8 +5957,7 @@ proc check_effective_target_arm_neonv2_ok_nocache { } {\n global et_arm_neonv2_flags\n global et_arm_neon_flags\n set et_arm_neonv2_flags \"\"\n- if { [check_effective_target_arm32]\n-\t && [check_effective_target_arm_neon_ok] } {\n+ if { [check_effective_target_arm_neon_ok] } {\n \tforeach flags {\"\" \"-mfloat-abi=softfp\" \"-mfpu=neon-vfpv4\" \"-mfpu=neon-vfpv4 -mfloat-abi=softfp\"} {\n \t if { [check_no_compiler_messages_nocache arm_neonv2_ok object {\n \t\t#include \"arm_neon.h\"\n@@ -8872,7 +8868,7 @@ proc check_effective_target_vect_pack_trunc { } {\n expr { [istarget powerpc*-*-*]\n \t || [check_effective_target_x86]\n \t || [istarget aarch64*-*-*]\n-\t || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]\n+\t || ([check_effective_target_arm_neon_ok]\n \t\t && [check_effective_target_arm_little_endian])\n \t || ([istarget mips*-*-*]\n \t\t && [et-is-effective-target mips_msa])\n@@ -8898,7 +8894,7 @@ proc check_effective_target_vect_unpack { } {\n \t || [istarget aarch64*-*-*]\n \t || ([istarget mips*-*-*]\n \t\t && [et-is-effective-target mips_msa])\n-\t || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]\n+\t || ([check_effective_target_arm_neon_ok]\n \t\t && [check_effective_target_arm_little_endian])\n \t || ([istarget s390*-*-*]\n \t\t && [check_effective_target_s390_vx])\n@@ -9585,8 +9581,7 @@ proc check_effective_target_vect_condition { } {\n \t || [check_effective_target_x86]\n \t || ([istarget mips*-*-*]\n \t\t && [et-is-effective-target mips_msa])\n-\t || ([istarget arm*-*-*]\n-\t\t && [check_effective_target_arm_neon_ok])\n+\t || [check_effective_target_arm_neon_ok]\n \t || ([istarget s390*-*-*]\n \t\t && [check_effective_target_s390_vx])\n \t || [istarget amdgcn-*-*]\n@@ -9604,8 +9599,7 @@ proc check_effective_target_vect_cond_mixed { } {\n expr { [check_effective_target_x86]\n \t || [istarget aarch64*-*-*]\n \t || [istarget powerpc*-*-*]\n-\t || ([istarget arm*-*-*]\n-\t\t && [check_effective_target_arm_neon_ok])\n+\t || [check_effective_target_arm_neon_ok]\n \t || ([istarget mips*-*-*]\n \t\t && [et-is-effective-target mips_msa])\n \t || ([istarget s390*-*-*]\n@@ -9786,8 +9780,7 @@ proc available_vector_sizes { } {\n \t lappend result [aarch64_sve_bits]\n \t}\n \tlappend result 128 64\n- } elseif { [istarget arm*-*-*]\n-\t\t&& [check_effective_target_arm_neon_ok] } {\n+ } elseif { [check_effective_target_arm_neon_ok] } {\n \tlappend result 128 64\n } elseif { [check_effective_target_x86] } {\n \tif { [check_avx_available] && ![check_prefer_avx128] } {\n", "prefixes": [ "v1", "1/2" ] }