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GET /api/patches/2226706/?format=api
{ "id": 2226706, "url": "http://patchwork.ozlabs.org/api/patches/2226706/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuoi95js4.gcc.gcc-TEST.clyon.56.1.1@forge-stage.sourceware.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bmm.hhuoi95js4.gcc.gcc-TEST.clyon.56.1.1@forge-stage.sourceware.org>", "list_archive_url": null, "date": "2026-04-22T18:26:41", "name": "[v1,1/1] WIP: arm: always enable both simd and mve builtins", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "92af3ece2f21366cef8b0335182d82771019a77c", "submitter": { "id": 92734, "url": "http://patchwork.ozlabs.org/api/people/92734/?format=api", "name": "Christophe Lyon via Sourceware Forge", "email": "forge-bot+clyon@forge-stage.sourceware.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuoi95js4.gcc.gcc-TEST.clyon.56.1.1@forge-stage.sourceware.org/mbox/", "series": [ { "id": 501078, "url": "http://patchwork.ozlabs.org/api/series/501078/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501078", "date": "2026-04-22T18:26:40", "name": "MVE", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501078/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226706/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226706/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org", "sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org", "server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g17QJ6jYlz1yGs\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 04:43:04 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 20E1A4313C8E\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 18:43:03 +0000 (GMT)", "from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id 96B6A4A98F0F\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 18:27:27 +0000 (GMT)", "from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id 71BAA4347F\n for <gcc-patches@gcc.gnu.org>; Wed, 22 Apr 2026 18:27:27 +0000 (UTC)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 20E1A4313C8E", "OpenDKIM Filter v2.11.0 sourceware.org 96B6A4A98F0F" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 96B6A4A98F0F", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 96B6A4A98F0F", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776882447; cv=none;\n b=qR+Q3c5/U2ddBYqZeK8L5raW6dNOwTtzmiVf8SQ+s17uWf1BVo10Ni8/gVtwagkPJ6RoiNyTy2Z3fj44A85x17irkC35UcsYA7Yc+6tMXDygNG5LiedUWYGdTQmpML4YdG+KGCL69W7Ngtz16VDRrYhVVnZmbAxhulMzxd6ZduM=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776882447; c=relaxed/simple;\n bh=/gPdDqoAkb6T6P9/q6fMfhUqLk2xKsHirIiBRnSWkRo=;\n h=From:Date:Subject:To:Message-ID;\n b=f68BbRH2Kxo02w+sEsZGPF/ujraIx9Ykc0FcEAWLMlieThSkKSYi4Lv9UD8LhlOQwSj7W4xHnga7G+ljhANBciPwkUK4K/jhePUtACamZUcC5U3h9EqOE28BqyqVFCYNOZ8pYCtOlaiJ2TF0KVaKvOYflifhJubf+7cy/1Z8Eds=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Christophe Lyon via Sourceware Forge\n <forge-bot+clyon@forge-stage.sourceware.org>", "Date": "Wed, 22 Apr 2026 18:26:41 +0000", "Subject": "[PATCH v1 1/1] WIP: arm: always enable both simd and mve builtins", "To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>", "Message-ID": "\n <bmm.hhuoi95js4.gcc.gcc-TEST.clyon.56.1.1@forge-stage.sourceware.org>", "X-Mailer": "batrachomyomachia", "X-Requested-Reviewer": "rearnsha", "X-Pull-Request-Organization": "gcc", "X-Pull-Request-Repository": "gcc-TEST", "X-Pull-Request": "https://forge.sourceware.org/gcc/gcc-TEST/pulls/56", "References": "\n <bmm.hhuoi95js4.gcc.gcc-TEST.clyon.56.1.0@forge-stage.sourceware.org>", "In-Reply-To": "\n <bmm.hhuoi95js4.gcc.gcc-TEST.clyon.56.1.0@forge-stage.sourceware.org>", "X-Patch-URL": "\n https://forge.sourceware.org/gcc/gcc-TEST/commit/500e389872ad732d57c30b05c3caac7e9499357f", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Reply-To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>,\n clyon@gcc.gnu.org", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Christophe Lyon <christophe.lyon@linaro.org>\n\nWe get lots of error messages when compiling arm_neon.h under\ne.g. -mcpu=cortex-m55, because Neon builtins are enabled only when\n!TARGET_HAVE_MVE. This has been the case since MVE support was\nintroduced.\n\nThis patch uses an approach similar to what we do on aarch64, but only\npartially since Neon intrinsics do not use the \"new\" framework.\n\nWe register all types and Neon intrinsics, whether MVE is enabled or\nnot, which enables to compile arm_neon.h. However, we need to\nintroduce a \"switcher\" similar to aarch64's to avoid ICEs when LTO is\nenabled: in that case, since we have to enable the MVE intrinsics, we\ntemporarily change arm_active_target.isa to enable MVE bits. This\nenables hooks like arm_vector_mode_supported_p and arm_array_mode to\nbehave as expected by the MVE intrinsics framework. We switch back\nto the previous arm_active_target.isa immediately after.\n\nThere is no impact on the testsuite results, except that gcc.log is no\nlonger full of errors messages when trying to compile arm_neon.h if\nMVE is forced somehow.\n\ngcc/ChangeLog:\n\n\t* config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Remove\n\tTARGET_HAVE_MVE condition.\n\t(arm_init_mve_builtins): Remove calls to\n\tarm_init_simd_builtin_types and\n\tarm_init_simd_builtin_scalar_types. Switch to MVE isa flags.\n\t(arm_init_neon_builtins): Remove calls to\n\tarm_init_simd_builtin_types and\n\tarm_init_simd_builtin_scalar_types.\n\t(arm_target_switcher::arm_target_switcher): New.\n\t(arm_target_switcher::~arm_target_switcher): New.\n\t(arm_init_builtins): Call arm_init_simd_builtin_scalar_types and\n\tarm_init_simd_builtin_types. Always call arm_init_mve_builtins\n\tand arm_init_neon_builtins.\n\t* config/arm/arm-protos.h (class arm_target_switcher): New.\n---\n gcc/config/arm/arm-builtins.cc | 131 ++++++++++++++++++++++-----------\n gcc/config/arm/arm-protos.h | 15 ++++\n 2 files changed, 101 insertions(+), 45 deletions(-)", "diff": "diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc\nindex 3bb2566f9a2f..2e4f3595ed2e 100644\n--- a/gcc/config/arm/arm-builtins.cc\n+++ b/gcc/config/arm/arm-builtins.cc\n@@ -48,6 +48,7 @@\n #include \"basic-block.h\"\n #include \"gimple.h\"\n #include \"ssa.h\"\n+#include \"regs.h\"\n \n #define SIMD_MAX_BUILTIN_ARGS 7\n \n@@ -1105,37 +1106,35 @@ arm_init_simd_builtin_types (void)\n an entry in our mangling table, consequently, they get default\n mangling. As a further gotcha, poly8_t and poly16_t are signed\n types, poly64_t and poly128_t are unsigned types. */\n- if (!TARGET_HAVE_MVE)\n- {\n- arm_simd_polyQI_type_node\n-\t= build_distinct_type_copy (intQI_type_node);\n- (*lang_hooks.types.register_builtin_type) (arm_simd_polyQI_type_node,\n-\t\t\t\t\t\t \"__builtin_neon_poly8\");\n- arm_simd_polyHI_type_node\n-\t= build_distinct_type_copy (intHI_type_node);\n- (*lang_hooks.types.register_builtin_type) (arm_simd_polyHI_type_node,\n-\t\t\t\t\t\t \"__builtin_neon_poly16\");\n- arm_simd_polyDI_type_node\n-\t= build_distinct_type_copy (unsigned_intDI_type_node);\n- (*lang_hooks.types.register_builtin_type) (arm_simd_polyDI_type_node,\n-\t\t\t\t\t\t \"__builtin_neon_poly64\");\n- arm_simd_polyTI_type_node\n-\t= build_distinct_type_copy (unsigned_intTI_type_node);\n- (*lang_hooks.types.register_builtin_type) (arm_simd_polyTI_type_node,\n-\t\t\t\t\t\t \"__builtin_neon_poly128\");\n- /* Init poly vector element types with scalar poly types. */\n- arm_simd_types[Poly8x8_t].eltype = arm_simd_polyQI_type_node;\n- arm_simd_types[Poly8x16_t].eltype = arm_simd_polyQI_type_node;\n- arm_simd_types[Poly16x4_t].eltype = arm_simd_polyHI_type_node;\n- arm_simd_types[Poly16x8_t].eltype = arm_simd_polyHI_type_node;\n- /* Note: poly64x2_t is defined in arm_neon.h, to ensure it gets default\n-\t mangling. */\n-\n- /* Prevent front-ends from transforming poly vectors into string\n-\t literals. */\n- TYPE_STRING_FLAG (arm_simd_polyQI_type_node) = false;\n- TYPE_STRING_FLAG (arm_simd_polyHI_type_node) = false;\n- }\n+ arm_simd_polyQI_type_node\n+ = build_distinct_type_copy (intQI_type_node);\n+ (*lang_hooks.types.register_builtin_type) (arm_simd_polyQI_type_node,\n+\t\t\t\t\t \"__builtin_neon_poly8\");\n+ arm_simd_polyHI_type_node\n+ = build_distinct_type_copy (intHI_type_node);\n+ (*lang_hooks.types.register_builtin_type) (arm_simd_polyHI_type_node,\n+\t\t\t\t\t \"__builtin_neon_poly16\");\n+ arm_simd_polyDI_type_node\n+ = build_distinct_type_copy (unsigned_intDI_type_node);\n+ (*lang_hooks.types.register_builtin_type) (arm_simd_polyDI_type_node,\n+\t\t\t\t\t \"__builtin_neon_poly64\");\n+ arm_simd_polyTI_type_node\n+ = build_distinct_type_copy (unsigned_intTI_type_node);\n+ (*lang_hooks.types.register_builtin_type) (arm_simd_polyTI_type_node,\n+\t\t\t\t\t \"__builtin_neon_poly128\");\n+ /* Init poly vector element types with scalar poly types. */\n+ arm_simd_types[Poly8x8_t].eltype = arm_simd_polyQI_type_node;\n+ arm_simd_types[Poly8x16_t].eltype = arm_simd_polyQI_type_node;\n+ arm_simd_types[Poly16x4_t].eltype = arm_simd_polyHI_type_node;\n+ arm_simd_types[Poly16x8_t].eltype = arm_simd_polyHI_type_node;\n+ /* Note: poly64x2_t is defined in arm_neon.h, to ensure it gets default\n+ mangling. */\n+\n+ /* Prevent front-ends from transforming poly vectors into string\n+ literals. */\n+ TYPE_STRING_FLAG (arm_simd_polyQI_type_node) = false;\n+ TYPE_STRING_FLAG (arm_simd_polyHI_type_node) = false;\n+\n /* Init all the element types built by the front-end. */\n arm_simd_types[Int8x8_t].eltype = get_typenode_from_name (INT8_TYPE);\n arm_simd_types[Int8x16_t].eltype = get_typenode_from_name (INT8_TYPE);\n@@ -1451,8 +1450,8 @@ arm_init_mve_builtins (void)\n {\n volatile unsigned int i, fcode = ARM_BUILTIN_MVE_PATTERN_START;\n \n- arm_init_simd_builtin_scalar_types ();\n- arm_init_simd_builtin_types ();\n+ enum isa_feature mve_flags[] = { ISA_MVE_FP, isa_nobit };\n+ arm_target_switcher switcher (mve_flags);\n \n /* Add support for __builtin_{get,set}_fpscr_nzcvqc, used by MVE intrinsics\n that read and/or write the carry bit. */\n@@ -1496,14 +1495,6 @@ arm_init_neon_builtins (void)\n {\n unsigned int i, fcode = ARM_BUILTIN_NEON_PATTERN_START;\n \n- arm_init_simd_builtin_types ();\n-\n- /* Strong-typing hasn't been implemented for all AdvSIMD builtin intrinsics.\n- Therefore we need to preserve the old __builtin scalar types. It can be\n- removed once all the intrinsics become strongly typed using the qualifier\n- system. */\n- arm_init_simd_builtin_scalar_types ();\n-\n for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++, fcode++)\n {\n arm_builtin_datum *d = &neon_builtin_data[i];\n@@ -1690,6 +1681,50 @@ arm_init_fp16_builtins (void)\n \t\t\t\t\t \"__fp16\");\n }\n \n+/* Temporarily set FLAGS as the enabled target features. */\n+arm_target_switcher::arm_target_switcher (const enum isa_feature *flags)\n+ : m_old_general_regs_only (TARGET_GENERAL_REGS_ONLY),\n+ m_old_target_pragma (current_target_pragma)\n+{\n+ m_old_arm_active_target_isa = sbitmap_alloc (isa_num_bits);\n+ bitmap_copy (m_old_arm_active_target_isa, arm_active_target.isa);\n+\n+ /* Changing the ISA flags and have_regs_of_mode should be enough here. We\n+ shouldn't need to pay the compile-time cost of a full target switch. */\n+ if (! TARGET_SOFT_FLOAT)\n+ global_options.x_target_flags &= ~MASK_GENERAL_REGS_ONLY;\n+\n+ arm_initialize_isa (arm_active_target.isa, flags);\n+\n+ /* Target pragmas are irrelevant when defining intrinsics artificially. */\n+ current_target_pragma = NULL_TREE;\n+\n+ /* Ensure SIMD / VFP regs are available if Neon or MVE is enabled. */\n+ memcpy (m_old_have_regs_of_mode, have_regs_of_mode, sizeof\n+\t (have_regs_of_mode));\n+\n+ for (int i = 0; i < NUM_MACHINE_MODES; ++i)\n+ if ((bitmap_bit_p (arm_active_target.isa, isa_bit_mve)\n+\t && (VALID_MVE_MODE ((machine_mode) i)\n+\t || VALID_MVE_STRUCT_MODE ((machine_mode) i)))\n+\t|| (bitmap_bit_p (arm_active_target.isa, isa_bit_neon)\n+\t && (VALID_NEON_QREG_MODE ((machine_mode) i)\n+\t\t|| VALID_NEON_DREG_MODE ((machine_mode) i))))\n+ have_regs_of_mode[i] = true;\n+}\n+\n+arm_target_switcher::~arm_target_switcher ()\n+{\n+ if (m_old_general_regs_only)\n+ global_options.x_target_flags |= MASK_GENERAL_REGS_ONLY;\n+ bitmap_copy (arm_active_target.isa, m_old_arm_active_target_isa);\n+ sbitmap_free (m_old_arm_active_target_isa);\n+ current_target_pragma = m_old_target_pragma;\n+\n+ memcpy (have_regs_of_mode, m_old_have_regs_of_mode,\n+\t sizeof (have_regs_of_mode));\n+}\n+\n void\n arm_init_builtins (void)\n {\n@@ -1709,10 +1744,16 @@ arm_init_builtins (void)\n = arm_general_add_builtin_function (\"__builtin_arm_lane_check\",\n \t\t\t\t\t lane_check_fpr,\n \t\t\t\t\t ARM_BUILTIN_SIMD_LANE_CHECK);\n- if (TARGET_HAVE_MVE)\n-\tarm_init_mve_builtins ();\n- else\n-\tarm_init_neon_builtins ();\n+\n+ /* Strong-typing hasn't been implemented for all AdvSIMD builtin\n+\t intrinsics. Therefore we need to preserve the old __builtin scalar\n+\t types. It can be removed once all the intrinsics become strongly\n+\t typed using the qualifier system. */\n+ arm_init_simd_builtin_scalar_types ();\n+ arm_init_simd_builtin_types ();\n+ arm_init_neon_builtins ();\n+ arm_init_mve_builtins ();\n+\n arm_init_vfp_builtins ();\n arm_init_crypto_builtins ();\n }\ndiff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h\nindex ff7e7658f912..b95e16db3635 100644\n--- a/gcc/config/arm/arm-protos.h\n+++ b/gcc/config/arm/arm-protos.h\n@@ -611,4 +611,19 @@ bool arm_mve_immediate_check(rtx, machine_mode, bool);\n \n opt_machine_mode arm_mve_data_mode (scalar_mode, poly_uint64);\n \n+/* RAII class for enabling enough features to define built-in types\n+ and implement the arm_mve.h pragma. */\n+class arm_target_switcher\n+{\n+public:\n+ arm_target_switcher (const enum isa_feature *flags);\n+ ~arm_target_switcher ();\n+\n+private:\n+ sbitmap m_old_arm_active_target_isa;\n+ bool m_old_general_regs_only;\n+ tree m_old_target_pragma;\n+ bool m_old_have_regs_of_mode[MAX_MACHINE_MODE];\n+};\n+\n #endif /* ! GCC_ARM_PROTOS_H */\n", "prefixes": [ "v1", "1/1" ] }