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{
    "id": 2226658,
    "url": "http://patchwork.ozlabs.org/api/patches/2226658/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260422180359.1067313-1-ibuclaw@gdcproject.org/",
    "project": {
        "id": 17,
        "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api",
        "name": "GNU Compiler Collection",
        "link_name": "gcc",
        "list_id": "gcc-patches.gcc.gnu.org",
        "list_email": "gcc-patches@gcc.gnu.org",
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    "msgid": "<20260422180359.1067313-1-ibuclaw@gdcproject.org>",
    "list_archive_url": null,
    "date": "2026-04-22T18:03:59",
    "name": "[GCC17-stage1] m32c: Remove all support for M32C target.",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "140b03e19033ad39e2d021bd9f5d384e9e2db114",
    "submitter": {
        "id": 46728,
        "url": "http://patchwork.ozlabs.org/api/people/46728/?format=api",
        "name": "Iain Buclaw",
        "email": "ibuclaw@gdcproject.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260422180359.1067313-1-ibuclaw@gdcproject.org/mbox/",
    "series": [
        {
            "id": 501062,
            "url": "http://patchwork.ozlabs.org/api/series/501062/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501062",
            "date": "2026-04-22T18:03:59",
            "name": "[GCC17-stage1] m32c: Remove all support for M32C target.",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/501062/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2226658/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2226658/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Iain Buclaw <ibuclaw@gdcproject.org>",
        "To": "gcc-patches@gcc.gnu.org",
        "Cc": "Iain Buclaw <ibuclaw@gdcproject.org>",
        "Subject": "[PATCH GCC17-stage1] m32c: Remove all support for M32C target.",
        "Date": "Wed, 22 Apr 2026 20:03:59 +0200",
        "Message-ID": "<20260422180359.1067313-1-ibuclaw@gdcproject.org>",
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    },
    "content": "Hi,\n\nm32c target support in GCC was deprecated in GCC 16 as the target had no\nmaintainer since GCC 9.\n\nOK for trunk?\n\nRegards,\nIain.\n\n---\ncontrib/ChangeLog:\n\n\t* compare-all-tests: Remove references to m32c.\n\t* config-list.mk: Likewise.\n\ngcc/ChangeLog:\n\n\t* config/m32c/*: Delete entire directory.\n\t* attr-urls.def: Remove references to m32c.\n\t* config.gcc: Likewise.\n\t* config/msp430/msp430.cc (msp430_expand_epilogue): Likewise.\n\t* configure: Regenerate.\n\t* configure.ac: Remove references to m32c.\n\t* doc/extend.texi: Likewise.\n\t* doc/install.texi: Likewise.\n\t* doc/invoke.texi: Likewise.\n\t* doc/md.texi: Likewise.\n\t* explow.cc (promote_mode): Likewise.\n\t* regenerate-opt-urls.py: Likewise.\n\t* config/microblaze/microblaze.opt.urls: Regenerate.\n\t* config/msp430/msp430.opt.urls: Regenerate.\n\t* config/nds32/nds32.opt.urls: Regenerate.\n\t* config/rl78/rl78.opt.urls: Regenerate.\n\t* config/rs6000/sysv4.opt.urls: Regenerate.\n\t* config/rx/elf.opt.urls: Regenerate.\n\t* config/stormy16/stormy16.opt.urls: Regenerate.\n\t* config/visium/visium.opt.urls: Regenerate.\n\nlibgcc/ChangeLog:\n\n\t* config/m32c/*: Delete entire directory.\n\t* config.host: Remove references to m32c.\n\t* config/rl78/lib2div.c (C3): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.c-torture/compile/20000804-1.c: Remove references to m32c.\n\t* gcc.c-torture/compile/20001226-1.c: Likewise.\n\t* gcc.c-torture/compile/limits-stringlit.c: Likewise.\n\t* gcc.c-torture/execute/20020404-1.c: Likewise.\n\t* gcc.dg/20020312-2.c: Likewise.\n\t* gcc.dg/max-1.c: Likewise.\n\t* gcc.dg/torture/pr26565.c: Likewise.\n\t* gcc.dg/tree-ssa/reassoc-32.c: Likewise.\n\t* gcc.dg/tree-ssa/reassoc-33.c: Likewise.\n\t* gcc.dg/tree-ssa/reassoc-34.c: Likewise.\n\t* gcc.dg/tree-ssa/reassoc-35.c: Likewise.\n\t* gcc.dg/tree-ssa/reassoc-36.c: Likewise.\n\t* gcc.dg/utf-array-short-wchar.c: Likewise.\n\t* gcc.dg/utf-array.c: Likewise.\n\t* lib/target-supports.exp: Likewise.\n---\n contrib/compare-all-tests                     |    3 +-\n contrib/config-list.mk                        |    2 +-\n gcc/attr-urls.def                             |    4 -\n gcc/config.gcc                                |   12 +-\n gcc/config/m32c/addsub.md                     |  259 -\n gcc/config/m32c/bitops.md                     |  421 --\n gcc/config/m32c/blkmov.md                     |  241 -\n gcc/config/m32c/cond.md                       |  309 --\n gcc/config/m32c/constraints.md                |  225 -\n gcc/config/m32c/jump.md                       |  134 -\n gcc/config/m32c/m32c-modes.def                |   28 -\n gcc/config/m32c/m32c-pragma.cc                |  128 -\n gcc/config/m32c/m32c-protos.h                 |   80 -\n gcc/config/m32c/m32c.abi                      |  131 -\n gcc/config/m32c/m32c.cc                       | 4511 -----------------\n gcc/config/m32c/m32c.h                        |  635 ---\n gcc/config/m32c/m32c.md                       |   79 -\n gcc/config/m32c/m32c.opt                      |   43 -\n gcc/config/m32c/m32c.opt.urls                 |    8 -\n gcc/config/m32c/minmax.md                     |   57 -\n gcc/config/m32c/mov.md                        |  490 --\n gcc/config/m32c/muldiv.md                     |  287 --\n gcc/config/m32c/predicates.md                 |  294 --\n gcc/config/m32c/prologue.md                   |  201 -\n gcc/config/m32c/shift.md                      |  351 --\n gcc/config/m32c/t-m32c                        |   42 -\n gcc/config/microblaze/microblaze.opt.urls     |    2 +-\n gcc/config/msp430/msp430.cc                   |    3 +-\n gcc/config/msp430/msp430.opt.urls             |    2 +-\n gcc/config/nds32/nds32.opt.urls               |    2 +-\n gcc/config/rl78/rl78.opt.urls                 |    2 +-\n gcc/config/rs6000/sysv4.opt.urls              |    2 +-\n gcc/config/rx/elf.opt.urls                    |    2 +-\n gcc/config/stormy16/stormy16.opt.urls         |    2 +-\n gcc/config/visium/visium.opt.urls             |    2 +-\n gcc/configure                                 |    2 +-\n gcc/configure.ac                              |    2 +-\n gcc/doc/extend.texi                           |  115 +-\n gcc/doc/install.texi                          |   12 +-\n gcc/doc/invoke.texi                           |   37 -\n gcc/doc/md.texi                               |  129 -\n gcc/explow.cc                                 |    2 +-\n gcc/regenerate-opt-urls.py                    |    1 -\n .../gcc.c-torture/compile/20000804-1.c        |    1 -\n .../gcc.c-torture/compile/20001226-1.c        |    1 -\n .../gcc.c-torture/compile/limits-stringlit.c  |    2 +-\n .../gcc.c-torture/execute/20020404-1.c        |    1 -\n gcc/testsuite/gcc.dg/20020312-2.c             |    2 -\n gcc/testsuite/gcc.dg/max-1.c                  |    2 -\n gcc/testsuite/gcc.dg/torture/pr26565.c        |    2 -\n gcc/testsuite/gcc.dg/tree-ssa/reassoc-32.c    |    2 +-\n gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c    |    2 +-\n gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c    |    2 +-\n gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c    |    2 +-\n gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c    |    2 +-\n gcc/testsuite/gcc.dg/utf-array-short-wchar.c  |    6 +-\n gcc/testsuite/gcc.dg/utf-array.c              |    6 +-\n gcc/testsuite/lib/target-supports.exp         |    3 -\n libgcc/config.host                            |    7 -\n libgcc/config/m32c/lib1funcs.S                |  230 -\n libgcc/config/m32c/lib2funcs.c                |  147 -\n libgcc/config/m32c/t-m32c                     |   13 -\n libgcc/config/m32c/trapv.c                    |   42 -\n libgcc/config/rl78/lib2div.c                  |    2 +-\n 64 files changed, 30 insertions(+), 9741 deletions(-)\n delete mode 100644 gcc/config/m32c/addsub.md\n delete mode 100644 gcc/config/m32c/bitops.md\n delete mode 100644 gcc/config/m32c/blkmov.md\n delete mode 100644 gcc/config/m32c/cond.md\n delete mode 100644 gcc/config/m32c/constraints.md\n delete mode 100644 gcc/config/m32c/jump.md\n delete mode 100644 gcc/config/m32c/m32c-modes.def\n delete mode 100644 gcc/config/m32c/m32c-pragma.cc\n delete mode 100644 gcc/config/m32c/m32c-protos.h\n delete mode 100644 gcc/config/m32c/m32c.abi\n delete mode 100644 gcc/config/m32c/m32c.cc\n delete mode 100644 gcc/config/m32c/m32c.h\n delete mode 100644 gcc/config/m32c/m32c.md\n delete mode 100644 gcc/config/m32c/m32c.opt\n delete mode 100644 gcc/config/m32c/m32c.opt.urls\n delete mode 100644 gcc/config/m32c/minmax.md\n delete mode 100644 gcc/config/m32c/mov.md\n delete mode 100644 gcc/config/m32c/muldiv.md\n delete mode 100644 gcc/config/m32c/predicates.md\n delete mode 100644 gcc/config/m32c/prologue.md\n delete mode 100644 gcc/config/m32c/shift.md\n delete mode 100644 gcc/config/m32c/t-m32c\n delete mode 100644 libgcc/config/m32c/lib1funcs.S\n delete mode 100644 libgcc/config/m32c/lib2funcs.c\n delete mode 100644 libgcc/config/m32c/t-m32c\n delete mode 100644 libgcc/config/m32c/trapv.c",
    "diff": "diff --git a/contrib/compare-all-tests b/contrib/compare-all-tests\nindex 3564e60c8ea..561b2195c64 100644\n--- a/contrib/compare-all-tests\n+++ b/contrib/compare-all-tests\n@@ -24,7 +24,6 @@ arm_opts='-mthumb/-march=armv5t -mthumb/-march=armv6t2 -march=armv5 -mthumb/-mar\n cris_opts='-march=v32 -march=v1'\n h8300_opts='/ -mh -mh/-mn -ms -ms/-mn -msx -msx/-mn -mint32 -mh/-mint32 -mh/-mn/-mint32 -ms/-mint32 -ms/-mn/-mint32 -msx/-mint32 -msx/-mn/-mint32'\n i386_opts='-m32 -m64 -m32/-msse/-msse2/-mfpmath=sse'\n-m32c_opts='-mcpu=r8c -mcpu=m16c -mcpu=m32c'\n m68k_opts='-m68000 -m68020 -m68020/-m68881 -m68040/-m68881 -m68060/-m68881 -mcfv4e'\n mips_opts='-msoft-float/-mgp32/-mips16 -mabi=32/-mfp32/-mgp32/-mips16 -mabi=o64/-mfp64/-mgp64/-mips16 -msoft-float/-mgp32 -mfp32/-mgp32 -march=mips64r2/-mabi=32/-mfp64/-mgp32 -msoft-float/-mgp64 -msingle-float/-mfp32/-mgp64 -mfp64/-mgp64'\n mn10300_opts='-mam33 -mam33-2'\n@@ -34,7 +33,7 @@ s390_opts='-m31 -m31/-mzarch -m64'\n sh_opts='-m3 -m3e -m4 -m4a -m4al -m4/-mieee -m1 -m1/-mno-cbranchdi -m2a -m2a/-mieee -m2e -m2e/-mieee'\n sparc_opts='-mcpu=v8/-m32 -mcpu=v9/-m32 -m64'\n \n-all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32c m32r m68k mcore mips mmix mn10300 pa pdp11 ppc sh sparc v850 vax xstormy16 xtensa' # e500 \n+all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32r m68k mcore mips mmix mn10300 pa pdp11 ppc sh sparc v850 vax xstormy16 xtensa' # e500\n \n test_one_file ()\n {\ndiff --git a/contrib/config-list.mk b/contrib/config-list.mk\nindex 076fc8fb49e..54ca15a7808 100644\n--- a/contrib/config-list.mk\n+++ b/contrib/config-list.mk\n@@ -66,7 +66,7 @@ LIST = \\\n   lm32-rtems lm32-uclinux \\\n   loongarch32-linux-gnuf64 loongarch32-linux-gnuf32 loongarch32-linux-gnusf \\\n   loongarch64-linux-gnuf64 loongarch64-linux-gnuf32 loongarch64-linux-gnusf \\\n-  m32c-elfOPT-enable-obsolete m32r-elf m32rle-elf \\\n+  m32r-elf m32rle-elf \\\n   m68k-elf m68k-netbsdelf \\\n   m68k-uclinux m68k-linux m68k-rtems \\\n   mcore-elf microblaze-linux microblaze-elf \\\ndiff --git a/gcc/attr-urls.def b/gcc/attr-urls.def\nindex c75030793b9..db5ec7124a0 100644\n--- a/gcc/attr-urls.def\n+++ b/gcc/attr-urls.def\n@@ -20,7 +20,6 @@ const attr_url_entry all_attrs[] = {\n  { \"assume\", \"gcc/Common-Attributes.html#index-assume\", \"\", 6},\n  { \"assume_aligned\", \"gcc/Common-Attributes.html#index-assume_005faligned\", \"\", 14},\n  { \"aux\", \"gcc/ARC-Attributes.html#index-aux_002c-ARC\", \"ARC\", 3},\n- { \"bank_switch\", \"gcc/M32C-Attributes.html#index-bank_005fswitch_002c-M32C\", \"M32C\", 11},\n  { \"below100\", \"gcc/Xstormy16-Attributes.html#index-below100_002c-Xstormy16\", \"Xstormy16\", 8},\n  { \"break_handler\", \"gcc/MicroBlaze-Attributes.html#index-break_005fhandler_002c-MicroBlaze\", \"MicroBlaze\", 13},\n  { \"brk_interrupt\", \"gcc/RL78-Attributes.html#index-brk_005finterrupt_002c-RL78\", \"RL78\", 13},\n@@ -54,7 +53,6 @@ const attr_url_entry all_attrs[] = {\n  { \"externally_visible\", \"gcc/Common-Attributes.html#index-externally_005fvisible\", \"\", 18},\n  { \"fallthrough\", \"gcc/Common-Attributes.html#index-fallthrough\", \"\", 11},\n  { \"far\", \"gcc/MIPS-Attributes.html#index-far_002c-MIPS\", \"MIPS\", 3},\n- { \"fast_interrupt\", \"gcc/M32C-Attributes.html#index-fast_005finterrupt_002c-M32C\", \"M32C\", 14},\n  { \"fast_interrupt\", \"gcc/MicroBlaze-Attributes.html#index-fast_005finterrupt_002c-MicroBlaze\", \"MicroBlaze\", 14},\n  { \"fast_interrupt\", \"gcc/RX-Attributes.html#index-fast_005finterrupt_002c-RX\", \"RX\", 14},\n  { \"fastcall\", \"gcc/x86-Attributes.html#index-fastcall_002c-x86-32\", \"x86-32\", 8},\n@@ -70,7 +68,6 @@ const attr_url_entry all_attrs[] = {\n  { \"forwarder_section\", \"gcc/Epiphany-Attributes.html#index-forwarder_005fsection_002c-Epiphany\", \"Epiphany\", 17},\n  { \"function_return\", \"gcc/x86-Attributes.html#index-function_005freturn_002c-x86\", \"x86\", 15},\n  { \"function_vector\", \"gcc/H8_002f300-Attributes.html#index-function_005fvector_002c-H8_002f300\", \"H8/300\", 15},\n- { \"function_vector\", \"gcc/M32C-Attributes.html#index-function_005fvector_002c-M16C_002fM32C\", \"M16C/M32C\", 15},\n  { \"function_vector\", \"gcc/SH-Attributes.html#index-function_005fvector_002c-SH\", \"SH\", 15},\n  { \"gcc_struct\", \"gcc/PowerPC-Attributes.html#index-gcc_005fstruct_002c-PowerPC\", \"PowerPC\", 10},\n  { \"gcc_struct\", \"gcc/x86-Attributes.html#index-gcc_005fstruct_002c-x86\", \"x86\", 10},\n@@ -90,7 +87,6 @@ const attr_url_entry all_attrs[] = {\n  { \"interrupt\", \"gcc/C-SKY-Attributes.html#index-interrupt_002c-C-SKY\", \"C-SKY\", 9},\n  { \"interrupt\", \"gcc/Common-Attributes.html#index-interrupt\", \"\", 9},\n  { \"interrupt\", \"gcc/Epiphany-Attributes.html#index-interrupt_002c-Epiphany\", \"Epiphany\", 9},\n- { \"interrupt\", \"gcc/M32C-Attributes.html#index-interrupt_002c-M32C\", \"M32C\", 9},\n  { \"interrupt\", \"gcc/M32R_002fD-Attributes.html#index-interrupt_002c-M32R_002fD\", \"M32R/D\", 9},\n  { \"interrupt\", \"gcc/MIPS-Attributes.html#index-interrupt_002c-MIPS\", \"MIPS\", 9},\n  { \"interrupt\", \"gcc/MSP430-Attributes.html#index-interrupt_002c-MSP430\", \"MSP430\", 9},\ndiff --git a/gcc/config.gcc b/gcc/config.gcc\nindex 8fe99616f82..1f977664bd2 100644\n--- a/gcc/config.gcc\n+++ b/gcc/config.gcc\n@@ -283,7 +283,7 @@ esac\n # Obsolete configurations.\n case ${target} in\n      ia64*-*-hpux* | ia64*-*-*vms* | ia64*-*-elf*\t\\\n-   | m32c*-*-* | epiphany*-*-* | rl78*-*-*\t\t\\\n+   | epiphany*-*-* | rl78*-*-*\t\t\\\n  )\n     if test \"x$enable_obsolete\" != xyes; then\n       echo \"*** Configuration ${target} is obsolete.\" >&2\n@@ -359,11 +359,6 @@ tm_p_file=\n cpu_type=`echo ${target} | sed 's/-.*$//'`\n cpu_is_64bit=\n case ${target} in\n-m32c*-*-*)\n-        cpu_type=m32c\n-\ttmake_file=m32c/t-m32c\n-\ttarget_has_targetm_common=no\n-        ;;\n aarch64*-*-*)\n \tcpu_type=aarch64\n \textra_headers=\"arm_fp16.h arm_neon.h arm_bf16.h arm_acle.h arm_sve.h arm_sme.h arm_neon_sve_bridge.h arm_private_fp8.h arm_private_neon_types.h\"\n@@ -3704,11 +3699,6 @@ am33_2.0-*-linux*)\n \tgas=yes gnu_ld=yes\n \tuse_collect2=no\n \t;;\n-m32c-*-elf*)\n-\ttm_file=\"elfos.h newlib-stdint.h ${tm_file}\"\n-\tc_target_objs=\"m32c-pragma.o\"\n-\tcxx_target_objs=\"m32c-pragma.o\"\n- \t;;\n *)\n \techo \"*** Configuration ${target} not supported\" 1>&2\n \texit 1\ndiff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md\ndeleted file mode 100644\nindex db4d309ae1f..00000000000\n--- a/gcc/config/m32c/addsub.md\n+++ /dev/null\n@@ -1,259 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; add, sub\n-\n-(define_insn \"addqi3\"\n-  [(set (match_operand:QI 0 \"mra_or_sp_operand\"\n-\t\t  \"=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm\")\n-\t(plus:QI (match_operand:QI 1 \"mra_operand\"\n-\t\t  \"%0,0,0,0, 0,0,0,0\")\n-\t\t (match_operand:QI 2 \"mrai_operand\"\n-\t\t  \"iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa\")))]\n-  \"\"\n-  \"add.b\\t%2,%0\"\n-  [(set_attr \"flags\" \"oszc\")]\n-  )\n-\n-(define_insn \"addhi3\"\n-  [(set (match_operand:HI 0 \"m32c_nonimmediate_operand\"\n-\t \t  \"=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp\")\n-\t(plus:HI (match_operand:HI 1 \"m32c_any_operand\"\n-\t\t  \"%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0\")\n-\t\t (match_operand:HI 2 \"m32c_any_operand\"\n-\t\t  \"IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i\")))]\n-  \"\"\n-  \"@\n-   add.w\\t%2,%0\n-   add.w\\t%2,%0\n-   add.w\\t%2,%0\n-   add.w\\t%2,%0\n-   sub.w\\t%m2,%0\n-   sub.w\\t%m2,%0\n-   mova\\t%d2[%1],%0\n-   stc\\t%1,%0\n-   mova\\t%D2[%1],%0\n-   add.w\\t%2,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc\")]\n-  )\n-\n-(define_insn \"addpsi3\"\n-  [(set (match_operand:PSI 0 \"m32c_nonimmediate_operand\" \"=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi\")\n-\t(plus:PSI (match_operand:PSI 1 \"m32c_nonimmediate_operand\" \"0,0,0,0,0, Raa,Rad\")\n-\t\t  (match_operand:PSI 2 \"m32c_any_operand\" \"Is3,IS1,iSdRpi,?Rmm,i, i,IS2\")))]\n-  \"TARGET_A24\"\n-  \"@\n-   add.l:q\\t%2,%0\n-   addx\\t%2,%0\n-   add.l\\t%2,%0\n-   add.l\\t%2,%0\n-   add.l\\t%2,%0\n-   mova\\t%d2[%1],%0\n-   mova\\t%D2[%1],%0\"\n-  [(set_attr \"flags\" \"oszc,oszc,oszc,oszc,oszc,n,n\")]\n-  )\n-\n-(define_expand \"addsi3\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm\")\n-        (plus:SI (match_operand:SI 1 \"mra_operand\" \"%0,0,0,0\")\n-                 (match_operand:SI 2 \"mrai_operand\" \"iRsiSd,?Rmm,iRsiSd,?Rmm\")))]\n-  \"TARGET_A24 ||TARGET_A16\"\n-  \"\"\n-  )\n-\n-(define_insn \"addsi3_1\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd\")\n-        (plus:SI (match_operand:SI 1 \"mra_operand\" \"%0,0,0,0,0,0,0,0\")\n-                 (match_operand:SI 2 \"mrai_operand\" \"IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd\")))]\n-  \"TARGET_A16\"\n-  \"*\n-  \n-  switch (which_alternative)\n-    { \n-    case 0:\n-      return \\\"add.w %X2,%h0\\;adcf.w %H0\\\";\n-    case 1:\n-      return \\\"add.w %X2,%h0\\;adcf.w %H0\\\";\n-    case 2:\n-      if (GET_CODE (operands[2]) == SYMBOL_REF)\n-        {\n-          output_asm_insn (\\\"add.w #%%lo(%d2),%h0\\\",operands);\n-          return \\\"adc.w #%%hi(%d2),%H0\\\";\n-        }\n-      else\n-        {\n-          output_asm_insn (\\\"add.w %X2,%h0\\\",operands);\n-          operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-          return \\\"adc.w %X2,%H0\\\";\n-        }\n-    case 3:\n-      return \\\"add.w %h2,%h0\\;adc.w %H2,%H0\\\";\n-    case 4:\n-      output_asm_insn (\\\"add.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"adc.w %X2,%H0\\\";\n-    case 5:\n-      return \\\"add.w %h2,%h0\\;adc.w %H2,%H0\\\";\n-    case 6:\n-      return \\\"add.w %h2,%h0\\;adc.w %H2,%H0\\\";\n-    case 7:\n-      return \\\"add.w %h2,%h0\\;adc.w %H2,%H0\\\";\n-    default:\n-      gcc_unreachable ();\n-    }\"\n-  [(set_attr \"flags\" \"x,x,x,x,x,x,x,x\")]\n-)\n-\n-(define_insn \"addsi3_2\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm\")\n-        (plus:SI (match_operand:SI 1 \"mra_operand\" \"%0,0,0,0\")\n-                 (match_operand:SI 2 \"mrai_operand\" \"iRsiSd,?Rmm,iRsiSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"add.l\\t%2,%0\"\n-  [(set_attr \"flags\" \"oszc\")]\n-)\n-\n-(define_insn \"subqi3\"\n-  [(set (match_operand:QI 0 \"mra_or_sp_operand\"\n-\t\t   \"=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp\")\n-\t(minus:QI (match_operand:QI 1 \"mra_operand\"\n-\t\t   \"0,0,0,0, 0,0,0,0, 0\")\n-\t\t  (match_operand:QI 2 \"mrai_operand\"\n-\t\t   \"iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i\")))]\n-  \"\"\n-  \"sub.b\\t%2,%0\"\n-  [(set_attr \"flags\" \"oszc\")]\n-  )\n-\n-(define_insn \"subhi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\"\n-\t\t   \"=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm\")\n-\t(minus:HI (match_operand:HI 1 \"mras_operand\"\n-\t\t   \"0,0,0,0, 0,0\")\n-\t\t  (match_operand:HI 2 \"mrai_operand\"\n-\t\t   \"IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2\")))]\n-  \"\"\n-  \"@\n-   sub.w\\t%2,%0\n-   sub.w\\t%2,%0\n-   sub.w\\t%2,%0\n-   sub.w\\t%2,%0\n-   add.w\\t%m2,%0\n-   add.w\\t%m2,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc,oszc,oszc,oszc,oszc\")]\n-  )\n-\n-(define_insn \"subpsi3\"\n-  [(set (match_operand:PSI 0 \"mra_operand\" \"=RpiSd,RpiSd,??Rmm,??Rmm\")\n-\t(minus:PSI (match_operand:PSI 1 \"mra_operand\" \"0,0,0,0\")\n-\t\t   (match_operand:PSI 2 \"mrai_operand\" \"iRpiSd,?Rmm,iRpiSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"sub.%&\\t%2,%0\"\n-  [(set_attr \"flags\" \"oszc\")]\n-  )\n-\n-(define_expand \"subsi3\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm\")\n-        (minus:SI (match_operand:SI 1 \"mra_operand\" \"0,0,0,0\")\n-                  (match_operand:SI 2 \"mrai_operand\" \"iRsiSd,?Rmm,iRsiSd,?Rmm\")))]\n-  \"TARGET_A24 ||TARGET_A16\"\n-  \"\"\n-)\n-\n-(define_insn \"subsi3_1\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd\")\n-        (minus:SI (match_operand:SI 1 \"mra_operand\" \"0,0,0,0,0,0\")\n-                  (match_operand:SI 2 \"mrai_operand\" \"i,?Rmm,i,RsiSd,?Rmm,RsiSd\")))]\n-  \"TARGET_A16\"\n-  \"*\n-  switch (which_alternative)\n-    {\n-    case 0:\n-      output_asm_insn (\\\"sub.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"sbb.w %X2,%H0\\\";\n-    case 1:\n-      return \\\"sub.w %h2,%h0\\;sbb.w %H2,%H0\\\";\n-    case 2:\n-      output_asm_insn (\\\"sub.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"sbb.w %X2,%H0\\\";\n-    case 3:\n-      return \\\"sub.w %h2,%h0\\;sbb.w %H2,%H0\\\";\n-    case 4:\n-      return \\\"sub.w %h2,%h0\\;sbb.w %H2,%H0\\\";\n-    case 5:\n-      return \\\"sub.w %h2,%h0\\;sbb.w %H2,%H0\\\";\n-    default:\n-      gcc_unreachable ();\n-    }\"\n-  [(set_attr \"flags\" \"x,x,x,x,x,x\")]\n-)\n-\n-(define_insn \"subsi3_2\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm\")\n-        (minus:SI (match_operand:SI 1 \"mra_operand\" \"0,0,0,0\")\n-                  (match_operand:SI 2 \"mrai_operand\" \"iRsiSd,?Rmm,iRsiSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"sub.l\\t%2,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc,oszc,oszc\")]\n-)\n-\n-(define_insn \"negqi2\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=SdRhl,??Rmm\")\n-\t(neg:QI (match_operand:QI 1 \"mra_operand\" \"0,0\")))]\n-  \"\"\n-  \"neg.b\\t%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"neghi2\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=SdRhi,??Rmm\")\n-\t(neg:HI (match_operand:HI 1 \"mra_operand\" \"0,0\")))]\n-  \"\"\n-  \"neg.w\\t%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-; We can negate an SImode by operating on the subparts.  GCC deals\n-; with this itself for larger modes, but not SI.\n-(define_insn \"negsi2\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=SdR03,??Rmm\")\n-\t(neg:SI (match_operand:SI 1 \"mra_operand\" \"0,0\")))]\n-  \"\"\n-  \"not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"absqi2\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RhlSd,??Rmm\")\n-\t(abs:QI (match_operand:QI 1 \"mra_operand\" \"0,0\")))]\n-  \"\"\n-  \"abs.b\\t%0\"\n-  [(set_attr \"flags\" \"oszc\")]\n-  )\n-\n-(define_insn \"abshi2\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,??Rmm\")\n-\t(abs:HI (match_operand:HI 1 \"mra_operand\" \"0,0\")))]\n-  \"\"\n-  \"abs.w\\t%0\"\n-  [(set_attr \"flags\" \"oszc\")]\n-  )\ndiff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md\ndeleted file mode 100644\nindex 75d07ddebe9..00000000000\n--- a/gcc/config/m32c/bitops.md\n+++ /dev/null\n@@ -1,421 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; Bit-wise operations (and, ior, xor, shift)\n-\n-; On the R8C and M16C, \"address\" for bit instructions is usually (but\n-; not always!) the *bit* address, not the *byte* address.  This\n-; confuses gcc, so we avoid cases where gcc would produce the wrong\n-; code.  We're left with absolute addresses and registers, and the odd\n-; case of shifting a bit by a variable.\n-\n-; On the M32C, \"address\" for bit instructions is a regular address,\n-; and the bit number is stored in a separate field.  Thus, we can let\n-; gcc do more interesting things.  However, the M32C cannot set all\n-; the bits in a 16-bit register, which the R8C/M16C can do.\n-\n-; However, it all means that we end up with two sets of patterns, one\n-; for each chip.\n-\n-;;----------------------------------------------------------------------\n-\n-;; First off, all the ways we can set one bit, other than plain IOR.\n-\n-(define_insn \"bset_qi\"\n-  [(set (match_operand:QI 0 \"memsym_operand\" \"+Si\")\n-\t(ior:QI (subreg:QI (ashift:HI (const_int 1)\n-\t\t\t\t      (subreg:QI (match_operand:HI 1 \"a_qi_operand\" \"Raa\") 0)) 0)\n-\t\t(match_dup 0)))]\n-  \"TARGET_A16\"\n-  \"bset\\t%0[%1]\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"bset_hi\"\n-  [(set (zero_extract:HI (match_operand:QI 0 \"memsym_operand\" \"+Si\")\n-\t\t\t (const_int 1)\n-\t\t\t (zero_extend:HI (subreg:QI (match_operand:HI 1 \"a_qi_operand\" \"Raa\") 0)))\n-\t(const_int 1))]\n-  \"TARGET_A16\"\n-  \"bset\\t%0[%1]\"\n-  [(set_attr \"flags\" \"n\")]\n-  )  \n-\n-;;----------------------------------------------------------------------\n-\n-;; Now all the ways we can clear one bit, other than plain AND.\n-\n-; This is odd because the shift patterns use QI counts, but we can't\n-; easily put QI in $aN without causing problems elsewhere.\n-(define_insn \"bclr_qi\"\n-  [(set (zero_extract:HI (match_operand:QI 0 \"memsym_operand\" \"+Si\")\n-\t\t\t (const_int 1)\n-\t\t\t (zero_extend:HI (subreg:QI (match_operand:HI 1 \"a_qi_operand\" \"Raa\") 0)))\n-\t(const_int 0))]\n-  \"TARGET_A16\"\n-  \"bclr\\t%0[%1]\"\n-  [(set_attr \"flags\" \"n\")]\n-  )  \n-\n-\n-;;----------------------------------------------------------------------\n-\n-;; Now the generic patterns.\n-\n-(define_insn \"andqi3_16\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm\")\n-\t(and:QI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-\t\t(match_operand:QI 2 \"mrai_operand\" \"Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm\")))]\n-  \"TARGET_A16\"\n-  \"@\n-   bclr\\t%B2,%0\n-   bclr\\t%B2,%h0\n-   and.b\\t%x2,%0\n-   and.b\\t%x2,%0\n-   and.b\\t%x2,%0\n-   and.b\\t%x2,%0\"\n-  [(set_attr \"flags\" \"n,n,sz,sz,sz,sz\")]\n-  )\n-\n-(define_insn \"andhi3_16\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm\")\n-\t(and:HI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0,0,0,0\")\n-\t\t(match_operand:HI 2 \"mrai_operand\" \"ImB,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd\")))]\n-  \"TARGET_A16\"\n-  \"@\n-   \n-   bclr\\t%B2,%0\n-   bclr\\t%B2-8,1+%0\n-   bclr\\t%B2,%0\n-   and.w\\t%X2,%0\n-   and.w\\t%X2,%0\n-   and.w\\t%X2,%0\n-   and.w\\t%X2,%0\"\n-  [(set_attr \"flags\" \"n,n,n,sz,sz,sz,sz\")]\n-  )\n-\n-(define_insn \"andsi3\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd\")\n-        (and:SI (match_operand:SI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-                (match_operand:SI 2 \"mrai_operand\" \"i,?Rmm,i,RsiSd,?Rmm,RsiSd\")))]\n-  \"\"\n-  \"*\n-  switch (which_alternative)\n-    {\n-    case 0:\n-      output_asm_insn (\\\"and.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"and.w %X2,%H0\\\";\n-    case 1:\n-      return \\\"and.w %h2,%h0\\;and.w %H2,%H0\\\";\n-    case 2:\n-      output_asm_insn (\\\"and.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"and.w %X2,%H0\\\";\n-    case 3:\n-      return \\\"and.w %h2,%h0\\;and.w %H2,%H0\\\";\n-    case 4:\n-      return \\\"and.w %h2,%h0\\;and.w %H2,%H0\\\";\n-    case 5:\n-      return \\\"and.w %h2,%h0\\;and.w %H2,%H0\\\";\n-    default:\n-      gcc_unreachable ();\n-    }\"\n-  [(set_attr \"flags\" \"x,x,x,x,x,x\")]\n-)\n-\n-\n-(define_insn \"iorqi3_16\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm\")\n-\t(ior:QI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-\t\t(match_operand:QI 2 \"mrai_operand\" \"Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm\")))]\n-  \"TARGET_A16\"\n-  \"@\n-   bset\\t%B2,%0\n-   bset\\t%B2,%h0\n-   or.b\\t%x2,%0\n-   or.b\\t%x2,%0\n-   or.b\\t%x2,%0\n-   or.b\\t%x2,%0\"\n-  [(set_attr \"flags\" \"n,n,sz,sz,sz,sz\")]\n-  )\n-\n-(define_insn \"iorhi3_16\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm\")\n-\t(ior:HI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0,0,0,0\")\n-\t\t(match_operand:HI 2 \"mrai_operand\" \"Ilb,Ilw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm\")))]\n-  \"TARGET_A16\"\n-  \"@\n-   bset %B2,%0\n-   bset\\t%B2-8,1+%0\n-   bset\\t%B2,%0\n-   or.w\\t%X2,%0\n-   or.w\\t%X2,%0\n-   or.w\\t%X2,%0\n-   or.w\\t%X2,%0\"\n-  [(set_attr \"flags\" \"n,n,n,sz,sz,sz,sz\")]\n-  )\n-\n-; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n-\n-(define_insn \"andqi3_24\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm\")\n-\t(and:QI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-\t\t(match_operand:QI 2 \"mrai_operand\" \"Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"@\n-   bclr\\t%B2,%0\n-   bclr\\t%B2,%0\n-   and.b\\t%x2,%0\n-   and.b\\t%x2,%0\n-   and.b\\t%x2,%0\n-   and.b\\t%x2,%0\"\n-  [(set_attr \"flags\" \"n,n,sz,sz,sz,sz\")]\n-  )\n-\n-(define_insn \"andhi3_24\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm\")\n-\t(and:HI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0,0,0,0,0\")\n-\t\t(match_operand:HI 2 \"mrai_operand\" \"ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd\")))]\n-  \"TARGET_A24\"\n-  \"@\n-   bclr\\t%B2,%0\n-   bclr\\t%B2-8,1+%0\n-   bclr\\t%B2,%h0\n-   bclr\\t%B2-8,%H0\n-   and.w\\t%X2,%0\n-   and.w\\t%X2,%0\n-   and.w\\t%X2,%0\n-   and.w\\t%X2,%0\"\n-  [(set_attr \"flags\" \"n,n,n,n,sz,sz,sz,sz\")]\n-  )\n-\n-\n-\n-(define_insn \"iorqi3_24\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm\")\n-\t(ior:QI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0\")\n-\t\t(match_operand:QI 2 \"mrai_operand\" \"Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"@\n-   bset\\t%B2,%0\n-   or.b\\t%x2,%0\n-   or.b\\t%x2,%0\n-   or.b\\t%x2,%0\n-   or.b\\t%x2,%0\"\n-  [(set_attr \"flags\" \"n,sz,sz,sz,sz\")]\n-  )\n-\n-(define_insn \"iorhi3_24\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm\")\n-\t(ior:HI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0,0,0,0,0\")\n-\t\t(match_operand:HI 2 \"mrai_operand\" \"Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"@\n-   bset\\t%B2,%0\n-   bset\\t%B2-8,1+%0\n-   bset\\t%B2,%h0\n-   bset\\t%B2-8,%H0\n-   or.w\\t%X2,%0\n-   or.w\\t%X2,%0\n-   or.w\\t%X2,%0\n-   or.w\\t%X2,%0\"\n-  [(set_attr \"flags\" \"n,n,n,n,sz,sz,sz,sz\")]\n-  )\n-\n-\n-; ----------------------------------------------------------------------\n-\n-(define_expand \"andqi3\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"\")\n-\t(and:QI (match_operand:QI 1 \"mra_operand\" \"\")\n-\t\t(match_operand:QI 2 \"mrai_operand\" \"\")))]\n-  \"\"\n-  \"if (TARGET_A16)\n-     emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));\n-   else\n-     emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));\n-   DONE;\"\n-  )\n-\n-(define_expand \"andhi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"\")\n-\t(and:HI (match_operand:HI 1 \"mra_operand\" \"\")\n-\t\t(match_operand:HI 2 \"mrai_operand\" \"\")))]\n-  \"\"\n-  \"if (TARGET_A16)\n-     emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));\n-   else\n-     emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));\n-   DONE;\"\n-  )\n-\n-(define_expand \"iorqi3\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"\")\n-\t(ior:QI (match_operand:QI 1 \"mra_operand\" \"\")\n-\t\t(match_operand:QI 2 \"mrai_operand\" \"\")))]\n-  \"\"\n-  \"if (TARGET_A16)\n-     emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));\n-   else\n-     emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));\n-   DONE;\"\n-  )\n-\n-(define_expand \"iorhi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"\")\n-\t(ior:HI (match_operand:HI 1 \"mra_operand\" \"\")\n-\t\t(match_operand:HI 2 \"mrai_operand\" \"\")))]\n-  \"\"\n-  \"if (TARGET_A16)\n-     emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));\n-   else\n-     emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));\n-   DONE;\"\n-  )\n-\n-(define_insn \"iorsi3\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd\")\n-        (ior:SI (match_operand:SI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-                (match_operand:SI 2 \"mrai_operand\" \"i,?Rmm,i,RsiSd,?Rmm,RsiSd\")))]\n-  \"\"\n-  \"*\n-  switch (which_alternative)\n-    {\n-    case 0:\n-      output_asm_insn (\\\"or.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"or.w %X2,%H0\\\";\n-    case 1:\n-      return \\\"or.w %h2,%h0\\;or.w %H2,%H0\\\";\n-    case 2:\n-      output_asm_insn (\\\"or.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"or.w %X2,%H0\\\";\n-    case 3:\n-      return \\\"or.w %h2,%h0\\;or.w %H2,%H0\\\";\n-    case 4:\n-      return \\\"or.w %h2,%h0\\;or.w %H2,%H0\\\";\n-    case 5:\n-      return \\\"or.w %h2,%h0\\;or.w %H2,%H0\\\";\n-    default:\n-      gcc_unreachable ();\n-    }\"\n-  [(set_attr \"flags\" \"x,x,x,x,x,x\")]\n-)\n-\n-(define_insn \"xorqi3\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RhlSd,RhlSd,??Rmm,??Rmm\")\n-\t(xor:QI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0\")\n-\t\t(match_operand:QI 2 \"mrai_operand\" \"iRhlSd,?Rmm,iRhlSd,?Rmm\")))]\n-  \"\"\n-  \"xor.b\\t%x2,%0\"\n-  [(set_attr \"flags\" \"sz,sz,sz,sz\")]\n-  )\n-\n-(define_insn \"xorhi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,RhiSd,??Rmm,??Rmm\")\n-\t(xor:HI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0\")\n-\t\t(match_operand:HI 2 \"mrai_operand\" \"iRhiSd,?Rmm,iRhiSd,?Rmm\")))]\n-  \"\"\n-  \"xor.w\\t%X2,%0\"\n-  [(set_attr \"flags\" \"sz,sz,sz,sz\")]\n-  )\n-\n-(define_insn \"xorsi3\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd\")\n-        (xor:SI (match_operand:SI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-                (match_operand:SI 2 \"mrai_operand\" \"i,?Rmm,i,RsiSd,?Rmm,RsiSd\")))]\n-  \"\"\n-  \"*\n-  switch (which_alternative)\n-    {\n-    case 0:\n-      output_asm_insn (\\\"xor.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"xor.w %X2,%H0\\\";\n-    case 1:\n-      return \\\"xor.w %h2,%h0\\;xor.w %H2,%H0\\\";\n-    case 2:\n-      output_asm_insn (\\\"xor.w %X2,%h0\\\",operands);\n-      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);\n-      return \\\"xor.w %X2,%H0\\\";\n-    case 3:\n-      return \\\"xor.w %h2,%h0\\;xor.w %H2,%H0\\\";\n-    case 4:\n-      return \\\"xor.w %h2,%h0\\;xor.w %H2,%H0\\\";\n-    case 5:\n-      return \\\"xor.w %h2,%h0\\;xor.w %H2,%H0\\\";\n-    default:\n-      gcc_unreachable ();\n-    }\"\n-  [(set_attr \"flags\" \"x,x,x,x,x,x\")]\n-)\n-\n-(define_insn \"one_cmplqi2\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RhlSd,??Rmm\")\n-\t(not:QI (match_operand:QI 1 \"mra_operand\" \"0,0\")))]\n-  \"\"\n-  \"not.b\\t%0\"\n-  [(set_attr \"flags\" \"sz,sz\")]\n-  )\n-\n-(define_insn \"one_cmplhi2\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,??Rmm\")\n-\t(not:HI (match_operand:HI 1 \"mra_operand\" \"0,0\")))]\n-  \"\"\n-  \"not.w\\t%0\"\n-  [(set_attr \"flags\" \"sz,sz\")]\n-  )\n-\n-; Optimizations using bit opcodes\n-\n-; We need this because combine only looks at three insns at a time,\n-; and the bclr_qi pattern uses four - mov, shift, not, and.  GCC\n-; should never expand this pattern, because it only shifts a constant\n-; by a constant, so gcc should do that itself.\n-(define_insn \"shift1_qi\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=Rqi\")\n-\t(ashift:QI (const_int 1)\n-\t\t   (match_operand 1 \"const_int_operand\" \"In4\")))]\n-  \"\"\n-  \"mov.b\\t#1,%0\\n\\tshl.b\\t%1,%0\"\n-  )\n-(define_insn \"shift1_hi\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=Rhi\")\n-\t(ashift:HI (const_int 1)\n-\t\t   (match_operand 1 \"const_int_operand\" \"In4\")))]\n-  \"\"\n-  \"mov.w\\t#1,%0\\n\\tshl.w\\t%1,%0\"\n-  )\n-\n-; Generic insert-bit expander, needed so that we can use the bit\n-; opcodes for volatile bitfields.\n-\n-(define_expand \"insv\"\n-  [(set (zero_extract:HI (match_operand:HI 0 \"mra_operand\" \"\")\n-\t\t\t (match_operand 1 \"const_int_operand\" \"\")\n-\t\t\t (match_operand 2 \"const_int_operand\" \"\"))\n-\t(match_operand:HI 3 \"const_int_operand\" \"\"))]\n-  \"\"\n-  \"if (m32c_expand_insv (operands))\n-     FAIL;\n-   DONE;\"\n-  )\ndiff --git a/gcc/config/m32c/blkmov.md b/gcc/config/m32c/blkmov.md\ndeleted file mode 100644\nindex b97e8abe0a3..00000000000\n--- a/gcc/config/m32c/blkmov.md\n+++ /dev/null\n@@ -1,241 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2006-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; various block move instructions\n-\n-;; R8C:\n-;;  SMOVB - while (r3--) { *a1-- = *r1ha0--; } - memcpy\n-;;  SMOVF - while (r3--) { *a1++ = *r1ha0++; } - memcpy\n-;;  SSTR  - while (r3--) { *a1++ = [r0l,r0]; } - memset\n-\n-;; M32CM:\n-;;  SCMPU - while (*a0 && *a0 != *a1) { a0++; a1++; } - strcmp\n-;;  SIN   - while (r3--) { *a1++ = *a0; }\n-;;  SMOVB - while (r3--) { *a1-- = *a0--; } - memcpy\n-;;  SMOVF - while (r3--) { *a1++ = *a0++; } - memcpy\n-;;  SMOVU - while (*a1++ = *a0++) ; - strcpy\n-;;  SOUT  - while (r3--) { *a1 = *a0++; }\n-;;  SSTR  - while (r3--) { *a1++ = [r0l,r0]; } - memset\n-\n-\n-\n-;; 0 = destination (mem:BLK ...)\n-;; 1 = source (mem:BLK ...)\n-;; 2 = count\n-;; 3 = alignment\n-(define_expand \"cpymemhi\"\n-  [(match_operand 0 \"ap_operand\" \"\")\n-   (match_operand 1 \"ap_operand\" \"\")\n-   (match_operand 2 \"m32c_r3_operand\" \"\")\n-   (match_operand 3 \"\" \"\")\n-   ]\n-  \"\"\n-  \"if (m32c_expand_cpymemhi(operands)) DONE; FAIL;\"\n-  )\n-\n-;; We can't use mode iterators for these because M16C uses r1h to extend\n-;; the source address, for copying data from ROM to RAM.  We don't yet\n-;; support that, but we need to zero our r1h, so the patterns differ.\n-\n-;; 0 = dest (out)\n-;; 1 = src (out)\n-;; 2 = count (out)\n-;; 3 = dest (in)\n-;; 4 = src (in)\n-;; 5 = count (in)\n-(define_insn \"cpymemhi_bhi_op\"\n-  [(set (mem:QI (match_operand:HI 3 \"ap_operand\" \"0\"))\n-\t(mem:QI (match_operand:HI 4 \"ap_operand\" \"1\")))\n-   (set (match_operand:HI 2 \"m32c_r3_operand\" \"=R3w\")\n-\t(const_int 0))\n-   (set (match_operand:HI 0 \"ap_operand\" \"=Ra1\")\n-\t(plus:HI (match_dup 3)\n-\t\t  (zero_extend:HI (match_operand:HI 5 \"m32c_r3_operand\" \"2\"))))\n-   (set (match_operand:HI 1 \"ap_operand\" \"=Ra0\")\n-\t(plus:HI (match_dup 4)\n-\t\t  (zero_extend:HI (match_dup 5))))\n-   (use (reg:HI R1_REGNO))]\n-  \"TARGET_A16\"\n-  \"mov.b:q\\t#0,r1h\\n\\tsmovf.b\\t; %0[0..%2-1]=r1h%1[]\"\n-  )\n-(define_insn \"cpymemhi_bpsi_op\"\n-  [(set (mem:QI (match_operand:PSI 3 \"ap_operand\" \"0\"))\n-\t(mem:QI (match_operand:PSI 4 \"ap_operand\" \"1\")))\n-   (set (match_operand:HI 2 \"m32c_r3_operand\" \"=R3w\")\n-\t(const_int 0))\n-   (set (match_operand:PSI 0 \"ap_operand\" \"=Ra1\")\n-\t(plus:PSI (match_dup 3)\n-\t\t  (zero_extend:PSI (match_operand:HI 5 \"m32c_r3_operand\" \"2\"))))\n-   (set (match_operand:PSI 1 \"ap_operand\" \"=Ra0\")\n-\t(plus:PSI (match_dup 4)\n-\t\t  (zero_extend:PSI (match_dup 5))))]\n-  \"TARGET_A24\"\n-  \"smovf.b\\t; %0[0..%2-1]=%1[]\"\n-  )\n-(define_insn \"cpymemhi_whi_op\"\n-  [(set (mem:HI (match_operand:HI 3 \"ap_operand\" \"0\"))\n-\t(mem:HI (match_operand:HI 4 \"ap_operand\" \"1\")))\n-   (set (match_operand:HI 2 \"m32c_r3_operand\" \"=R3w\")\n-\t(const_int 0))\n-   (set (match_operand:HI 0 \"ap_operand\" \"=Ra1\")\n-\t(plus:HI (match_dup 3)\n-\t\t  (zero_extend:HI (match_operand:HI 5 \"m32c_r3_operand\" \"2\"))))\n-   (set (match_operand:HI 1 \"ap_operand\" \"=Ra0\")\n-\t(plus:HI (match_dup 4)\n-\t\t  (zero_extend:HI (match_dup 5))))\n-   (use (reg:HI R1_REGNO))]\n-  \"TARGET_A16\"\n-  \"mov.b:q\\t#0,r1h\\n\\tsmovf.w\\t; %0[0..%2-1]=r1h%1[]\"\n-  )\n-(define_insn \"cpymemhi_wpsi_op\"\n-  [(set (mem:HI (match_operand:PSI 3 \"ap_operand\" \"0\"))\n-\t(mem:HI (match_operand:PSI 4 \"ap_operand\" \"1\")))\n-   (set (match_operand:HI 2 \"m32c_r3_operand\" \"=R3w\")\n-\t(const_int 0))\n-   (set (match_operand:PSI 0 \"ap_operand\" \"=Ra1\")\n-\t(plus:PSI (match_dup 3)\n-\t\t  (zero_extend:PSI (match_operand:HI 5 \"m32c_r3_operand\" \"2\"))))\n-   (set (match_operand:PSI 1 \"ap_operand\" \"=Ra0\")\n-\t(plus:PSI (match_dup 4)\n-\t\t  (zero_extend:PSI (match_dup 5))))]\n-  \"TARGET_A24\"\n-  \"smovf.w\\t; %0[0..%2-1]=%1[]\"\n-  )\n-\n-\n-\n-;; 0 = destination (mem:BLK ...)\n-;; 1 = number of bytes\n-;; 2 = value to store\n-;; 3 = alignment\n-(define_expand \"setmemhi\"\n-  [(match_operand 0 \"ap_operand\" \"\")\n-   (match_operand 1 \"m32c_r3_operand\" \"\")\n-   (match_operand 2 \"m32c_r0_operand\" \"\")\n-   (match_operand 3 \"\" \"\")\n-   ]\n-  \"TARGET_A24\"\n-  \"if (m32c_expand_setmemhi(operands)) DONE; FAIL;\"\n-  )\n-\n-;; 0 = address (out)\n-;; 1 = count (out)\n-;; 2 = value (in)\n-;; 3 = address (in)\n-;; 4 = count (in)\n-(define_insn \"setmemhi_b<mode>_op\"\n-  [(set (mem:QI (match_operand:HPSI 3 \"ap_operand\" \"0\"))\n-\t(match_operand:QI 2 \"m32c_r0_operand\" \"R0w\"))\n-   (set (match_operand:HI 1 \"m32c_r3_operand\" \"=R3w\")\n-\t(const_int 0))\n-   (set (match_operand:HPSI 0 \"ap_operand\" \"=Ra1\")\n-\t(plus:HPSI (match_dup 3)\n-\t\t  (zero_extend:HPSI (match_operand:HI 4 \"m32c_r3_operand\" \"1\"))))]\n-  \"TARGET_A24\"\n-  \"sstr.b\\t; %0[0..%1-1]=%2\"\n-  )\n-\n-(define_insn \"setmemhi_w<mode>_op\"\n-  [(set (mem:HI (match_operand:HPSI 3 \"ap_operand\" \"0\"))\n-\t(match_operand:HI 2 \"m32c_r0_operand\" \"R0w\"))\n-   (set (match_operand:HI 1 \"m32c_r3_operand\" \"=R3w\")\n-\t(const_int 0))\n-   (set (match_operand:HPSI 0 \"ap_operand\" \"=Ra1\")\n-\t(plus:HPSI (match_dup 3)\n-\t\t  (zero_extend:HPSI (match_operand:HI 4 \"m32c_r3_operand\" \"1\"))))]\n-  \"TARGET_A24\"\n-  \"sstr.w\\t; %0[0..%1-1]=%2\"\n-  )\n-\n-\n-;; SCMPU sets the flags according to the result of the string\n-;; comparison.  GCC wants the result to be a signed value reflecting\n-;; the result, which it then compares to zero.  Hopefully we can\n-;; optimize that later (see peephole in cond.md).  Meanwhile, the\n-;; strcmp builtin is expanded to a SCMPU followed by a flags-to-int\n-;; pattern in cond.md.\n-\n-;; 0 = result:HI\n-;; 1 = destination (mem:BLK ...)\n-;; 2 = source (mem:BLK ...)\n-;; 3 = alignment\n-\n-(define_expand \"cmpstrsi\"\n-  [(match_operand:HI 0 \"register_operand\" \"\")\n-   (match_operand 1 \"memory_operand\" \"\")\n-   (match_operand 2 \"memory_operand\" \"\")\n-   (match_operand 3 \"const_int_operand\" \"\")\n-   ]\n-  \"TARGET_A24\"\n-  \"if (m32c_expand_cmpstr(operands)) DONE; FAIL;\"\n-  )\n-\n-;; 0 = string1\n-;; 1 = string2\n-\n-(define_insn \"cmpstrhi_op\"\n-  [(set (reg:CC FLG_REGNO)\n-\t(compare:CC (mem:BLK (match_operand:PSI 0 \"ap_operand\" \"Ra0\"))\n-\t\t    (mem:BLK (match_operand:PSI 1 \"ap_operand\" \"Ra1\"))))\n-   (clobber (match_operand:PSI 2 \"ap_operand\" \"=0\"))\n-   (clobber (match_operand:PSI 3 \"ap_operand\" \"=1\"))]\n-  \"TARGET_A24\"\n-  \"scmpu.b\\t; flags := strcmp(*%0,*%1)\"\n-  [(set_attr \"flags\" \"oszc\")]\n-  )\n-\n-\n-\n-;; Note that SMOVU leaves the address registers pointing *after*\n-;; the NUL at the end of the string.  This is not what gcc expects; it\n-;; expects the address registers to point *at* the NUL.  The expander\n-;; must emit a suitable add insn.\n-\n-;; 0 = target: set to &NUL in dest\n-;; 1 = destination (mem:BLK ...)\n-;; 2 = source (mem:BLK ...)\n-\n-(define_expand \"movstr\"\n-  [(match_operand 0 \"m32c_nonimmediate_operand\" \"\")\n-   (match_operand 1 \"\" \"\")\n-   (match_operand 2 \"\" \"\")\n-   ]\n-  \"TARGET_A24\"\n-  \"if (m32c_expand_movstr(operands)) DONE; FAIL;\"\n-  )\n-\n-;; 0 = dest (out)\n-;; 1 = src (out) (clobbered)\n-;; 2 = dest (in)\n-;; 3 = src (in)\n-(define_insn \"movstr_op\"\n-  [(set (mem:BLK (match_operand:PSI 2 \"ap_operand\" \"0\"))\n-\t(mem:BLK (match_operand:PSI 3 \"ap_operand\" \"1\")))\n-   (set (match_operand:PSI 0 \"ap_operand\" \"=Ra1\")\n-\t(plus:PSI (match_dup 2)\n-\t\t  (unspec:PSI [(const_int 0)] UNS_SMOVU)))\n-   (set (match_operand:PSI 1 \"ap_operand\" \"=Ra0\")\n-\t(plus:PSI (match_dup 3)\n-\t\t  (unspec:PSI [(const_int 0)] UNS_SMOVU)))]\n-  \"TARGET_A24\"\n-  \"smovu.b\\t; while (*%2++ := *%3++) != 0\"\n-  [(set_attr \"flags\" \"*\")]\n-  )\n-  \ndiff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md\ndeleted file mode 100644\nindex 218a25f2ced..00000000000\n--- a/gcc/config/m32c/cond.md\n+++ /dev/null\n@@ -1,309 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-; conditionals - cmp, jcc, setcc, etc.\n-\n-; Special note about conditional instructions: GCC always emits the\n-; compare right before the insn, which is good, because m32c's mov\n-; insns modify the flags.  However, this means that any conditional\n-; insn that may require reloading must be kept with its compare until\n-; after reload finishes, else the reload insns might clobber the\n-; flags.  Thus, these rules:\n-;\n-; * the cmp* expanders just save the operands in compare_op0 and\n-;   compare_op1 via m32c_pend_compare.\n-; * conditional insns that won't need reload can call\n-;   m32c_unpend_compare before their expansion.\n-; * other insns must expand to include the compare operands within,\n-;   then split after reload to a separate compare and conditional.\n-\n-; Until support for relaxing is supported in gas, we must assume that\n-; short labels won't reach, so we must use long labels.\n-; Unfortunately, there aren't any conditional jumps with long labels,\n-; so instead we invert the conditional and jump around a regular jump.\n-\n-; Note that we can, at some point in the future, add code to omit the\n-; \"cmp\" portion of the insn if the preceding insn happened to set the\n-; right flags already.  For example, a mov followed by a \"cmp *,0\" is\n-; redundant; the move already set the Z flag.\n-\n-(define_insn_and_split \"cbranch<mode>4\"\n-  [(set (pc) (if_then_else\n-\t      (match_operator 0 \"m32c_cmp_operator\"\n-\t\t\t      [(match_operand:QHPSI 1 \"mra_operand\" \"RraSd\")\n-\t\t\t       (match_operand:QHPSI 2 \"mrai_operand\" \"iRraSd\")])\n-              (label_ref (match_operand 3 \"\" \"\"))\n-\t      (pc)))]\n-  \"\"\n-  \"#\"\n-  \"reload_completed\"\n-  [(set (reg:CC FLG_REGNO)\n-\t(compare (match_dup 1)\n-\t\t (match_dup 2)))\n-   (set (pc) (if_then_else (match_op_dup 0 [(reg:CC FLG_REGNO) (const_int 0)])\n-\t\t\t   (label_ref (match_dup 3))\n-\t\t\t   (pc)))]\n-  \"\"\n-  )\n-\n-(define_insn \"bcc_op\"\n-  [(set (pc)\n-        (if_then_else (match_operator 0 \"ordered_comparison_operator\"\n-\t\t       [(reg:CC FLG_REGNO) (const_int 0)])\n-                      (label_ref (match_operand 1 \"\"))\n-                      (pc)))]\n-  \"\"\n-  \"j%c0\\t%l1\"\n-  [(set_attr \"flags\" \"n\")]\n-)\n-\n-(define_insn \"stzx_16\"\n-  [(set (match_operand:QI 0 \"register_operand\" \"=R0w,R0w,R0w\")\n-\t(if_then_else:QI (eq (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t (match_operand:QI 1 \"const_int_operand\" \"i,i,0\")\n-\t\t\t (match_operand:QI 2 \"const_int_operand\" \"i,0,i\")))]\n-  \"TARGET_A16 && reload_completed\"\n-  \"@\n-   stzx\\t%1,%2,%0\n-   stz\\t%1,%0\n-   stnz\\t%2,%0\"\n-  [(set_attr \"flags\" \"n,n,n\")]\n-)\n-\n-(define_insn \"stzx_24_<mode>\"\n-  [(set (match_operand:QHI 0 \"mra_operand\" \"=RraSd,RraSd,RraSd\")\n-\t(if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t (match_operand:QHI 1 \"const_int_operand\" \"i,i,0\")\n-\t\t\t (match_operand:QHI 2 \"const_int_operand\" \"i,0,i\")))]\n-  \"TARGET_A24 && reload_completed\"\n-  \"@\n-   stzx.<bwl>\\t%1,%2,%0\n-   stz.<bwl>\\t%1,%0\n-   stnz.<bwl>\\t%2,%0\"\n-  [(set_attr \"flags\" \"n,n,n\")])\n-\n-(define_insn_and_split \"stzx_reversed_<mode>\"\n-  [(set (match_operand:QHI 0 \"m32c_r0_operand\" \"=R0w\")\n-\t(if_then_else:QHI (ne (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t (match_operand:QHI 1 \"const_int_operand\" \"\")\n-\t\t\t (match_operand:QHI 2 \"const_int_operand\" \"\")))]\n-  \"(TARGET_A24 || GET_MODE (operands[0]) == QImode) && reload_completed\"\n-  \"#\"\n-  \"\"\n-  [(set (match_dup 0)\n-\t(if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))\n-\t\t      (match_dup 2)\n-\t\t      (match_dup 1)))]\n-  \"\"\n-  )\n-\n-\n-(define_insn \"cmp<mode>_op\"\n-  [(set (reg:CC FLG_REGNO)\n-\t(compare (match_operand:QHPSI 0 \"mra_operand\" \"RraSd\")\n-\t\t (match_operand:QHPSI 1 \"mrai_operand\" \"RraSdi\")))]\n-  \"\"\n-  \"* return m32c_output_compare(insn, operands); \"\n-  [(set_attr \"flags\" \"oszc\")])\n-\n-;; m32c_conditional_register_usage changes the setcc_gen_code array to\n-;; point to the _24 variants if needed.\n-\n-;; We need to keep the compare and conditional sets together through\n-;; reload, because reload might need to add address reloads to the\n-;; set, which would clobber the flags.  By keeping them together, the\n-;; reloads get put before the compare, thus preserving the flags.\n-\n-;; These are the post-split patterns for the conditional sets.\n-\n-(define_insn \"scc_op\"\n-  [(set (match_operand:QI 0 \"register_operand\" \"=Rqi\")\n-\t(match_operator:QI 1 \"ordered_comparison_operator\"\n-\t [(reg:CC FLG_REGNO) (const_int 0)]))]\n-  \"TARGET_A16 && reload_completed\"\n-  \"* return m32c_scc_pattern(operands, GET_CODE (operands[1]));\")\n-\n-(define_insn \"scc_24_op\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd\")\n-\t(match_operator:HI 1 \"ordered_comparison_operator\"\n-\t [(reg:CC FLG_REGNO) (const_int 0)]))]\n-  \"TARGET_A24 && reload_completed\"\n-  \"sc%c1\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-)\n-\n-;; These are the pre-split patterns for the conditional sets.\n-\n-(define_expand \"cstore<mode>4\"\n-  [(set (match_operand:QI 0 \"register_operand\")\n-\t(match_operator:QI 1 \"ordered_comparison_operator\"\n-\t [(match_operand:QHPSI 2 \"mra_operand\")\n-\t  (match_operand:QHPSI 3 \"mrai_operand\")]))]\n-  \"\"\n-{\n-  if (TARGET_A24)\n-    {\n-      rtx o = gen_reg_rtx (HImode);\n-      emit_insn (gen_cstore<mode>4_24 (o, operands[1],\n-\t\t\t\t       operands[2], operands[3]));\n-      emit_move_insn (operands[0], gen_lowpart (QImode, o));\n-      DONE;\n-    }\n-})\n-\n-(define_insn_and_split \"*cstore<mode>4_16\"\n-  [(set (match_operand:QI 0 \"register_operand\" \"=Rqi\")\n-\t(match_operator:QI 1 \"ordered_comparison_operator\"\n-\t [(match_operand:QHPSI 2 \"mra_operand\" \"RraSd\")\n-\t  (match_operand:QHPSI 3 \"mrai_operand\" \"RraSdi\")]))]\n-  \"TARGET_A16\"\n-  \"#\"\n-  \"&& reload_completed\"\n-  [(set (reg:CC FLG_REGNO)\n-\t(compare (match_dup 2)\n-\t\t (match_dup 3)))\n-   (set (match_dup 0)\n-\t(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]\n-  \"\"\n-  [(set_attr \"flags\" \"x\")]\n-)\n-\n-(define_insn_and_split \"cstore<mode>4_24\"\n-  [(set (match_operand:HI 0 \"mra_nopp_operand\" \"=RhiSd\")\n-\t(match_operator:HI 1 \"ordered_comparison_operator\"\n-\t [(match_operand:QHPSI 2 \"mra_operand\" \"RraSd\")\n-\t  (match_operand:QHPSI 3 \"mrai_operand\" \"RraSdi\")]))]\n-  \"TARGET_A24\"\n-  \"#\"\n-  \"&& reload_completed\"\n-  [(set (reg:CC FLG_REGNO)\n-\t(compare (match_dup 2)\n-\t\t (match_dup 3)))\n-   (set (match_dup 0)\n-\t(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]\n-  \"\"\n-  [(set_attr \"flags\" \"x\")]\n-)\n-\n-(define_insn_and_split \"movqicc_<code>_<mode>\"\n-  [(set (match_operand:QI 0 \"register_operand\" \"=R0w\")\n-        (if_then_else:QI (eqne_cond (match_operand:QHPSI 1 \"mra_operand\" \"RraSd\")\n-\t\t\t\t    (match_operand:QHPSI 2 \"mrai_operand\" \"RraSdi\"))\n-\t\t\t  (match_operand:QI 3 \"const_int_operand\" \"\")\n-\t\t\t  (match_operand:QI 4 \"const_int_operand\" \"\")))]\n-  \"\"\n-  \"#\"\n-  \"reload_completed\"\n-  [(set (reg:CC FLG_REGNO)\n-\t(compare (match_dup 1)\n-\t\t (match_dup 2)))\n-   (set (match_dup 0)\n-        (if_then_else:QI (eqne_cond (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t (match_dup 3)\n-\t\t\t (match_dup 4)))]\n-  \"\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn_and_split \"movhicc_<code>_<mode>\"\n-  [(set (match_operand:HI 0 \"register_operand\" \"=R0w\")\n-        (if_then_else:HI (eqne_cond (match_operand:QHPSI 1 \"mra_operand\" \"RraSd\")\n-\t\t\t\t    (match_operand:QHPSI 2 \"mrai_operand\" \"RraSdi\"))\n-\t\t\t  (match_operand:HI 3 \"const_int_operand\" \"\")\n-\t\t\t  (match_operand:HI 4 \"const_int_operand\" \"\")))]\n-  \"TARGET_A24\"\n-  \"#\"\n-  \"reload_completed\"\n-  [(set (reg:CC FLG_REGNO)\n-\t(compare (match_dup 1)\n-\t\t (match_dup 2)))\n-   (set (match_dup 0)\n-        (if_then_else:HI (eqne_cond (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t (match_dup 3)\n-\t\t\t (match_dup 4)))]\n-  \"\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-;; And these are the expanders.\n-\n-(define_expand \"movqicc\"\n-  [(set (match_operand:QI 0 \"register_operand\" \"\")\n-        (if_then_else:QI (match_operand 1 \"m32c_eqne_operator\" \"\")\n-                         (match_operand:QI 2 \"const_int_operand\" \"\")\n-                         (match_operand:QI 3 \"const_int_operand\" \"\")))]\n-  \"\"\n-  \"if (m32c_expand_movcc(operands))\n-     FAIL;\n-   DONE;\"\n-)\n-\n-(define_expand \"movhicc\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"\")\n-        (if_then_else:HI (match_operand 1 \"m32c_eqne_operator\" \"\")\n-                         (match_operand:HI 2 \"const_int_operand\" \"\")\n-                         (match_operand:HI 3 \"const_int_operand\" \"\")))]\n-  \"TARGET_A24\"\n-  \"if (m32c_expand_movcc(operands))\n-     FAIL;\n-   DONE;\"\n-)\n-\n-\n-;; CMP opcodes subtract two values, set the flags, and discard the\n-;; value.  This pattern recovers the sign of the discarded value based\n-;; on the flags.  Operand 0 is set to -1, 0, or 1.  This is used for\n-;; the cmpstr pattern.  For optimal code, this should be removed if\n-;; followed by a suitable CMP insn (see the peephole following).  This\n-;; pattern is 7 bytes and 5 cycles.  If you don't need specific\n-;; values, a 5/4 pattern can be made with SCGT and BMLT to set the\n-;; appropriate bits.\n-\n-(define_insn \"cond_to_int\"\n-  [(set (match_operand:HI 0 \"mra_qi_operand\" \"=Rqi\")\n-\t(if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t (const_int -1)\n-\t\t\t (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t\t\t  (const_int 0)\n-\t\t\t\t\t  (const_int -1))))]\n-  \"TARGET_A24\"\n-  \"sceq\\t%0\\n\\tbmgt\\t1,%h0\\n\\tdec.w\\t%0\"\n-  [(set_attr \"flags\" \"x\")]\n-  )  \n-\n-;; A cond_to_int followed by a compare against zero is essentially a\n-;; no-op.  However, the result of the cond_to_int may be used by later\n-;; insns, so make sure it's dead before deleting its set.\n-\n-(define_peephole2\n-  [(set (match_operand:HI 0 \"mra_qi_operand\" \"\")\n-\t(if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t (const_int -1)\n-\t\t\t (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))\n-\t\t\t\t\t  (const_int 0)\n-\t\t\t\t\t  (const_int -1))))\n-   (set (reg:CC FLG_REGNO)\n-\t(compare (match_operand:HI 1 \"mra_qi_operand\" \"\")\n-\t\t (const_int 0)))\n-   ]\n-  \"rtx_equal_p (operands[0], operands[1])\n-     && dead_or_set_p (peep2_next_insn (1), operands[0])\"\n-  [(const_int 1)]\n-  \"\")\ndiff --git a/gcc/config/m32c/constraints.md b/gcc/config/m32c/constraints.md\ndeleted file mode 100644\nindex 6dd3a2ea34b..00000000000\n--- a/gcc/config/m32c/constraints.md\n+++ /dev/null\n@@ -1,225 +0,0 @@\n-;; m32c constraints\n-;; Copyright (C) 2012-2026 Free Software Foundation, Inc.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published by\n-;; the Free Software Foundation; either version 3, or (at your option)\n-;; any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-(define_register_constraint \"Rsp\" \"SP_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rfb\" \"FB_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rsb\" \"SB_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rcr\" \"TARGET_A16 ? CR_REGS : NO_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rcl\" \"TARGET_A24 ? CR_REGS : NO_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R0w\" \"R0_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R1w\" \"R1_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R2w\" \"R2_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R3w\" \"R3_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R02\" \"R02_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R13\" \"R13_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R03\" \"R03_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rdi\" \"DI_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rhl\" \"HL_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"R23\" \"R23_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Ra0\" \"A0_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Ra1\" \"A1_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Raa\" \"A_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Raw\" \"TARGET_A16 ? A_REGS : NO_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Ral\" \"TARGET_A24 ? A_REGS : NO_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rqi\" \"QI_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rad\" \"AD_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rsi\" \"SI_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rhi\" \"HI_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rhc\" \"HC_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rra\" \"RA_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rfl\" \"FLG_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rmm\" \"fixed_regs[MEM0_REGNO] ? NO_REGS : MEM_REGS\"\n-  \"@internal\")\n-\n-(define_register_constraint \"Rpi\" \"TARGET_A16 ? HI_REGS : RA_REGS\"\n-  \"@internal\")\n-\n-;;; For integer constant constraints:\n-;;; s=signed u=unsigned n=nonzero m=minus l=log2able,\n-;;; [sun] bits [SUN] bytes, p=pointer size\n-;;; I[-0-9][0-9] matches that number\n-\n-(define_constraint \"Is3\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, -8, 7)\")))\n-\n-(define_constraint \"IS1\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, -128, 127)\")))\n-\n-(define_constraint \"IS2\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, -32768, 32767)\")))\n-\n-(define_constraint \"IU2\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, 0, 65535)\")))\n-\n-(define_constraint \"IU3\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, 0, 0x00ffffff)\")))\n-\n-(define_constraint \"In4\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, -8, 8) && ival\")))\n-\n-(define_constraint \"In5\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, -16, 16) && ival\")))\n-\n-(define_constraint \"In6\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, -32, 32) && ival\")))\n-\n-(define_constraint \"IM2\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (ival, -65536, -1)\")))\n-\n-(define_constraint \"Ilb\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (exact_log2 (ival), 0, 7)\")))\n-\n-(define_constraint \"Imb\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (exact_log2 ((ival ^ 0xff) & 0xff), 0, 7)\")))\n-\n-(define_constraint \"ImB\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (exact_log2 ((ival ^ 0xffff) & 0xffff), 0, 7)\")))\n-\n-(define_constraint \"Ilw\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (exact_log2 (ival), 0, 15)\")))\n-\n-(define_constraint \"Imw\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"IN_RANGE (exact_log2 ((ival ^ 0xffff) & 0xffff), 0, 15)\")))\n-\n-(define_constraint \"I00\"\n-  \"@internal\"\n-  (and (match_code \"const_int\")\n-       (match_test \"ival == 0\")))\n-\n-(define_memory_constraint \"SF\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_SF)\"))\n-\n-(define_memory_constraint \"Sd\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Sd)\"))\n-\n-(define_memory_constraint \"Sa\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Sa)\"))\n-\n-(define_memory_constraint \"Si\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Si)\"))\n-\n-(define_memory_constraint \"Ss\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Ss)\"))\n-\n-(define_memory_constraint \"Sf\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Sf)\"))\n-\n-(define_memory_constraint \"Sb\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Sb)\"))\n-\n-(define_memory_constraint \"Sp\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Sp)\"))\n-\n-(define_memory_constraint \"S1\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_S1)\"))\n-\n-(define_constraint \"Rpa\"\n-  \"@internal\"\n-  (match_test \"m32c_matches_constraint_p (op, CONSTRAINT_Rpa)\"))\ndiff --git a/gcc/config/m32c/jump.md b/gcc/config/m32c/jump.md\ndeleted file mode 100644\nindex b9d2e8c1f9b..00000000000\n--- a/gcc/config/m32c/jump.md\n+++ /dev/null\n@@ -1,134 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; jump, conditionals, calls, etc\n-\n-(define_insn \"indirect_jump_16\"\n-  [(set (pc)\n-       (match_operand:HI 0 \"register_operand\" \"Rhi\"))]\n-  \"TARGET_A16\"\n-;  \"jmpi.a\\t%0\"\n-  ; no 16-bit jmpi in r8c\n-  \"push.b #0 | push.w\\t%0 | rts\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"indirect_jump_24\"\n-  [(set (pc)\n-       (match_operand:PSI 0 \"register_operand\" \"Rpi\"))]\n-  \"TARGET_A24\"\n-  \"jmpi.a\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_expand \"indirect_jump\"\n-  [(match_operand 0 \"register_operand\" \"\")]\n-  \"\"\n-  \"if (TARGET_A16)\n-     emit_jump_insn (gen_indirect_jump_16(operands[0]));\n-   else\n-     emit_jump_insn (gen_indirect_jump_24(operands[0]));\n-   DONE;\"\n-  )\n-\n-; We can replace this with jmp.s when gas supports relaxing.  m32c\n-; opcodes are too complicated to try to compute their sizes here, it's\n-; far easier (and more reliable) to let gas worry about it.\n-(define_insn \"jump\"\n-  [(set (pc)\n-\t(label_ref (match_operand 0 \"\" \"\")))]\n-  \"\"\n-  \"jmp.a\\t%l0\"\n-  [(set_attr \"flags\" \"n\")]\n-)\n-\n-; No 16-bit indirect calls on r8c/m16c.  */\n-(define_insn \"call\"\n-  [(call (match_operand:QI 0 \"memory_operand\" \"Si,SaSb,?Rmm\")\n-\t (match_operand 1 \"\" \"\"))\n-   (use (match_operand 2 \"immediate_operand\" \"\"))]\n-  \"\"\n-  \"*\n-switch (which_alternative) {\n-  case 0:\n-    {\n-      HOST_WIDE_INT func_vect_num = \n-      current_function_special_page_vector(XEXP (operands[0], 0));\n-      if (func_vect_num)\n-        {\n-          operands[3] = gen_rtx_CONST_INT (VOIDmode, func_vect_num);\n-          return \\\"jsrs\\t%3\\\";\n-        }\n-      else\n-        return \\\"jsr.a\\t%0\\\";\n-    }\n-  case 1: return TARGET_A16 ? \\\"push.w %a0 | jsr.a\\tm32c_jsri16\\\" : \\\"jsri.a\\t%a0\\\";\n-  case 2: return \\\"jsri.a\\t%a0\\\";\n-  default: gcc_unreachable ();\n-}\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"call_value\"\n-  [(set (match_operand 0 \"m32c_return_operand\" \"=RdiRmmRpa,RdiRmmRpa,RdiRmmRpa\")\n-\t(call (match_operand:QI 1 \"memory_operand\" \"Si,SaSb,?Rmm\")\n-\t      (match_operand 2 \"\" \"\")))\n-   (use (match_operand 3 \"immediate_operand\" \"\"))]\n-  \"\"\n-  \"*\n-switch (which_alternative) {\n-  case 0:\n-    {\n-      HOST_WIDE_INT func_vect_num = \n-      current_function_special_page_vector(XEXP (operands[1], 0));\n-      if (func_vect_num)\n-        {\n-          operands[4] = gen_rtx_CONST_INT (VOIDmode, func_vect_num);\n-          return \\\"jsrs\\t%4\\\";\n-        }\n-      else\n-        return \\\"jsr.a\\t%1\\\";\n-    }\n-  case 1: return TARGET_A16 ? \\\"push.w %a1 | jsr.a\\tm32c_jsri16\\\" : \\\"jsri.a\\t%a1\\\";\n-  case 2: return \\\"jsri.a\\t%a1\\\";\n-  default: gcc_unreachable ();\n-}\"\n-  [(set_attr \"flags\" \"x,x,x\")]\n-  )\n-\n-(define_expand \"untyped_call\"\n-  [(parallel [(call (match_operand 0 \"\" \"\")\n-                    (const_int 0))\n-              (match_operand 1 \"\" \"\")\n-              (match_operand 2 \"\" \"\")])]\n-  \"\"\n-  \"\n-{\n-  int i;\n-\n-  emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));\n-\n-  for (i = 0; i < XVECLEN (operands[2], 0); i++)\n-    {\n-      rtx set = XVECEXP (operands[2], 0, i);\n-      emit_move_insn (SET_DEST (set), SET_SRC (set));\n-    }\n-  DONE;\n-}\")\ndiff --git a/gcc/config/m32c/m32c-modes.def b/gcc/config/m32c/m32c-modes.def\ndeleted file mode 100644\nindex c4d9baf7a5d..00000000000\n--- a/gcc/config/m32c/m32c-modes.def\n+++ /dev/null\n@@ -1,28 +0,0 @@\n-/* Target-Specific Modes for R8C/M16C/M32C\n-   Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   You should have received a copy of the GNU General Public License\n-   along with GCC; see the file COPYING3.  If not see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-/* 24-bit pointers, whole */\n-/*INT_MODE (PI, 3);*/\n-\n-/* 24-bit pointers, in 32-bit units */\n-PARTIAL_INT_MODE (SI, 24, PSI);\n-\n-/* 48-bit MULEX result */\n-/* INT_MODE (MI, 6); */\ndiff --git a/gcc/config/m32c/m32c-pragma.cc b/gcc/config/m32c/m32c-pragma.cc\ndeleted file mode 100644\nindex b92f3ca7517..00000000000\n--- a/gcc/config/m32c/m32c-pragma.cc\n+++ /dev/null\n@@ -1,128 +0,0 @@\n-/* M32C Pragma support\n-   Copyright (C) 2004-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat, Inc.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify\n-   it under the terms of the GNU General Public License as published by\n-   the Free Software Foundation; either version 3, or (at your option)\n-   any later version.\n-\n-   GCC is distributed in the hope that it will be useful,\n-   but WITHOUT ANY WARRANTY; without even the implied warranty of\n-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n-   GNU General Public License for more details.\n-\n-   You should have received a copy of the GNU General Public License\n-   along with GCC; see the file COPYING3.  If not see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-#define IN_TARGET_CODE 1\n-\n-#include \"config.h\"\n-#include \"system.h\"\n-#include \"coretypes.h\"\n-#include \"tm.h\"\n-#include \"c-family/c-common.h\"\n-#include \"c-family/c-pragma.h\"\n-#include \"m32c-protos.h\"\n-\n-/* Implements the \"GCC memregs\" pragma.  This pragma takes only an\n-   integer, and is semantically identical to the -memregs= command\n-   line option.  The only catch is, the programmer should only use\n-   this pragma at the beginning of the file (preferably, in some\n-   project-wide header) to avoid ABI changes related to changing the\n-   list of available \"registers\".  */\n-static void\n-m32c_pragma_memregs (cpp_reader * reader ATTRIBUTE_UNUSED)\n-{\n-  /* on off */\n-  tree val;\n-  enum cpp_ttype type;\n-  HOST_WIDE_INT i;\n-\n-  type = pragma_lex (&val);\n-  if (type == CPP_NUMBER)\n-    {\n-      if (tree_fits_uhwi_p (val))\n-\t{\n-\t  i = tree_to_uhwi (val);\n-\n-\t  type = pragma_lex (&val);\n-\t  if (type != CPP_EOF)\n-\t    warning (0, \"junk at end of %<#pragma GCC memregs%> [0-16]\");\n-\n-\t  if (i >= 0 && i <= 16)\n-\t    {\n-\t      if (!ok_to_change_target_memregs)\n-\t\t{\n-\t\t  warning (0,\n-\t\t\t   \"%<#pragma GCC memregs%> must precede any function declarations\");\n-\t\t  return;\n-\t\t}\n-\t      target_memregs = i;\n-\t      m32c_conditional_register_usage ();\n-\t    }\n-\t  else\n-\t    {\n-\t      warning (0, \"%<#pragma GCC memregs%> takes a number [0-16]\");\n-\t    }\n-\n-\t  return;\n-\t}\n-    }\n-\n-  error (\"%<#pragma GCC memregs%> takes a number [0-16]\");\n-}\n-\n-/* Implements the \"pragma ADDRESS\" pragma.  This pragma takes a\n-   variable name and an address, and arranges for that variable to be\n-   \"at\" that address.  The variable is also made volatile.  */\n-static void\n-m32c_pragma_address (cpp_reader * reader ATTRIBUTE_UNUSED)\n-{\n-  /* on off */\n-  tree var, addr;\n-  enum cpp_ttype type;\n-\n-  type = pragma_lex (&var);\n-  if (type == CPP_NAME)\n-    {\n-      type = pragma_lex (&addr);\n-      if (type == CPP_NUMBER)\n-\t{\n-\t  if (var != error_mark_node)\n-\t    {\n-\t      unsigned uaddr = tree_to_uhwi (addr);\n-\t      m32c_note_pragma_address (IDENTIFIER_POINTER (var), uaddr);\n-\t    }\n-\n-\t  type = pragma_lex (&var);\n-\t  if (type != CPP_EOF)\n-\t    {\n-\t      error (\"junk at end of %<#pragma ADDRESS%>\");\n-\t    }\n-\t  return;\n-\t}\n-    }\n-  error (\"malformed %<#pragma ADDRESS%> variable address\");\n-}\n-\n-/* Implements REGISTER_TARGET_PRAGMAS.  */\n-void\n-m32c_register_pragmas (void)\n-{\n-  c_register_pragma (\"GCC\", \"memregs\", m32c_pragma_memregs);\n-  c_register_pragma (NULL, \"ADDRESS\", m32c_pragma_address);\n-  c_register_pragma (NULL, \"address\", m32c_pragma_address);\n-\n-  /* R8C and M16C have 16-bit pointers in a 20-bit address zpace.\n-     M32C has 24-bit pointers in a 24-bit address space, so does not\n-     need far pointers, but we accept the qualifier anyway, as a\n-     no-op.  */\n-  if (TARGET_A16)\n-    c_register_addr_space (\"__far\", ADDR_SPACE_FAR);\n-  else\n-    c_register_addr_space (\"__far\", ADDR_SPACE_GENERIC);\n-}\ndiff --git a/gcc/config/m32c/m32c-protos.h b/gcc/config/m32c/m32c-protos.h\ndeleted file mode 100644\nindex 822021a054e..00000000000\n--- a/gcc/config/m32c/m32c-protos.h\n+++ /dev/null\n@@ -1,80 +0,0 @@\n-/* Target Prototypes for R8C/M16C/M32C\n-   Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   You should have received a copy of the GNU General Public License\n-   along with GCC; see the file COPYING3.  If not see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-void m32c_conditional_register_usage (void);\n-unsigned int m32c_dwarf_frame_regnum (int);\n-int  m32c_eh_return_data_regno (int);\n-void m32c_emit_epilogue (void);\n-void m32c_emit_prologue (void);\n-int  m32c_epilogue_uses (int);\n-int  m32c_function_arg_regno_p (int);\n-void m32c_init_expanders (void);\n-int  m32c_initial_elimination_offset (int, int);\n-void m32c_output_reg_pop (FILE *, int);\n-void m32c_output_reg_push (FILE *, int);\n-poly_int64 m32c_push_rounding (poly_int64);\n-void m32c_register_pragmas (void);\n-void m32c_note_pragma_address (const char *, unsigned);\n-int  m32c_regno_ok_for_base_p (int);\n-int  m32c_trampoline_alignment (void);\n-int  m32c_trampoline_size (void);\n-\n-#ifdef RTX_CODE\n-\n-rtx  m32c_eh_return_stackadj_rtx (void);\n-void m32c_emit_eh_epilogue (rtx);\n-int  m32c_expand_cmpstr (rtx *);\n-int  m32c_expand_insv (rtx *);\n-int  m32c_expand_movcc (rtx *);\n-int  m32c_expand_cpymemhi (rtx *);\n-int  m32c_expand_movstr (rtx *);\n-void m32c_expand_neg_mulpsi3 (rtx *);\n-int  m32c_expand_setmemhi (rtx *);\n-bool m32c_matches_constraint_p (rtx, int);\n-bool m32c_illegal_subreg_p (rtx);\n-bool m32c_immd_dbl_mov (rtx *, machine_mode);\n-rtx  m32c_incoming_return_addr_rtx (void);\n-int  m32c_legitimize_reload_address (rtx *, machine_mode, int, int, int);\n-int  m32c_limit_reload_class (machine_mode, int);\n-bool m32c_mov_ok (rtx *, machine_mode);\n-char * m32c_output_compare (rtx_insn *, rtx *);\n-int  m32c_prepare_move (rtx *, machine_mode);\n-int  m32c_prepare_shift (rtx *, int, int);\n-int  m32c_reg_ok_for_base_p (rtx, int);\n-enum reg_class m32c_regno_reg_class (int);\n-rtx  m32c_return_addr_rtx (int);\n-const char *m32c_scc_pattern (rtx *, RTX_CODE);\n-int  m32c_secondary_reload_class (int, machine_mode, rtx);\n-int  m32c_split_move (rtx *, machine_mode, int);\n-int  m32c_split_psi_p (rtx *);\n-int current_function_special_page_vector (rtx);\n-\n-#endif\n-\n-#ifdef TREE_CODE\n-\n-tree m32c_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);\n-void m32c_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);\n-bool m32c_promote_function_return (const_tree);\n-int  m32c_special_page_vector_p (tree);\n-void m32c_output_aligned_common (FILE *, tree, const char *,\n-\t\t\t\t int, int, int);\n-\n-#endif\ndiff --git a/gcc/config/m32c/m32c.abi b/gcc/config/m32c/m32c.abi\ndeleted file mode 100644\nindex a77f081f6e6..00000000000\n--- a/gcc/config/m32c/m32c.abi\n+++ /dev/null\n@@ -1,131 +0,0 @@\n-   Target Definitions for R8C/M16C/M32C\n-   Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   You should have received a copy of the GNU General Public License\n-   along with GCC; see the file COPYING3.  If not see\n-   <http://www.gnu.org/licenses/>.\n-\n-\n-These are just some random notes I used during development of this\n-port.  Please don't consider these to be \"official\" specifications,\n-just additional information to help make the code easier to\n-understand.\n-\n-\n-Frame\n-=====\n-\n-\t+--------------------\n-\t| incoming args\n-\t+--------------------\n-\t| return Address\n-osp ->\t+--------------------\n-\t| saved fp\n-fp ->\t+--------------------\n-\t| local data\n-\t+--------------------\n-\t| saved regs\n-\t+--------------------\n-\t| outgoing args (opt)\n-sp ->\t+--------------------\n-\n-Argument Passing\n-================\n-\n-r8c, m16c\n----------\n-\n-First arg may be passed in r1l or r1 if it (1) fits (QImode or\n-HImode), (2) is named, and (3) is an integer or pointer type (no\n-structs, floats, etc).  Otherwise, it's passed on the stack.\n-\n-Second arg may be passed in r2, same restrictions (but not QImode),\n-even if the first arg is passed on the stack.\n-\n-Third and further args are passed on the stack.  No padding is used,\n-stack \"alignment\" is 8 bits.\n-\n-m32cm, m32c\n------------\n-First arg may be passed in r0l or r0, same restrictions as above.\n-\n-Second and further args are passed on the stack.  Padding is used\n-after QImode parameters (i.e. lower-addressed byte is the value,\n-higher-addressed byte is the padding), stack \"alignment\" is 16 bits.\n-\n-\n-Return Value\n-============\n-\n-r8c, m16c\n----------\n-\n-QImode in r0l\n-HImode in r0\n-near pointer in r0\n-(desired)\n-SImode in r2r0\n-far pointer in r2r0\n-(actual)\n-Anything bigger than 16 bits is returned in memory, at mem0 (mem0\n-through mem15 are provided by libgcc.a)\n-\n-Aggregate values (regardless of size) are returned by pushing a\n-pointer to a temporary area on the stack after the args are pushed.\n-The function fills in this area with the value.  Note that this\n-pointer on the stack does not affect how register arguments, if any,\n-are configured.\n-\n-m32cm, m32c\n------------\n-Same.\n-\n-\n-Registers Preserved Across Calls\n-================================\n-\n-r8c, m16c\n----------\n-sb, fb, sp (i.e. nearly all registers are call clobbered)\n-\n-m32cm, m32c\n------------\n-r1, r2, r3, a0, a1, sb, fb, sp\n-(except when used for return values)\n-\n-\n-Interrupt Handlers\n-==================\n-\n-The stack frame is slightly different for interrupt handlers, because\n-(1) we don't have a usable parent frame, and (2) we have to use\n-special instructions to return and thus must save/restore everything\n-differently.\n-\n-\t+--------------------\n-\t| program state\n-osp ->\t+--------------------\n-\t| return address\n-\t+--------------------\n-\t| saved r0..fp (pushm)\n-fp ->\t+--------------------\n-\t| local data\n-\t+--------------------\n-\t| saved regs mem0..mem15\n-\t+--------------------\n-\t| outgoing args (opt)\n-sp ->\t+--------------------\n-\ndiff --git a/gcc/config/m32c/m32c.cc b/gcc/config/m32c/m32c.cc\ndeleted file mode 100644\nindex b18246df05e..00000000000\n--- a/gcc/config/m32c/m32c.cc\n+++ /dev/null\n@@ -1,4511 +0,0 @@\n-/* Target Code for R8C/M16C/M32C\n-   Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   You should have received a copy of the GNU General Public License\n-   along with GCC; see the file COPYING3.  If not see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-#define IN_TARGET_CODE 1\n-\n-#include \"config.h\"\n-#include \"system.h\"\n-#include \"coretypes.h\"\n-#include \"backend.h\"\n-#include \"target.h\"\n-#include \"rtl.h\"\n-#include \"tree.h\"\n-#include \"stringpool.h\"\n-#include \"attribs.h\"\n-#include \"df.h\"\n-#include \"memmodel.h\"\n-#include \"tm_p.h\"\n-#include \"optabs.h\"\n-#include \"regs.h\"\n-#include \"emit-rtl.h\"\n-#include \"recog.h\"\n-#include \"diagnostic-core.h\"\n-#include \"output.h\"\n-#include \"insn-attr.h\"\n-#include \"flags.h\"\n-#include \"reload.h\"\n-#include \"stor-layout.h\"\n-#include \"varasm.h\"\n-#include \"calls.h\"\n-#include \"explow.h\"\n-#include \"expr.h\"\n-#include \"tm-constrs.h\"\n-#include \"builtins.h\"\n-#include \"opts.h\"\n-\n-/* This file should be included last.  */\n-#include \"target-def.h\"\n-\n-/* Prototypes */\n-\n-/* Used by m32c_pushm_popm.  */\n-typedef enum\n-{\n-  PP_pushm,\n-  PP_popm,\n-  PP_justcount\n-} Push_Pop_Type;\n-\n-static bool m32c_function_needs_enter (void);\n-static tree interrupt_handler (tree *, tree, tree, int, bool *);\n-static tree function_vector_handler (tree *, tree, tree, int, bool *);\n-static int interrupt_p (tree node);\n-static int bank_switch_p (tree node);\n-static int fast_interrupt_p (tree node);\n-static int interrupt_p (tree node);\n-static bool m32c_asm_integer (rtx, unsigned int, int);\n-static int m32c_comp_type_attributes (const_tree, const_tree);\n-static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);\n-static struct machine_function *m32c_init_machine_status (void);\n-static void m32c_insert_attributes (tree, tree *);\n-static bool m32c_legitimate_address_p (machine_mode, rtx, bool,\n-\t\t\t\t       code_helper = ERROR_MARK);\n-static bool m32c_addr_space_legitimate_address_p (machine_mode, rtx, bool,\n-\t\t\t\t\t\t  addr_space_t,\n-\t\t\t\t\t\t  code_helper = ERROR_MARK);\n-static rtx m32c_function_arg (cumulative_args_t, const function_arg_info &);\n-static bool m32c_pass_by_reference (cumulative_args_t,\n-\t\t\t\t    const function_arg_info &);\n-static void m32c_function_arg_advance (cumulative_args_t,\n-\t\t\t\t       const function_arg_info &);\n-static unsigned int m32c_function_arg_boundary (machine_mode, const_tree);\n-static int m32c_pushm_popm (Push_Pop_Type);\n-static bool m32c_strict_argument_naming (cumulative_args_t);\n-static rtx m32c_struct_value_rtx (tree, int);\n-static rtx m32c_subreg (machine_mode, rtx, machine_mode, int);\n-static int need_to_save (int);\n-static rtx m32c_function_value (const_tree, const_tree, bool);\n-static rtx m32c_libcall_value (machine_mode, const_rtx);\n-\n-/* Returns true if an address is specified, else false.  */\n-static bool m32c_get_pragma_address (const char *varname, unsigned *addr);\n-\n-static bool m32c_hard_regno_mode_ok (unsigned int, machine_mode);\n-\n-#define SYMBOL_FLAG_FUNCVEC_FUNCTION    (SYMBOL_FLAG_MACH_DEP << 0)\n-\n-#define streq(a,b) (strcmp ((a), (b)) == 0)\n-\n-/* Internal support routines */\n-\n-/* Debugging statements are tagged with DEBUG0 only so that they can\n-   be easily enabled individually, by replacing the '0' with '1' as\n-   needed.  */\n-#define DEBUG0 0\n-#define DEBUG1 1\n-\n-#if DEBUG0\n-#include \"print-tree.h\"\n-/* This is needed by some of the commented-out debug statements\n-   below.  */\n-static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;\n-#endif\n-static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;\n-\n-/* These are all to support encode_pattern().  */\n-static char pattern[30], *patternp;\n-static GTY(()) rtx patternr[30];\n-#define RTX_IS(x) (streq (pattern, x))\n-\n-/* Some macros to simplify the logic throughout this file.  */\n-#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)\n-#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))\n-\n-#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)\n-#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))\n-\n-static int\n-far_addr_space_p (rtx x)\n-{\n-  if (GET_CODE (x) != MEM)\n-    return 0;\n-#if DEBUG0\n-  fprintf(stderr, \"\\033[35mfar_addr_space: \"); debug_rtx(x);\n-  fprintf(stderr, \" = %d\\033[0m\\n\", MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);\n-#endif\n-  return MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR;\n-}\n-\n-/* We do most RTX matching by converting the RTX into a string, and\n-   using string compares.  This vastly simplifies the logic in many of\n-   the functions in this file.\n-\n-   On exit, pattern[] has the encoded string (use RTX_IS(\"...\") to\n-   compare it) and patternr[] has pointers to the nodes in the RTX\n-   corresponding to each character in the encoded string.  The latter\n-   is mostly used by print_operand().\n-\n-   Unrecognized patterns have '?' in them; this shows up when the\n-   assembler complains about syntax errors.\n-*/\n-\n-static void\n-encode_pattern_1 (rtx x)\n-{\n-  int i;\n-\n-  if (patternp == pattern + sizeof (pattern) - 2)\n-    {\n-      patternp[-1] = '?';\n-      return;\n-    }\n-\n-  patternr[patternp - pattern] = x;\n-\n-  switch (GET_CODE (x))\n-    {\n-    case REG:\n-      *patternp++ = 'r';\n-      break;\n-    case SUBREG:\n-      if (GET_MODE_SIZE (GET_MODE (x)) !=\n-\t  GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))\n-\t*patternp++ = 'S';\n-      if (GET_MODE (x) == PSImode\n-\t  && GET_CODE (XEXP (x, 0)) == REG)\n-\t*patternp++ = 'S';\n-      encode_pattern_1 (XEXP (x, 0));\n-      break;\n-    case MEM:\n-      *patternp++ = 'm';\n-      /* FALLTHRU */\n-    case CONST:\n-      encode_pattern_1 (XEXP (x, 0));\n-      break;\n-    case SIGN_EXTEND:\n-      *patternp++ = '^';\n-      *patternp++ = 'S';\n-      encode_pattern_1 (XEXP (x, 0));\n-      break;\n-    case ZERO_EXTEND:\n-      *patternp++ = '^';\n-      *patternp++ = 'Z';\n-      encode_pattern_1 (XEXP (x, 0));\n-      break;\n-    case PLUS:\n-      *patternp++ = '+';\n-      encode_pattern_1 (XEXP (x, 0));\n-      encode_pattern_1 (XEXP (x, 1));\n-      break;\n-    case PRE_DEC:\n-      *patternp++ = '>';\n-      encode_pattern_1 (XEXP (x, 0));\n-      break;\n-    case POST_INC:\n-      *patternp++ = '<';\n-      encode_pattern_1 (XEXP (x, 0));\n-      break;\n-    case LO_SUM:\n-      *patternp++ = 'L';\n-      encode_pattern_1 (XEXP (x, 0));\n-      encode_pattern_1 (XEXP (x, 1));\n-      break;\n-    case HIGH:\n-      *patternp++ = 'H';\n-      encode_pattern_1 (XEXP (x, 0));\n-      break;\n-    case SYMBOL_REF:\n-      *patternp++ = 's';\n-      break;\n-    case LABEL_REF:\n-      *patternp++ = 'l';\n-      break;\n-    case CODE_LABEL:\n-      *patternp++ = 'c';\n-      break;\n-    case CONST_INT:\n-    case CONST_DOUBLE:\n-      *patternp++ = 'i';\n-      break;\n-    case UNSPEC:\n-      *patternp++ = 'u';\n-      *patternp++ = '0' + XCINT (x, 1, UNSPEC);\n-      for (i = 0; i < XVECLEN (x, 0); i++)\n-\tencode_pattern_1 (XVECEXP (x, 0, i));\n-      break;\n-    case USE:\n-      *patternp++ = 'U';\n-      break;\n-    case PARALLEL:\n-      *patternp++ = '|';\n-      for (i = 0; i < XVECLEN (x, 0); i++)\n-\tencode_pattern_1 (XVECEXP (x, 0, i));\n-      break;\n-    case EXPR_LIST:\n-      *patternp++ = 'E';\n-      encode_pattern_1 (XEXP (x, 0));\n-      if (XEXP (x, 1))\n-\tencode_pattern_1 (XEXP (x, 1));\n-      break;\n-    default:\n-      *patternp++ = '?';\n-#if DEBUG0\n-      fprintf (stderr, \"can't encode pattern %s\\n\",\n-\t       GET_RTX_NAME (GET_CODE (x)));\n-      debug_rtx (x);\n-#endif\n-      break;\n-    }\n-}\n-\n-static void\n-encode_pattern (rtx x)\n-{\n-  patternp = pattern;\n-  encode_pattern_1 (x);\n-  *patternp = 0;\n-}\n-\n-/* Since register names indicate the mode they're used in, we need a\n-   way to determine which name to refer to the register with.  Called\n-   by print_operand().  */\n-\n-static const char *\n-reg_name_with_mode (int regno, machine_mode mode)\n-{\n-  int mlen = GET_MODE_SIZE (mode);\n-  if (regno == R0_REGNO && mlen == 1)\n-    return \"r0l\";\n-  if (regno == R0_REGNO && (mlen == 3 || mlen == 4))\n-    return \"r2r0\";\n-  if (regno == R0_REGNO && mlen == 6)\n-    return \"r2r1r0\";\n-  if (regno == R0_REGNO && mlen == 8)\n-    return \"r3r1r2r0\";\n-  if (regno == R1_REGNO && mlen == 1)\n-    return \"r1l\";\n-  if (regno == R1_REGNO && (mlen == 3 || mlen == 4))\n-    return \"r3r1\";\n-  if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))\n-    return \"a1a0\";\n-  return reg_names[regno];\n-}\n-\n-/* How many bytes a register uses on stack when it's pushed.  We need\n-   to know this because the push opcode needs to explicitly indicate\n-   the size of the register, even though the name of the register\n-   already tells it that.  Used by m32c_output_reg_{push,pop}, which\n-   is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}.  */\n-\n-static int\n-reg_push_size (int regno)\n-{\n-  switch (regno)\n-    {\n-    case R0_REGNO:\n-    case R1_REGNO:\n-      return 2;\n-    case R2_REGNO:\n-    case R3_REGNO:\n-    case FLG_REGNO:\n-      return 2;\n-    case A0_REGNO:\n-    case A1_REGNO:\n-    case SB_REGNO:\n-    case FB_REGNO:\n-    case SP_REGNO:\n-      if (TARGET_A16)\n-\treturn 2;\n-      else\n-\treturn 3;\n-    default:\n-      gcc_unreachable ();\n-    }\n-}\n-\n-/* Given two register classes, find the largest intersection between\n-   them.  If there is no intersection, return RETURNED_IF_EMPTY\n-   instead.  */\n-static reg_class_t\n-reduce_class (reg_class_t original_class, reg_class_t limiting_class,\n-\t      reg_class_t returned_if_empty)\n-{\n-  HARD_REG_SET cc;\n-  int i;\n-  reg_class_t best = NO_REGS;\n-  unsigned int best_size = 0;\n-\n-  if (original_class == limiting_class)\n-    return original_class;\n-\n-  cc = reg_class_contents[original_class] & reg_class_contents[limiting_class];\n-\n-  for (i = 0; i < LIM_REG_CLASSES; i++)\n-    {\n-      if (hard_reg_set_subset_p (reg_class_contents[i], cc))\n-\tif (best_size < reg_class_size[i])\n-\t  {\n-\t    best = (reg_class_t) i;\n-\t    best_size = reg_class_size[i];\n-\t  }\n-\n-    }\n-  if (best == NO_REGS)\n-    return returned_if_empty;\n-  return best;\n-}\n-\n-/* Used by m32c_register_move_cost to determine if a move is\n-   impossibly expensive.  */\n-static bool\n-class_can_hold_mode (reg_class_t rclass, machine_mode mode)\n-{\n-  /* Cache the results:  0=untested  1=no  2=yes */\n-  static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];\n-\n-  if (results[(int) rclass][mode] == 0)\n-    {\n-      int r;\n-      results[rclass][mode] = 1;\n-      for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)\n-\tif (in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, r)\n-\t    && m32c_hard_regno_mode_ok (r, mode))\n-\t  {\n-\t    results[rclass][mode] = 2;\n-\t    break;\n-\t  }\n-    }\n-\n-#if DEBUG0\n-  fprintf (stderr, \"class %s can hold %s? %s\\n\",\n-\t   class_names[(int) rclass], mode_name[mode],\n-\t   (results[rclass][mode] == 2) ? \"yes\" : \"no\");\n-#endif\n-  return results[(int) rclass][mode] == 2;\n-}\n-\n-/* Run-time Target Specification.  */\n-\n-/* Memregs are memory locations that gcc treats like general\n-   registers, as there are a limited number of true registers and the\n-   m32c families can use memory in most places that registers can be\n-   used.\n-\n-   However, since memory accesses are more expensive than registers,\n-   we allow the user to limit the number of memregs available, in\n-   order to try to persuade gcc to try harder to use real registers.\n-\n-   Memregs are provided by lib1funcs.S.\n-*/\n-\n-int ok_to_change_target_memregs = TRUE;\n-\n-/* Implements TARGET_OPTION_OVERRIDE.  */\n-\n-#undef TARGET_OPTION_OVERRIDE\n-#define TARGET_OPTION_OVERRIDE m32c_option_override\n-\n-static void\n-m32c_option_override (void)\n-{\n-  /* We limit memregs to 0..16, and provide a default.  */\n-  if (OPTION_SET_P (target_memregs))\n-    {\n-      if (target_memregs < 0 || target_memregs > 16)\n-\terror (\"invalid target memregs value %<%d%>\", target_memregs);\n-    }\n-  else\n-    target_memregs = 16;\n-\n-  if (TARGET_A24)\n-    flag_ivopts = 0;\n-\n-  /* This target defaults to strict volatile bitfields.  */\n-  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))\n-    flag_strict_volatile_bitfields = 1;\n-\n-  /* r8c/m16c have no 16-bit indirect call, so thunks are involved.\n-     This is always worse than an absolute call.  */\n-  if (TARGET_A16)\n-    flag_no_function_cse = 1;\n-\n-  /* This wants to put insns between compares and their jumps.  */\n-  /* FIXME: The right solution is to properly trace the flags register\n-     values, but that is too much work for stage 4.  */\n-  flag_combine_stack_adjustments = 0;\n-}\n-\n-#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE\n-#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change\n-\n-static void\n-m32c_override_options_after_change (void)\n-{\n-  if (TARGET_A16)\n-    flag_no_function_cse = 1;\n-}\n-\n-/* Defining data structures for per-function information */\n-\n-/* The usual; we set up our machine_function data.  */\n-static struct machine_function *\n-m32c_init_machine_status (void)\n-{\n-  return ggc_cleared_alloc<machine_function> ();\n-}\n-\n-/* Implements INIT_EXPANDERS.  We just set up to call the above\n-   function.  */\n-void\n-m32c_init_expanders (void)\n-{\n-  init_machine_status = m32c_init_machine_status;\n-}\n-\n-/* Storage Layout */\n-\n-/* Register Basics */\n-\n-/* Basic Characteristics of Registers */\n-\n-/* Whether a mode fits in a register is complex enough to warrant a\n-   table.  */\n-static struct\n-{\n-  char qi_regs;\n-  char hi_regs;\n-  char pi_regs;\n-  char si_regs;\n-  char di_regs;\n-} nregs_table[FIRST_PSEUDO_REGISTER] =\n-{\n-  { 1, 1, 2, 2, 4 },\t\t/* r0 */\n-  { 0, 1, 0, 0, 0 },\t\t/* r2 */\n-  { 1, 1, 2, 2, 0 },\t\t/* r1 */\n-  { 0, 1, 0, 0, 0 },\t\t/* r3 */\n-  { 0, 1, 1, 0, 0 },\t\t/* a0 */\n-  { 0, 1, 1, 0, 0 },\t\t/* a1 */\n-  { 0, 1, 1, 0, 0 },\t\t/* sb */\n-  { 0, 1, 1, 0, 0 },\t\t/* fb */\n-  { 0, 1, 1, 0, 0 },\t\t/* sp */\n-  { 1, 1, 1, 0, 0 },\t\t/* pc */\n-  { 0, 0, 0, 0, 0 },\t\t/* fl */\n-  { 1, 1, 1, 0, 0 },\t\t/* ap */\n-  { 1, 1, 2, 2, 4 },\t\t/* mem0 */\n-  { 1, 1, 2, 2, 4 },\t\t/* mem1 */\n-  { 1, 1, 2, 2, 4 },\t\t/* mem2 */\n-  { 1, 1, 2, 2, 4 },\t\t/* mem3 */\n-  { 1, 1, 2, 2, 4 },\t\t/* mem4 */\n-  { 1, 1, 2, 2, 0 },\t\t/* mem5 */\n-  { 1, 1, 2, 2, 0 },\t\t/* mem6 */\n-  { 1, 1, 0, 0, 0 },\t\t/* mem7 */\n-};\n-\n-/* Implements TARGET_CONDITIONAL_REGISTER_USAGE.  We adjust the number\n-   of available memregs, and select which registers need to be preserved\n-   across calls based on the chip family.  */\n-\n-#undef TARGET_CONDITIONAL_REGISTER_USAGE\n-#define TARGET_CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage\n-void\n-m32c_conditional_register_usage (void)\n-{\n-  int i;\n-\n-  if (target_memregs >= 0 && target_memregs <= 16)\n-    {\n-      /* The command line option is bytes, but our \"registers\" are\n-\t 16-bit words.  */\n-      for (i = (target_memregs+1)/2; i < 8; i++)\n-\t{\n-\t  fixed_regs[MEM0_REGNO + i] = 1;\n-\t  CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);\n-\t}\n-    }\n-\n-  /* M32CM and M32C preserve more registers across function calls.  */\n-  if (TARGET_A24)\n-    {\n-      call_used_regs[R1_REGNO] = 0;\n-      call_used_regs[R2_REGNO] = 0;\n-      call_used_regs[R3_REGNO] = 0;\n-      call_used_regs[A0_REGNO] = 0;\n-      call_used_regs[A1_REGNO] = 0;\n-    }\n-}\n-\n-/* How Values Fit in Registers */\n-\n-/* Implements TARGET_HARD_REGNO_NREGS.  This is complicated by the fact that\n-   different registers are different sizes from each other, *and* may\n-   be different sizes in different chip families.  */\n-static unsigned int\n-m32c_hard_regno_nregs_1 (unsigned int regno, machine_mode mode)\n-{\n-  if (regno == FLG_REGNO && mode == CCmode)\n-    return 1;\n-  if (regno >= FIRST_PSEUDO_REGISTER)\n-    return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);\n-\n-  if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)\n-    return (GET_MODE_SIZE (mode) + 1) / 2;\n-\n-  if (GET_MODE_SIZE (mode) <= 1)\n-    return nregs_table[regno].qi_regs;\n-  if (GET_MODE_SIZE (mode) <= 2)\n-    return nregs_table[regno].hi_regs;\n-  if (regno == A0_REGNO && mode == SImode && TARGET_A16)\n-    return 2;\n-  if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)\n-    return nregs_table[regno].pi_regs;\n-  if (GET_MODE_SIZE (mode) <= 4)\n-    return nregs_table[regno].si_regs;\n-  if (GET_MODE_SIZE (mode) <= 8)\n-    return nregs_table[regno].di_regs;\n-  return 0;\n-}\n-\n-static unsigned int\n-m32c_hard_regno_nregs (unsigned int regno, machine_mode mode)\n-{\n-  unsigned int rv = m32c_hard_regno_nregs_1 (regno, mode);\n-  return rv ? rv : 1;\n-}\n-\n-/* Implement TARGET_HARD_REGNO_MODE_OK.  The above function does the work\n-   already; just test its return value.  */\n-static bool\n-m32c_hard_regno_mode_ok (unsigned int regno, machine_mode mode)\n-{\n-  return m32c_hard_regno_nregs_1 (regno, mode) != 0;\n-}\n-\n-/* Implement TARGET_MODES_TIEABLE_P.  In general, modes aren't tieable since\n-   registers are all different sizes.  However, since most modes are\n-   bigger than our registers anyway, it's easier to implement this\n-   function that way, leaving QImode as the only unique case.  */\n-static bool\n-m32c_modes_tieable_p (machine_mode m1, machine_mode m2)\n-{\n-  if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))\n-    return 1;\n-\n-#if 0\n-  if (m1 == QImode || m2 == QImode)\n-    return 0;\n-#endif\n-\n-  return 1;\n-}\n-\n-/* Register Classes */\n-\n-/* Implements REGNO_REG_CLASS.  */\n-enum reg_class\n-m32c_regno_reg_class (int regno)\n-{\n-  switch (regno)\n-    {\n-    case R0_REGNO:\n-      return R0_REGS;\n-    case R1_REGNO:\n-      return R1_REGS;\n-    case R2_REGNO:\n-      return R2_REGS;\n-    case R3_REGNO:\n-      return R3_REGS;\n-    case A0_REGNO:\n-      return A0_REGS;\n-    case A1_REGNO:\n-      return A1_REGS;\n-    case SB_REGNO:\n-      return SB_REGS;\n-    case FB_REGNO:\n-      return FB_REGS;\n-    case SP_REGNO:\n-      return SP_REGS;\n-    case FLG_REGNO:\n-      return FLG_REGS;\n-    default:\n-      if (IS_MEM_REGNO (regno))\n-\treturn MEM_REGS;\n-      return ALL_REGS;\n-    }\n-}\n-\n-/* Implements REGNO_OK_FOR_BASE_P.  */\n-int\n-m32c_regno_ok_for_base_p (int regno)\n-{\n-  if (regno == A0_REGNO\n-      || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)\n-    return 1;\n-  return 0;\n-}\n-\n-/* Implements TARGET_PREFERRED_RELOAD_CLASS.  In general, prefer general\n-   registers of the appropriate size.  */\n-\n-#undef TARGET_PREFERRED_RELOAD_CLASS\n-#define TARGET_PREFERRED_RELOAD_CLASS m32c_preferred_reload_class\n-\n-static reg_class_t\n-m32c_preferred_reload_class (rtx x, reg_class_t rclass)\n-{\n-  reg_class_t newclass = rclass;\n-\n-#if DEBUG0\n-  fprintf (stderr, \"\\npreferred_reload_class for %s is \",\n-\t   class_names[rclass]);\n-#endif\n-  if (rclass == NO_REGS)\n-    rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;\n-\n-  if (reg_classes_intersect_p (rclass, CR_REGS))\n-    {\n-      switch (GET_MODE (x))\n-\t{\n-\tcase E_QImode:\n-\t  newclass = HL_REGS;\n-\t  break;\n-\tdefault:\n-\t  /*      newclass = HI_REGS; */\n-\t  break;\n-\t}\n-    }\n-\n-  else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)\n-    newclass = SI_REGS;\n-  else if (GET_MODE_SIZE (GET_MODE (x)) > 4\n-\t   && ! reg_class_subset_p (R03_REGS, rclass))\n-    newclass = DI_REGS;\n-\n-  rclass = reduce_class (rclass, newclass, rclass);\n-\n-  if (GET_MODE (x) == QImode)\n-    rclass = reduce_class (rclass, HL_REGS, rclass);\n-\n-#if DEBUG0\n-  fprintf (stderr, \"%s\\n\", class_names[rclass]);\n-  debug_rtx (x);\n-\n-  if (GET_CODE (x) == MEM\n-      && GET_CODE (XEXP (x, 0)) == PLUS\n-      && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)\n-    fprintf (stderr, \"Glorm!\\n\");\n-#endif\n-  return rclass;\n-}\n-\n-/* Implements TARGET_PREFERRED_OUTPUT_RELOAD_CLASS.  */\n-\n-#undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS\n-#define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS m32c_preferred_output_reload_class\n-\n-static reg_class_t\n-m32c_preferred_output_reload_class (rtx x, reg_class_t rclass)\n-{\n-  return m32c_preferred_reload_class (x, rclass);\n-}\n-\n-/* Implements LIMIT_RELOAD_CLASS.  We basically want to avoid using\n-   address registers for reloads since they're needed for address\n-   reloads.  */\n-int\n-m32c_limit_reload_class (machine_mode mode, int rclass)\n-{\n-#if DEBUG0\n-  fprintf (stderr, \"limit_reload_class for %s: %s ->\",\n-\t   mode_name[mode], class_names[rclass]);\n-#endif\n-\n-  if (mode == QImode)\n-    rclass = reduce_class (rclass, HL_REGS, rclass);\n-  else if (mode == HImode)\n-    rclass = reduce_class (rclass, HI_REGS, rclass);\n-  else if (mode == SImode)\n-    rclass = reduce_class (rclass, SI_REGS, rclass);\n-\n-  if (rclass != A_REGS)\n-    rclass = reduce_class (rclass, DI_REGS, rclass);\n-\n-#if DEBUG0\n-  fprintf (stderr, \" %s\\n\", class_names[rclass]);\n-#endif\n-  return rclass;\n-}\n-\n-/* Implements SECONDARY_RELOAD_CLASS.  QImode have to be reloaded in\n-   r0 or r1, as those are the only real QImode registers.  CR regs get\n-   reloaded through appropriately sized general or address\n-   registers.  */\n-int\n-m32c_secondary_reload_class (int rclass, machine_mode mode, rtx x)\n-{\n-  int cc = class_contents[rclass][0];\n-#if DEBUG0\n-  fprintf (stderr, \"\\nsecondary reload class %s %s\\n\",\n-\t   class_names[rclass], mode_name[mode]);\n-  debug_rtx (x);\n-#endif\n-  if (mode == QImode\n-      && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)\n-    return QI_REGS;\n-  if (reg_classes_intersect_p (rclass, CR_REGS)\n-      && GET_CODE (x) == REG\n-      && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)\n-    return (TARGET_A16 || mode == HImode) ? HI_REGS : A_REGS;\n-  return NO_REGS;\n-}\n-\n-/* Implements TARGET_CLASS_LIKELY_SPILLED_P.  A_REGS is needed for address\n-   reloads.  */\n-\n-#undef TARGET_CLASS_LIKELY_SPILLED_P\n-#define TARGET_CLASS_LIKELY_SPILLED_P m32c_class_likely_spilled_p\n-\n-static bool\n-m32c_class_likely_spilled_p (reg_class_t regclass)\n-{\n-  if (regclass == A_REGS)\n-    return true;\n-\n-  return (reg_class_size[(int) regclass] == 1);\n-}\n-\n-/* Implements TARGET_CLASS_MAX_NREGS.  We calculate this according to its\n-   documented meaning, to avoid potential inconsistencies with actual\n-   class definitions.  */\n-\n-#undef TARGET_CLASS_MAX_NREGS\n-#define TARGET_CLASS_MAX_NREGS m32c_class_max_nregs\n-\n-static unsigned char\n-m32c_class_max_nregs (reg_class_t regclass, machine_mode mode)\n-{\n-  int rn;\n-  unsigned char max = 0;\n-\n-  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)\n-    if (TEST_HARD_REG_BIT (reg_class_contents[(int) regclass], rn))\n-      {\n-\tunsigned char n = m32c_hard_regno_nregs (rn, mode);\n-\tif (max < n)\n-\t  max = n;\n-      }\n-  return max;\n-}\n-\n-/* Implements TARGET_CAN_CHANGE_MODE_CLASS.  Only r0 and r1 can change to\n-   QI (r0l, r1l) because the chip doesn't support QI ops on other\n-   registers (well, it does on a0/a1 but if we let gcc do that, reload\n-   suffers).  Otherwise, we allow changes to larger modes.  */\n-static bool\n-m32c_can_change_mode_class (machine_mode from,\n-\t\t\t    machine_mode to, reg_class_t rclass)\n-{\n-  int rn;\n-#if DEBUG0\n-  fprintf (stderr, \"can change from %s to %s in %s\\n\",\n-\t   mode_name[from], mode_name[to], class_names[rclass]);\n-#endif\n-\n-  /* If the larger mode isn't allowed in any of these registers, we\n-     can't allow the change.  */\n-  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)\n-    if (class_contents[rclass][0] & (1 << rn))\n-      if (! m32c_hard_regno_mode_ok (rn, to))\n-\treturn false;\n-\n-  if (to == QImode)\n-    return (class_contents[rclass][0] & 0x1ffa) == 0;\n-\n-  if (class_contents[rclass][0] & 0x0005\t/* r0, r1 */\n-      && GET_MODE_SIZE (from) > 1)\n-    return true;\n-  if (GET_MODE_SIZE (from) > 2)\t/* all other regs */\n-    return true;\n-\n-  return false;\n-}\n-\n-/* Helpers for the rest of the file.  */\n-/* TRUE if the rtx is a REG rtx for the given register.  */\n-#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \\\n-\t\t\t   && REGNO (rtx) == regno)\n-/* TRUE if the rtx is a pseudo - specifically, one we can use as a\n-   base register in address calculations (hence the \"strict\"\n-   argument).  */\n-#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \\\n-\t\t\t       && (REGNO (rtx) == AP_REGNO \\\n-\t\t\t\t   || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))\n-\n-#define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)\n-\n-/* Implements matching for constraints (see next function too).  'S' is\n-   for memory constraints, plus \"Rpa\" for PARALLEL rtx's we use for\n-   call return values.  */\n-bool\n-m32c_matches_constraint_p (rtx value, int constraint)\n-{\n-  encode_pattern (value);\n-\n-  switch (constraint) {\n-  case CONSTRAINT_SF:\n-    return (far_addr_space_p (value)\n-\t    && ((RTX_IS (\"mr\")\n-\t\t && A0_OR_PSEUDO (patternr[1])\n-\t\t && GET_MODE (patternr[1]) == SImode)\n-\t\t|| (RTX_IS (\"m+^Sri\")\n-\t\t    && A0_OR_PSEUDO (patternr[4])\n-\t\t    && GET_MODE (patternr[4]) == HImode)\n-\t\t|| (RTX_IS (\"m+^Srs\")\n-\t\t    && A0_OR_PSEUDO (patternr[4])\n-\t\t    && GET_MODE (patternr[4]) == HImode)\n-\t\t|| (RTX_IS (\"m+^S+ris\")\n-\t\t    && A0_OR_PSEUDO (patternr[5])\n-\t\t    && GET_MODE (patternr[5]) == HImode)\n-\t\t|| RTX_IS (\"ms\")));\n-  case CONSTRAINT_Sd:\n-    {\n-      /* This is the common \"src/dest\" address */\n-      rtx r;\n-      if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))\n-\treturn true;\n-      if (RTX_IS (\"ms\") || RTX_IS (\"m+si\"))\n-\treturn true;\n-      if (RTX_IS (\"m++rii\"))\n-\t{\n-\t  if (REGNO (patternr[3]) == FB_REGNO\n-\t      && INTVAL (patternr[4]) == 0)\n-\t    return true;\n-\t}\n-      if (RTX_IS (\"mr\"))\n-\tr = patternr[1];\n-      else if (RTX_IS (\"m+ri\") || RTX_IS (\"m+rs\") || RTX_IS (\"m+r+si\"))\n-\tr = patternr[2];\n-      else\n-\treturn false;\n-      if (REGNO (r) == SP_REGNO)\n-\treturn false;\n-      return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);\n-    }\n-  case CONSTRAINT_Sa:\n-    {\n-      rtx r;\n-      if (RTX_IS (\"mr\"))\n-\tr = patternr[1];\n-      else if (RTX_IS (\"m+ri\"))\n-\tr = patternr[2];\n-      else\n-\treturn false;\n-      return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));\n-    }\n-  case CONSTRAINT_Si:\n-    return (RTX_IS (\"mi\") || RTX_IS (\"ms\") || RTX_IS (\"m+si\"));\n-  case CONSTRAINT_Ss:\n-    return ((RTX_IS (\"mr\")\n-\t     && (IS_REG (patternr[1], SP_REGNO)))\n-\t    || (RTX_IS (\"m+ri\") && (IS_REG (patternr[2], SP_REGNO))));\n-  case CONSTRAINT_Sf:\n-    return ((RTX_IS (\"mr\")\n-\t     && (IS_REG (patternr[1], FB_REGNO)))\n-\t    || (RTX_IS (\"m+ri\") && (IS_REG (patternr[2], FB_REGNO))));\n-  case CONSTRAINT_Sb:\n-    return ((RTX_IS (\"mr\")\n-\t     && (IS_REG (patternr[1], SB_REGNO)))\n-\t    || (RTX_IS (\"m+ri\") && (IS_REG (patternr[2], SB_REGNO))));\n-  case CONSTRAINT_Sp:\n-    /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */\n-    return (RTX_IS (\"mi\")\n-\t    && !(INTVAL (patternr[1]) & ~0x1fff));\n-  case CONSTRAINT_S1:\n-    return r1h_operand (value, QImode);\n-  case CONSTRAINT_Rpa:\n-    return GET_CODE (value) == PARALLEL;\n-  default:\n-    return false;\n-  }\n-}\n-\n-/* STACK AND CALLING */\n-\n-/* Frame Layout */\n-\n-/* Implements RETURN_ADDR_RTX.  Note that R8C and M16C push 24 bits\n-   (yes, THREE bytes) onto the stack for the return address, but we\n-   don't support pointers bigger than 16 bits on those chips.  This\n-   will likely wreak havoc with exception unwinding.  FIXME.  */\n-rtx\n-m32c_return_addr_rtx (int count)\n-{\n-  machine_mode mode;\n-  int offset;\n-  rtx ra_mem;\n-\n-  if (count)\n-    return NULL_RTX;\n-  /* we want 2[$fb] */\n-\n-  if (TARGET_A24)\n-    {\n-      /* It's four bytes */\n-      mode = PSImode;\n-      offset = 4;\n-    }\n-  else\n-    {\n-      /* FIXME: it's really 3 bytes */\n-      mode = HImode;\n-      offset = 2;\n-    }\n-\n-  ra_mem =\n-    gen_rtx_MEM (mode, plus_constant (Pmode, gen_rtx_REG (Pmode, FP_REGNO),\n-\t\t\t\t      offset));\n-  return copy_to_mode_reg (mode, ra_mem);\n-}\n-\n-/* Implements INCOMING_RETURN_ADDR_RTX.  See comment above.  */\n-rtx\n-m32c_incoming_return_addr_rtx (void)\n-{\n-  /* we want [sp] */\n-  return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));\n-}\n-\n-/* Exception Handling Support */\n-\n-/* Implements EH_RETURN_DATA_REGNO.  Choose registers able to hold\n-   pointers.  */\n-int\n-m32c_eh_return_data_regno (int n)\n-{\n-  switch (n)\n-    {\n-    case 0:\n-      return MEM0_REGNO;\n-    case 1:\n-      return MEM0_REGNO+4;\n-    default:\n-      return INVALID_REGNUM;\n-    }\n-}\n-\n-/* Implements EH_RETURN_STACKADJ_RTX.  Saved and used later in\n-   m32c_emit_eh_epilogue.  */\n-rtx\n-m32c_eh_return_stackadj_rtx (void)\n-{\n-  if (!cfun->machine->eh_stack_adjust)\n-    {\n-      rtx sa;\n-\n-      sa = gen_rtx_REG (Pmode, R0_REGNO);\n-      cfun->machine->eh_stack_adjust = sa;\n-    }\n-  return cfun->machine->eh_stack_adjust;\n-}\n-\n-/* Registers That Address the Stack Frame */\n-\n-/* Implements DWARF_FRAME_REGNUM and DEBUGGER_REGNO.  Note that\n-   the original spec called for dwarf numbers to vary with register\n-   width as well, for example, r0l, r0, and r2r0 would each have\n-   different dwarf numbers.  GCC doesn't support this, and we don't do\n-   it, and gdb seems to like it this way anyway.  */\n-unsigned int\n-m32c_dwarf_frame_regnum (int n)\n-{\n-  switch (n)\n-    {\n-    case R0_REGNO:\n-      return 5;\n-    case R1_REGNO:\n-      return 6;\n-    case R2_REGNO:\n-      return 7;\n-    case R3_REGNO:\n-      return 8;\n-    case A0_REGNO:\n-      return 9;\n-    case A1_REGNO:\n-      return 10;\n-    case FB_REGNO:\n-      return 11;\n-    case SB_REGNO:\n-      return 19;\n-\n-    case SP_REGNO:\n-      return 12;\n-    case PC_REGNO:\n-      return 13;\n-    default:\n-      return DWARF_FRAME_REGISTERS + 1;\n-    }\n-}\n-\n-/* The frame looks like this:\n-\n-   ap -> +------------------------------\n-         | Return address (3 or 4 bytes)\n-\t | Saved FB (2 or 4 bytes)\n-   fb -> +------------------------------\n-\t | local vars\n-         | register saves fb\n-\t |        through r0 as needed\n-   sp -> +------------------------------\n-*/\n-\n-/* We use this to wrap all emitted insns in the prologue.  */\n-static rtx\n-F (rtx x)\n-{\n-  RTX_FRAME_RELATED_P (x) = 1;\n-  return x;\n-}\n-\n-/* This maps register numbers to the PUSHM/POPM bitfield, and tells us\n-   how much the stack pointer moves for each, for each cpu family.  */\n-static struct\n-{\n-  int reg1;\n-  int bit;\n-  int a16_bytes;\n-  int a24_bytes;\n-} pushm_info[] =\n-{\n-  /* These are in reverse push (nearest-to-sp) order.  */\n-  { R0_REGNO, 0x80, 2, 2 },\n-  { R1_REGNO, 0x40, 2, 2 },\n-  { R2_REGNO, 0x20, 2, 2 },\n-  { R3_REGNO, 0x10, 2, 2 },\n-  { A0_REGNO, 0x08, 2, 4 },\n-  { A1_REGNO, 0x04, 2, 4 },\n-  { SB_REGNO, 0x02, 2, 4 },\n-  { FB_REGNO, 0x01, 2, 4 }\n-};\n-\n-#define PUSHM_N (ARRAY_SIZE (pushm_info))\n-\n-/* Returns TRUE if we need to save/restore the given register.  We\n-   save everything for exception handlers, so that any register can be\n-   unwound.  For interrupt handlers, we save everything if the handler\n-   calls something else (because we don't know what *that* function\n-   might do), but try to be a bit smarter if the handler is a leaf\n-   function.  We always save $a0, though, because we use that in the\n-   epilogue to copy $fb to $sp.  */\n-static int\n-need_to_save (int regno)\n-{\n-  if (fixed_regs[regno])\n-    return 0;\n-  if (crtl->calls_eh_return)\n-    return 1;\n-  if (regno == FP_REGNO)\n-    return 0;\n-  if (cfun->machine->is_interrupt\n-      && (!cfun->machine->is_leaf\n-\t  || (regno == A0_REGNO\n-\t      && m32c_function_needs_enter ())\n-\t  ))\n-    return 1;\n-  if (df_regs_ever_live_p (regno)\n-      && (!call_used_or_fixed_reg_p (regno) || cfun->machine->is_interrupt))\n-    return 1;\n-  return 0;\n-}\n-\n-/* This function contains all the intelligence about saving and\n-   restoring registers.  It always figures out the register save set.\n-   When called with PP_justcount, it merely returns the size of the\n-   save set (for eliminating the frame pointer, for example).  When\n-   called with PP_pushm or PP_popm, it emits the appropriate\n-   instructions for saving (pushm) or restoring (popm) the\n-   registers.  */\n-static int\n-m32c_pushm_popm (Push_Pop_Type ppt)\n-{\n-  int reg_mask = 0;\n-  int byte_count = 0, bytes;\n-  int i;\n-  rtx dwarf_set[PUSHM_N];\n-  int n_dwarfs = 0;\n-  int nosave_mask = 0;\n-\n-  if (crtl->return_rtx\n-      && GET_CODE (crtl->return_rtx) == PARALLEL\n-      && !(crtl->calls_eh_return || cfun->machine->is_interrupt))\n-    {\n-      rtx exp = XVECEXP (crtl->return_rtx, 0, 0);\n-      rtx rv = XEXP (exp, 0);\n-      int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));\n-\n-      if (rv_bytes > 2)\n-\tnosave_mask |= 0x20;\t/* PSI, SI */\n-      else\n-\tnosave_mask |= 0xf0;\t/* DF */\n-      if (rv_bytes > 4)\n-\tnosave_mask |= 0x50;\t/* DI */\n-    }\n-\n-  for (i = 0; i < (int) PUSHM_N; i++)\n-    {\n-      /* Skip if neither register needs saving.  */\n-      if (!need_to_save (pushm_info[i].reg1))\n-\tcontinue;\n-\n-      if (pushm_info[i].bit & nosave_mask)\n-\tcontinue;\n-\n-      reg_mask |= pushm_info[i].bit;\n-      bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;\n-\n-      if (ppt == PP_pushm)\n-\t{\n-\t  machine_mode mode = (bytes == 2) ? HImode : SImode;\n-\t  rtx addr;\n-\n-\t  /* Always use stack_pointer_rtx instead of calling\n-\t     rtx_gen_REG ourselves.  Code elsewhere in GCC assumes\n-\t     that there is a single rtx representing the stack pointer,\n-\t     namely stack_pointer_rtx, and uses == to recognize it.  */\n-\t  addr = stack_pointer_rtx;\n-\n-\t  if (byte_count != 0)\n-\t    addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));\n-\n-\t  dwarf_set[n_dwarfs++] =\n-\t    gen_rtx_SET (gen_rtx_MEM (mode, addr),\n-\t\t\t gen_rtx_REG (mode, pushm_info[i].reg1));\n-\t  F (dwarf_set[n_dwarfs - 1]);\n-\n-\t}\n-      byte_count += bytes;\n-    }\n-\n-  if (cfun->machine->is_interrupt)\n-    {\n-      cfun->machine->intr_pushm = reg_mask & 0xfe;\n-      reg_mask = 0;\n-      byte_count = 0;\n-    }\n-\n-  if (cfun->machine->is_interrupt)\n-    for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)\n-      if (need_to_save (i))\n-\t{\n-\t  byte_count += 2;\n-\t  cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;\n-\t}\n-\n-  if (ppt == PP_pushm && byte_count)\n-    {\n-      rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));\n-      rtx pushm;\n-\n-      if (reg_mask)\n-\t{\n-\t  XVECEXP (note, 0, 0)\n-\t    = gen_rtx_SET (stack_pointer_rtx,\n-\t\t\t   gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),\n-\t\t\t\t\t stack_pointer_rtx,\n-\t\t\t\t\t GEN_INT (-byte_count)));\n-\t  F (XVECEXP (note, 0, 0));\n-\n-\t  for (i = 0; i < n_dwarfs; i++)\n-\t    XVECEXP (note, 0, i + 1) = dwarf_set[i];\n-\n-\t  pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));\n-\n-\t  add_reg_note (pushm, REG_FRAME_RELATED_EXPR, note);\n-\t}\n-\n-      if (cfun->machine->is_interrupt)\n-\tfor (i = MEM0_REGNO; i <= MEM7_REGNO; i++)\n-\t  if (cfun->machine->intr_pushmem[i - MEM0_REGNO])\n-\t    {\n-\t      if (TARGET_A16)\n-\t\tpushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));\n-\t      else\n-\t\tpushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));\n-\t      F (pushm);\n-\t    }\n-    }\n-  if (ppt == PP_popm && byte_count)\n-    {\n-      if (cfun->machine->is_interrupt)\n-\tfor (i = MEM7_REGNO; i >= MEM0_REGNO; i--)\n-\t  if (cfun->machine->intr_pushmem[i - MEM0_REGNO])\n-\t    {\n-\t      if (TARGET_A16)\n-\t\temit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));\n-\t      else\n-\t\temit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));\n-\t    }\n-      if (reg_mask)\n-\temit_insn (gen_popm (GEN_INT (reg_mask)));\n-    }\n-\n-  return byte_count;\n-}\n-\n-/* Implements INITIAL_ELIMINATION_OFFSET.  See the comment above that\n-   diagrams our call frame.  */\n-int\n-m32c_initial_elimination_offset (int from, int to)\n-{\n-  int ofs = 0;\n-\n-  if (from == AP_REGNO)\n-    {\n-      if (TARGET_A16)\n-\tofs += 5;\n-      else\n-\tofs += 8;\n-    }\n-\n-  if (to == SP_REGNO)\n-    {\n-      ofs += m32c_pushm_popm (PP_justcount);\n-      ofs += get_frame_size ();\n-    }\n-\n-  /* Account for push rounding.  */\n-  if (TARGET_A24)\n-    ofs = (ofs + 1) & ~1;\n-#if DEBUG0\n-  fprintf (stderr, \"initial_elimination_offset from=%d to=%d, ofs=%d\\n\", from,\n-\t   to, ofs);\n-#endif\n-  return ofs;\n-}\n-\n-/* Passing Function Arguments on the Stack */\n-\n-/* Implements PUSH_ROUNDING.  The R8C and M16C have byte stacks, the\n-   M32C has word stacks.  */\n-poly_int64\n-m32c_push_rounding (poly_int64 n)\n-{\n-  if (TARGET_R8C || TARGET_M16C)\n-    return n;\n-  return (n + 1) & ~1;\n-}\n-\n-#undef TARGET_PUSH_ARGUMENT\n-#define TARGET_PUSH_ARGUMENT hook_bool_uint_true\n-\n-/* Passing Arguments in Registers */\n-\n-/* Implements TARGET_FUNCTION_ARG.  Arguments are passed partly in\n-   registers, partly on stack.  If our function returns a struct, a\n-   pointer to a buffer for it is at the top of the stack (last thing\n-   pushed).  The first few real arguments may be in registers as\n-   follows:\n-\n-   R8C/M16C:\targ1 in r1 if it's QI or HI (else it's pushed on stack)\n-\t\targ2 in r2 if it's HI (else pushed on stack)\n-\t\trest on stack\n-   M32C:        arg1 in r0 if it's QI or HI (else it's pushed on stack)\n-\t\trest on stack\n-\n-   Structs are not passed in registers, even if they fit.  Only\n-   integer and pointer types are passed in registers.\n-\n-   Note that when arg1 doesn't fit in r1, arg2 may still be passed in\n-   r2 if it fits.  */\n-#undef TARGET_FUNCTION_ARG\n-#define TARGET_FUNCTION_ARG m32c_function_arg\n-static rtx\n-m32c_function_arg (cumulative_args_t ca_v, const function_arg_info &arg)\n-{\n-  CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);\n-\n-  /* Can return a reg, parallel, or 0 for stack */\n-  rtx rv = NULL_RTX;\n-#if DEBUG0\n-  fprintf (stderr, \"func_arg %d (%s, %d)\\n\",\n-\t   ca->parm_num, mode_name[arg.mode], arg.named);\n-  debug_tree (arg.type);\n-#endif\n-\n-  if (arg.end_marker_p ())\n-    return GEN_INT (0);\n-\n-  if (ca->force_mem || !arg.named)\n-    {\n-#if DEBUG0\n-      fprintf (stderr, \"func arg: force %d named %d, mem\\n\", ca->force_mem,\n-\t       arg.named);\n-#endif\n-      return NULL_RTX;\n-    }\n-\n-  if (arg.type && INTEGRAL_TYPE_P (arg.type) && POINTER_TYPE_P (arg.type))\n-    return NULL_RTX;\n-\n-  if (arg.aggregate_type_p ())\n-    return NULL_RTX;\n-\n-  switch (ca->parm_num)\n-    {\n-    case 1:\n-      if (GET_MODE_SIZE (arg.mode) == 1 || GET_MODE_SIZE (arg.mode) == 2)\n-\trv = gen_rtx_REG (arg.mode, TARGET_A16 ? R1_REGNO : R0_REGNO);\n-      break;\n-\n-    case 2:\n-      if (TARGET_A16 && GET_MODE_SIZE (arg.mode) == 2)\n-\trv = gen_rtx_REG (arg.mode, R2_REGNO);\n-      break;\n-    }\n-\n-#if DEBUG0\n-  debug_rtx (rv);\n-#endif\n-  return rv;\n-}\n-\n-#undef TARGET_PASS_BY_REFERENCE\n-#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference\n-static bool\n-m32c_pass_by_reference (cumulative_args_t, const function_arg_info &)\n-{\n-  return 0;\n-}\n-\n-/* Implements INIT_CUMULATIVE_ARGS.  */\n-void\n-m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,\n-\t\t\t   tree fntype,\n-\t\t\t   rtx libname ATTRIBUTE_UNUSED,\n-\t\t\t   tree fndecl,\n-\t\t\t   int n_named_args ATTRIBUTE_UNUSED)\n-{\n-  if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))\n-    ca->force_mem = 1;\n-  else\n-    ca->force_mem = 0;\n-  ca->parm_num = 1;\n-}\n-\n-/* Implements TARGET_FUNCTION_ARG_ADVANCE.  force_mem is set for\n-   functions returning structures, so we always reset that.  Otherwise,\n-   we only need to know the sequence number of the argument to know what\n-   to do with it.  */\n-#undef TARGET_FUNCTION_ARG_ADVANCE\n-#define TARGET_FUNCTION_ARG_ADVANCE m32c_function_arg_advance\n-static void\n-m32c_function_arg_advance (cumulative_args_t ca_v,\n-\t\t\t   const function_arg_info &)\n-{\n-  CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);\n-\n-  if (ca->force_mem)\n-    ca->force_mem = 0;\n-  else\n-    ca->parm_num++;\n-}\n-\n-/* Implements TARGET_FUNCTION_ARG_BOUNDARY.  */\n-#undef TARGET_FUNCTION_ARG_BOUNDARY\n-#define TARGET_FUNCTION_ARG_BOUNDARY m32c_function_arg_boundary\n-static unsigned int\n-m32c_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED,\n-\t\t\t    const_tree type ATTRIBUTE_UNUSED)\n-{\n-  return (TARGET_A16 ? 8 : 16);\n-}\n-\n-/* Implements FUNCTION_ARG_REGNO_P.  */\n-int\n-m32c_function_arg_regno_p (int r)\n-{\n-  if (TARGET_A24)\n-    return (r == R0_REGNO);\n-  return (r == R1_REGNO || r == R2_REGNO);\n-}\n-\n-/* HImode and PSImode are the two \"native\" modes as far as GCC is\n-   concerned, but the chips also support a 32-bit mode which is used\n-   for some opcodes in R8C/M16C and for reset vectors and such.  */\n-#undef TARGET_VALID_POINTER_MODE\n-#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode\n-static bool\n-m32c_valid_pointer_mode (scalar_int_mode mode)\n-{\n-  if (mode == HImode\n-      || mode == PSImode\n-      || mode == SImode\n-      )\n-    return 1;\n-  return 0;\n-}\n-\n-/* How Scalar Function Values Are Returned */\n-\n-/* Implements TARGET_LIBCALL_VALUE.  Most values are returned in $r0, or some\n-   combination of registers starting there (r2r0 for longs, r3r1r2r0\n-   for long long, r3r2r1r0 for doubles), except that that ABI\n-   currently doesn't work because it ends up using all available\n-   general registers and gcc often can't compile it.  So, instead, we\n-   return anything bigger than 16 bits in \"mem0\" (effectively, a\n-   memory location).  */\n-\n-#undef TARGET_LIBCALL_VALUE\n-#define TARGET_LIBCALL_VALUE m32c_libcall_value\n-\n-static rtx\n-m32c_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)\n-{\n-  /* return reg or parallel */\n-#if 0\n-  /* FIXME: GCC has difficulty returning large values in registers,\n-     because that ties up most of the general registers and gives the\n-     register allocator little to work with.  Until we can resolve\n-     this, large values are returned in memory.  */\n-  if (mode == DFmode)\n-    {\n-      rtx rv;\n-\n-      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));\n-      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,\n-\t\t\t\t\t      gen_rtx_REG (HImode,\n-\t\t\t\t\t\t\t   R0_REGNO),\n-\t\t\t\t\t      GEN_INT (0));\n-      XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,\n-\t\t\t\t\t      gen_rtx_REG (HImode,\n-\t\t\t\t\t\t\t   R1_REGNO),\n-\t\t\t\t\t      GEN_INT (2));\n-      XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,\n-\t\t\t\t\t      gen_rtx_REG (HImode,\n-\t\t\t\t\t\t\t   R2_REGNO),\n-\t\t\t\t\t      GEN_INT (4));\n-      XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,\n-\t\t\t\t\t      gen_rtx_REG (HImode,\n-\t\t\t\t\t\t\t   R3_REGNO),\n-\t\t\t\t\t      GEN_INT (6));\n-      return rv;\n-    }\n-\n-  if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)\n-    {\n-      rtx rv;\n-\n-      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));\n-      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,\n-\t\t\t\t\t      gen_rtx_REG (mode,\n-\t\t\t\t\t\t\t   R0_REGNO),\n-\t\t\t\t\t      GEN_INT (0));\n-      return rv;\n-    }\n-#endif\n-\n-  if (GET_MODE_SIZE (mode) > 2)\n-    return gen_rtx_REG (mode, MEM0_REGNO);\n-  return gen_rtx_REG (mode, R0_REGNO);\n-}\n-\n-/* Implements TARGET_FUNCTION_VALUE.  Functions and libcalls have the same\n-   conventions.  */\n-\n-#undef TARGET_FUNCTION_VALUE\n-#define TARGET_FUNCTION_VALUE m32c_function_value\n-\n-static rtx\n-m32c_function_value (const_tree valtype,\n-\t\t     const_tree fn_decl_or_type ATTRIBUTE_UNUSED,\n-\t\t     bool outgoing ATTRIBUTE_UNUSED)\n-{\n-  /* return reg or parallel */\n-  const machine_mode mode = TYPE_MODE (valtype);\n-  return m32c_libcall_value (mode, NULL_RTX);\n-}\n-\n-/* Implements TARGET_FUNCTION_VALUE_REGNO_P.  */\n-\n-#undef TARGET_FUNCTION_VALUE_REGNO_P\n-#define TARGET_FUNCTION_VALUE_REGNO_P m32c_function_value_regno_p\n-\n-static bool\n-m32c_function_value_regno_p (const unsigned int regno)\n-{\n-  return (regno == R0_REGNO || regno == MEM0_REGNO);\n-}\n-\n-/* How Large Values Are Returned */\n-\n-/* We return structures by pushing the address on the stack, even if\n-   we use registers for the first few \"real\" arguments.  */\n-#undef TARGET_STRUCT_VALUE_RTX\n-#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx\n-static rtx\n-m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,\n-\t\t       int incoming ATTRIBUTE_UNUSED)\n-{\n-  return 0;\n-}\n-\n-/* Function Entry and Exit */\n-\n-/* Implements EPILOGUE_USES.  Interrupts restore all registers.  */\n-int\n-m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)\n-{\n-  if (cfun->machine->is_interrupt)\n-    return 1;\n-  return 0;\n-}\n-\n-/* Implementing the Varargs Macros */\n-\n-#undef TARGET_STRICT_ARGUMENT_NAMING\n-#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming\n-static bool\n-m32c_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)\n-{\n-  return 1;\n-}\n-\n-/* Trampolines for Nested Functions */\n-\n-/*\n-   m16c:\n-   1 0000 75C43412              mov.w   #0x1234,a0\n-   2 0004 FC000000              jmp.a   label\n-\n-   m32c:\n-   1 0000 BC563412              mov.l:s #0x123456,a0\n-   2 0004 CC000000              jmp.a   label\n-*/\n-\n-/* Implements TRAMPOLINE_SIZE.  */\n-int\n-m32c_trampoline_size (void)\n-{\n-  /* Allocate extra space so we can avoid the messy shifts when we\n-     initialize the trampoline; we just write past the end of the\n-     opcode.  */\n-  return TARGET_A16 ? 8 : 10;\n-}\n-\n-/* Implements TRAMPOLINE_ALIGNMENT.  */\n-int\n-m32c_trampoline_alignment (void)\n-{\n-  return 2;\n-}\n-\n-/* Implements TARGET_TRAMPOLINE_INIT.  */\n-\n-#undef TARGET_TRAMPOLINE_INIT\n-#define TARGET_TRAMPOLINE_INIT m32c_trampoline_init\n-static void\n-m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)\n-{\n-  rtx function = XEXP (DECL_RTL (fndecl), 0);\n-\n-#define A0(m,i) adjust_address (m_tramp, m, i)\n-  if (TARGET_A16)\n-    {\n-      /* Note: we subtract a \"word\" because the moves want signed\n-\t constants, not unsigned constants.  */\n-      emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));\n-      emit_move_insn (A0 (HImode, 2), chainval);\n-      emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));\n-      /* We use 16-bit addresses here, but store the zero to turn it\n-\t into a 24-bit offset.  */\n-      emit_move_insn (A0 (HImode, 5), function);\n-      emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));\n-    }\n-  else\n-    {\n-      /* Note that the PSI moves actually write 4 bytes.  Make sure we\n-\t write stuff out in the right order, and leave room for the\n-\t extra byte at the end.  */\n-      emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));\n-      emit_move_insn (A0 (PSImode, 1), chainval);\n-      emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));\n-      emit_move_insn (A0 (PSImode, 5), function);\n-    }\n-#undef A0\n-}\n-\n-#undef TARGET_LRA_P\n-#define TARGET_LRA_P hook_bool_void_false\n-\n-/* Addressing Modes */\n-\n-/* The r8c/m32c family supports a wide range of non-orthogonal\n-   addressing modes, including the ability to double-indirect on *some*\n-   of them.  Not all insns support all modes, either, but we rely on\n-   predicates and constraints to deal with that.  */\n-#undef TARGET_LEGITIMATE_ADDRESS_P\n-#define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p\n-bool\n-m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict, code_helper)\n-{\n-  int mode_adjust;\n-  if (CONSTANT_P (x))\n-    return 1;\n-\n-  if (TARGET_A16 && GET_MODE (x) != HImode && GET_MODE (x) != SImode)\n-    return 0;\n-  if (TARGET_A24 && GET_MODE (x) != PSImode)\n-    return 0;\n-\n-  /* Wide references to memory will be split after reload, so we must\n-     ensure that all parts of such splits remain legitimate\n-     addresses.  */\n-  mode_adjust = GET_MODE_SIZE (mode) - 1;\n-\n-  /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */\n-  if (GET_CODE (x) == PRE_DEC\n-      || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)\n-    {\n-      return (GET_CODE (XEXP (x, 0)) == REG\n-\t      && REGNO (XEXP (x, 0)) == SP_REGNO);\n-    }\n-\n-#if 0\n-  /* This is the double indirection detection, but it currently\n-     doesn't work as cleanly as this code implies, so until we've had\n-     a chance to debug it, leave it disabled.  */\n-  if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)\n-    {\n-#if DEBUG_DOUBLE\n-      fprintf (stderr, \"double indirect\\n\");\n-#endif\n-      x = XEXP (x, 0);\n-    }\n-#endif\n-\n-  encode_pattern (x);\n-  if (RTX_IS (\"r\"))\n-    {\n-      /* Most indexable registers can be used without displacements,\n-\t although some of them will be emitted with an explicit zero\n-\t to please the assembler.  */\n-      switch (REGNO (patternr[0]))\n-\t{\n-\tcase A1_REGNO:\n-\tcase SB_REGNO:\n-\tcase FB_REGNO:\n-\tcase SP_REGNO:\n-\t  if (TARGET_A16 && GET_MODE (x) == SImode)\n-\t    return 0;\n-\t  /* FALLTHRU */\n-\tcase A0_REGNO:\n-\t  return 1;\n-\n-\tdefault:\n-\t  if (IS_PSEUDO (patternr[0], strict))\n-\t    return 1;\n-\t  return 0;\n-\t}\n-    }\n-\n-  if (TARGET_A16 && GET_MODE (x) == SImode)\n-    return 0;\n-\n-  if (RTX_IS (\"+ri\"))\n-    {\n-      /* This is more interesting, because different base registers\n-\t allow for different displacements - both range and signedness\n-\t - and it differs from chip series to chip series too.  */\n-      int rn = REGNO (patternr[1]);\n-      HOST_WIDE_INT offs = INTVAL (patternr[2]);\n-      switch (rn)\n-\t{\n-\tcase A0_REGNO:\n-\tcase A1_REGNO:\n-\tcase SB_REGNO:\n-\t  /* The syntax only allows positive offsets, but when the\n-\t     offsets span the entire memory range, we can simulate\n-\t     negative offsets by wrapping.  */\n-\t  if (TARGET_A16)\n-\t    return (offs >= -65536 && offs <= 65535 - mode_adjust);\n-\t  if (rn == SB_REGNO)\n-\t    return (offs >= 0 && offs <= 65535 - mode_adjust);\n-\t  /* A0 or A1 */\n-\t  return (offs >= -16777216 && offs <= 16777215);\n-\n-\tcase FB_REGNO:\n-\t  if (TARGET_A16)\n-\t    return (offs >= -128 && offs <= 127 - mode_adjust);\n-\t  return (offs >= -65536 && offs <= 65535 - mode_adjust);\n-\n-\tcase SP_REGNO:\n-\t  return (offs >= -128 && offs <= 127 - mode_adjust);\n-\n-\tdefault:\n-\t  if (IS_PSEUDO (patternr[1], strict))\n-\t    return 1;\n-\t  return 0;\n-\t}\n-    }\n-  if (RTX_IS (\"+rs\") || RTX_IS (\"+r+si\"))\n-    {\n-      rtx reg = patternr[1];\n-\n-      /* We don't know where the symbol is, so only allow base\n-\t registers which support displacements spanning the whole\n-\t address range.  */\n-      switch (REGNO (reg))\n-\t{\n-\tcase A0_REGNO:\n-\tcase A1_REGNO:\n-\t  /* $sb needs a secondary reload, but since it's involved in\n-\t     memory address reloads too, we don't deal with it very\n-\t     well.  */\n-\t  /*    case SB_REGNO: */\n-\t  return 1;\n-\tdefault:\n-\t  if (GET_CODE (reg) == SUBREG)\n-\t    return 0;\n-\t  if (IS_PSEUDO (reg, strict))\n-\t    return 1;\n-\t  return 0;\n-\t}\n-    }\n-  return 0;\n-}\n-\n-/* Implements REG_OK_FOR_BASE_P.  */\n-int\n-m32c_reg_ok_for_base_p (rtx x, int strict)\n-{\n-  if (GET_CODE (x) != REG)\n-    return 0;\n-  switch (REGNO (x))\n-    {\n-    case A0_REGNO:\n-    case A1_REGNO:\n-    case SB_REGNO:\n-    case FB_REGNO:\n-    case SP_REGNO:\n-      return 1;\n-    default:\n-      if (IS_PSEUDO (x, strict))\n-\treturn 1;\n-      return 0;\n-    }\n-}\n-\n-/* We have three choices for choosing fb->aN offsets.  If we choose -128,\n-   we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,\n-   like this:\n-       EB 4B FF    mova    -128[$fb],$a0\n-       D8 0C FF FF mov.w:Q #0,-1[$a0]\n-\n-   Alternately, we subtract the frame size, and hopefully use 8-bit aN\n-   displacements:\n-       7B F4       stc $fb,$a0\n-       77 54 00 01 sub #256,$a0\n-       D8 08 01    mov.w:Q #0,1[$a0]\n-\n-   If we don't offset (i.e. offset by zero), we end up with:\n-       7B F4       stc $fb,$a0\n-       D8 0C 00 FF mov.w:Q #0,-256[$a0]\n-\n-   We have to subtract *something* so that we have a PLUS rtx to mark\n-   that we've done this reload.  The -128 offset will never result in\n-   an 8-bit aN offset, and the payoff for the second case is five\n-   loads *if* those loads are within 256 bytes of the other end of the\n-   frame, so the third case seems best.  Note that we subtract the\n-   zero, but detect that in the addhi3 pattern.  */\n-\n-#define BIG_FB_ADJ 0\n-\n-/* Implements LEGITIMIZE_ADDRESS.  The only address we really have to\n-   worry about is frame base offsets, as $fb has a limited\n-   displacement range.  We deal with this by attempting to reload $fb\n-   itself into an address register; that seems to result in the best\n-   code.  */\n-#undef TARGET_LEGITIMIZE_ADDRESS\n-#define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address\n-static rtx\n-m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,\n-\t\t\t machine_mode mode)\n-{\n-#if DEBUG0\n-  fprintf (stderr, \"m32c_legitimize_address for mode %s\\n\", mode_name[mode]);\n-  debug_rtx (x);\n-  fprintf (stderr, \"\\n\");\n-#endif\n-\n-  if (GET_CODE (x) == PLUS\n-      && GET_CODE (XEXP (x, 0)) == REG\n-      && REGNO (XEXP (x, 0)) == FB_REGNO\n-      && GET_CODE (XEXP (x, 1)) == CONST_INT\n-      && (INTVAL (XEXP (x, 1)) < -128\n-\t  || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))\n-    {\n-      /* reload FB to A_REGS */\n-      rtx temp = gen_reg_rtx (Pmode);\n-      x = copy_rtx (x);\n-      emit_insn (gen_rtx_SET (temp, XEXP (x, 0)));\n-      XEXP (x, 0) = temp;\n-    }\n-\n-  return x;\n-}\n-\n-/* Implements LEGITIMIZE_RELOAD_ADDRESS.  See comment above.  */\n-int\n-m32c_legitimize_reload_address (rtx * x,\n-\t\t\t\tmachine_mode mode,\n-\t\t\t\tint opnum,\n-\t\t\t\tint type, int ind_levels ATTRIBUTE_UNUSED)\n-{\n-#if DEBUG0\n-  fprintf (stderr, \"\\nm32c_legitimize_reload_address for mode %s\\n\",\n-\t   mode_name[mode]);\n-  debug_rtx (*x);\n-#endif\n-\n-  /* At one point, this function tried to get $fb copied to an address\n-     register, which in theory would maximize sharing, but gcc was\n-     *also* still trying to reload the whole address, and we'd run out\n-     of address registers.  So we let gcc do the naive (but safe)\n-     reload instead, when the above function doesn't handle it for\n-     us.\n-\n-     The code below is a second attempt at the above.  */\n-\n-  if (GET_CODE (*x) == PLUS\n-      && GET_CODE (XEXP (*x, 0)) == REG\n-      && REGNO (XEXP (*x, 0)) == FB_REGNO\n-      && GET_CODE (XEXP (*x, 1)) == CONST_INT\n-      && (INTVAL (XEXP (*x, 1)) < -128\n-\t  || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))\n-    {\n-      rtx sum;\n-      int offset = INTVAL (XEXP (*x, 1));\n-      int adjustment = -BIG_FB_ADJ;\n-\n-      sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),\n-\t\t\t  GEN_INT (adjustment));\n-      *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));\n-      if (type == RELOAD_OTHER)\n-\ttype = RELOAD_FOR_OTHER_ADDRESS;\n-      push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,\n-\t\t   A_REGS, Pmode, VOIDmode, 0, 0, opnum,\n-\t\t   (enum reload_type) type);\n-      return 1;\n-    }\n-\n-  if (GET_CODE (*x) == PLUS\n-      && GET_CODE (XEXP (*x, 0)) == PLUS\n-      && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG\n-      && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO\n-      && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT\n-      && GET_CODE (XEXP (*x, 1)) == CONST_INT\n-      )\n-    {\n-      if (type == RELOAD_OTHER)\n-\ttype = RELOAD_FOR_OTHER_ADDRESS;\n-      push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,\n-\t\t   A_REGS, Pmode, VOIDmode, 0, 0, opnum,\n-\t\t   (enum reload_type) type);\n-      return 1;\n-    }\n-\n-  if (TARGET_A24 && GET_MODE (*x) == PSImode)\n-    {\n-      push_reload (*x, NULL_RTX, x, NULL,\n-\t\t   A_REGS, PSImode, VOIDmode, 0, 0, opnum,\n-\t\t   (enum reload_type) type);\n-      return 1;\n-    }\n-\n-  return 0;\n-}\n-\n-/* Return the appropriate mode for a named address pointer.  */\n-#undef TARGET_ADDR_SPACE_POINTER_MODE\n-#define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode\n-static scalar_int_mode\n-m32c_addr_space_pointer_mode (addr_space_t addrspace)\n-{\n-  switch (addrspace)\n-    {\n-    case ADDR_SPACE_GENERIC:\n-      return TARGET_A24 ? PSImode : HImode;\n-    case ADDR_SPACE_FAR:\n-      return SImode;\n-    default:\n-      gcc_unreachable ();\n-    }\n-}\n-\n-/* Return the appropriate mode for a named address address.  */\n-#undef TARGET_ADDR_SPACE_ADDRESS_MODE\n-#define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode\n-static scalar_int_mode\n-m32c_addr_space_address_mode (addr_space_t addrspace)\n-{\n-  switch (addrspace)\n-    {\n-    case ADDR_SPACE_GENERIC:\n-      return TARGET_A24 ? PSImode : HImode;\n-    case ADDR_SPACE_FAR:\n-      return SImode;\n-    default:\n-      gcc_unreachable ();\n-    }\n-}\n-\n-/* Like m32c_legitimate_address_p, except with named addresses.  */\n-#undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P\n-#define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \\\n-  m32c_addr_space_legitimate_address_p\n-static bool\n-m32c_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,\n-\t\t\t\t      addr_space_t as, code_helper ch)\n-{\n-  if (as == ADDR_SPACE_FAR)\n-    {\n-      if (TARGET_A24)\n-\treturn 0;\n-      encode_pattern (x);\n-      if (RTX_IS (\"r\"))\n-\t{\n-\t  if (GET_MODE (x) != SImode)\n-\t    return 0;\n-\t  switch (REGNO (patternr[0]))\n-\t    {\n-\t    case A0_REGNO:\n-\t      return 1;\n-\n-\t    default:\n-\t      if (IS_PSEUDO (patternr[0], strict))\n-\t\treturn 1;\n-\t      return 0;\n-\t    }\n-\t}\n-      if (RTX_IS (\"+^Sri\"))\n-\t{\n-\t  int rn = REGNO (patternr[3]);\n-\t  HOST_WIDE_INT offs = INTVAL (patternr[4]);\n-\t  if (GET_MODE (patternr[3]) != HImode)\n-\t    return 0;\n-\t  switch (rn)\n-\t    {\n-\t    case A0_REGNO:\n-\t      return (offs >= 0 && offs <= 0xfffff);\n-\n-\t    default:\n-\t      if (IS_PSEUDO (patternr[3], strict))\n-\t\treturn 1;\n-\t      return 0;\n-\t    }\n-\t}\n-      if (RTX_IS (\"+^Srs\"))\n-\t{\n-\t  int rn = REGNO (patternr[3]);\n-\t  if (GET_MODE (patternr[3]) != HImode)\n-\t    return 0;\n-\t  switch (rn)\n-\t    {\n-\t    case A0_REGNO:\n-\t      return 1;\n-\n-\t    default:\n-\t      if (IS_PSEUDO (patternr[3], strict))\n-\t\treturn 1;\n-\t      return 0;\n-\t    }\n-\t}\n-      if (RTX_IS (\"+^S+ris\"))\n-\t{\n-\t  int rn = REGNO (patternr[4]);\n-\t  if (GET_MODE (patternr[4]) != HImode)\n-\t    return 0;\n-\t  switch (rn)\n-\t    {\n-\t    case A0_REGNO:\n-\t      return 1;\n-\n-\t    default:\n-\t      if (IS_PSEUDO (patternr[4], strict))\n-\t\treturn 1;\n-\t      return 0;\n-\t    }\n-\t}\n-      if (RTX_IS (\"s\"))\n-\t{\n-\t  return 1;\n-\t}\n-      return 0;\n-    }\n-\n-  else if (as != ADDR_SPACE_GENERIC)\n-    gcc_unreachable ();\n-\n-  return m32c_legitimate_address_p (mode, x, strict, ch);\n-}\n-\n-/* Like m32c_legitimate_address, except with named address support.  */\n-#undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS\n-#define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address\n-static rtx\n-m32c_addr_space_legitimize_address (rtx x, rtx oldx, machine_mode mode,\n-\t\t\t\t    addr_space_t as)\n-{\n-  if (as != ADDR_SPACE_GENERIC)\n-    {\n-#if DEBUG0\n-      fprintf (stderr, \"\\033[36mm32c_addr_space_legitimize_address for mode %s\\033[0m\\n\", mode_name[mode]);\n-      debug_rtx (x);\n-      fprintf (stderr, \"\\n\");\n-#endif\n-\n-      if (GET_CODE (x) != REG)\n-\t{\n-\t  x = force_reg (SImode, x);\n-\t}\n-      return x;\n-    }\n-\n-  return m32c_legitimize_address (x, oldx, mode);\n-}\n-\n-/* Determine if one named address space is a subset of another.  */\n-#undef TARGET_ADDR_SPACE_SUBSET_P\n-#define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p\n-static bool\n-m32c_addr_space_subset_p (addr_space_t subset, addr_space_t superset)\n-{\n-  gcc_assert (subset == ADDR_SPACE_GENERIC || subset == ADDR_SPACE_FAR);\n-  gcc_assert (superset == ADDR_SPACE_GENERIC || superset == ADDR_SPACE_FAR);\n-\n-  if (subset == superset)\n-    return true;\n-\n-  else\n-    return (subset == ADDR_SPACE_GENERIC && superset == ADDR_SPACE_FAR);\n-}\n-\n-#undef TARGET_ADDR_SPACE_CONVERT\n-#define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert\n-/* Convert from one address space to another.  */\n-static rtx\n-m32c_addr_space_convert (rtx op, tree from_type, tree to_type)\n-{\n-  addr_space_t from_as = TYPE_ADDR_SPACE (TREE_TYPE (from_type));\n-  addr_space_t to_as = TYPE_ADDR_SPACE (TREE_TYPE (to_type));\n-  rtx result;\n-\n-  gcc_assert (from_as == ADDR_SPACE_GENERIC || from_as == ADDR_SPACE_FAR);\n-  gcc_assert (to_as == ADDR_SPACE_GENERIC || to_as == ADDR_SPACE_FAR);\n-\n-  if (to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_FAR)\n-    {\n-      /* This is unpredictable, as we're truncating off usable address\n-\t bits.  */\n-\n-      result = gen_reg_rtx (HImode);\n-      emit_move_insn (result, simplify_subreg (HImode, op, SImode, 0));\n-      return result;\n-    }\n-  else if (to_as == ADDR_SPACE_FAR && from_as == ADDR_SPACE_GENERIC)\n-    {\n-      /* This always works.  */\n-      result = gen_reg_rtx (SImode);\n-      emit_insn (gen_zero_extendhisi2 (result, op));\n-      return result;\n-    }\n-  else\n-    gcc_unreachable ();\n-}\n-\n-/* Condition Code Status */\n-\n-#undef TARGET_FIXED_CONDITION_CODE_REGS\n-#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs\n-static bool\n-m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)\n-{\n-  *p1 = FLG_REGNO;\n-  *p2 = INVALID_REGNUM;\n-  return true;\n-}\n-\n-/* Describing Relative Costs of Operations */\n-\n-/* Implements TARGET_REGISTER_MOVE_COST.  We make impossible moves\n-   prohibitively expensive, like trying to put QIs in r2/r3 (there are\n-   no opcodes to do that).  We also discourage use of mem* registers\n-   since they're really memory.  */\n-\n-#undef TARGET_REGISTER_MOVE_COST\n-#define TARGET_REGISTER_MOVE_COST m32c_register_move_cost\n-\n-static int\n-m32c_register_move_cost (machine_mode mode, reg_class_t from,\n-\t\t\t reg_class_t to)\n-{\n-  int cost = COSTS_N_INSNS (3);\n-  HARD_REG_SET cc;\n-\n-/* FIXME: pick real values, but not 2 for now.  */\n-  cc = reg_class_contents[from] | reg_class_contents[(int) to];\n-\n-  if (mode == QImode\n-      && hard_reg_set_intersect_p (cc, reg_class_contents[R23_REGS]))\n-    {\n-      if (hard_reg_set_subset_p (cc, reg_class_contents[R23_REGS]))\n-\tcost = COSTS_N_INSNS (1000);\n-      else\n-\tcost = COSTS_N_INSNS (80);\n-    }\n-\n-  if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))\n-    cost = COSTS_N_INSNS (1000);\n-\n-  if (reg_classes_intersect_p (from, CR_REGS))\n-    cost += COSTS_N_INSNS (5);\n-\n-  if (reg_classes_intersect_p (to, CR_REGS))\n-    cost += COSTS_N_INSNS (5);\n-\n-  if (from == MEM_REGS || to == MEM_REGS)\n-    cost += COSTS_N_INSNS (50);\n-  else if (reg_classes_intersect_p (from, MEM_REGS)\n-\t   || reg_classes_intersect_p (to, MEM_REGS))\n-    cost += COSTS_N_INSNS (10);\n-\n-#if DEBUG0\n-  fprintf (stderr, \"register_move_cost %s from %s to %s = %d\\n\",\n-\t   mode_name[mode], class_names[(int) from], class_names[(int) to],\n-\t   cost);\n-#endif\n-  return cost;\n-}\n-\n-/*  Implements TARGET_MEMORY_MOVE_COST.  */\n-\n-#undef TARGET_MEMORY_MOVE_COST\n-#define TARGET_MEMORY_MOVE_COST m32c_memory_move_cost\n-\n-static int\n-m32c_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,\n-\t\t       reg_class_t rclass ATTRIBUTE_UNUSED,\n-\t\t       bool in ATTRIBUTE_UNUSED)\n-{\n-  /* FIXME: pick real values.  */\n-  return COSTS_N_INSNS (10);\n-}\n-\n-/* Here we try to describe when we use multiple opcodes for one RTX so\n-   that gcc knows when to use them.  */\n-#undef TARGET_RTX_COSTS\n-#define TARGET_RTX_COSTS m32c_rtx_costs\n-static bool\n-m32c_rtx_costs (rtx x, machine_mode mode, int outer_code,\n-\t\tint opno ATTRIBUTE_UNUSED,\n-\t\tint *total, bool speed ATTRIBUTE_UNUSED)\n-{\n-  int code = GET_CODE (x);\n-  switch (code)\n-    {\n-    case REG:\n-      if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)\n-\t*total += COSTS_N_INSNS (500);\n-      else\n-\t*total += COSTS_N_INSNS (1);\n-      return true;\n-\n-    case ASHIFT:\n-    case LSHIFTRT:\n-    case ASHIFTRT:\n-      if (GET_CODE (XEXP (x, 1)) != CONST_INT)\n-\t{\n-\t  /* mov.b r1l, r1h */\n-\t  *total +=  COSTS_N_INSNS (1);\n-\t  return true;\n-\t}\n-      if (INTVAL (XEXP (x, 1)) > 8\n-\t  || INTVAL (XEXP (x, 1)) < -8)\n-\t{\n-\t  /* mov.b #N, r1l */\n-\t  /* mov.b r1l, r1h */\n-\t  *total +=  COSTS_N_INSNS (2);\n-\t  return true;\n-\t}\n-      return true;\n-\n-    case LE:\n-    case LEU:\n-    case LT:\n-    case LTU:\n-    case GT:\n-    case GTU:\n-    case GE:\n-    case GEU:\n-    case NE:\n-    case EQ:\n-      if (outer_code == SET)\n-\t{\n-\t  *total += COSTS_N_INSNS (2);\n-\t  return true;\n-\t}\n-      break;\n-\n-    case ZERO_EXTRACT:\n-      {\n-\trtx dest = XEXP (x, 0);\n-\trtx addr = XEXP (dest, 0);\n-\tswitch (GET_CODE (addr))\n-\t  {\n-\t  case CONST_INT:\n-\t    *total += COSTS_N_INSNS (1);\n-\t    break;\n-\t  case SYMBOL_REF:\n-\t    *total += COSTS_N_INSNS (3);\n-\t    break;\n-\t  default:\n-\t    *total += COSTS_N_INSNS (2);\n-\t    break;\n-\t  }\n-\treturn true;\n-      }\n-      break;\n-\n-    default:\n-      /* Reasonable default.  */\n-      if (TARGET_A16 && mode == SImode)\n-\t*total += COSTS_N_INSNS (2);\n-      break;\n-    }\n-  return false;\n-}\n-\n-#undef TARGET_ADDRESS_COST\n-#define TARGET_ADDRESS_COST m32c_address_cost\n-static int\n-m32c_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,\n-\t\t   addr_space_t as ATTRIBUTE_UNUSED,\n-\t\t   bool speed ATTRIBUTE_UNUSED)\n-{\n-  int i;\n-  /*  fprintf(stderr, \"\\naddress_cost\\n\");\n-      debug_rtx(addr);*/\n-  switch (GET_CODE (addr))\n-    {\n-    case CONST_INT:\n-      i = INTVAL (addr);\n-      if (i == 0)\n-\treturn COSTS_N_INSNS(1);\n-      if (i > 0 && i <= 255)\n-\treturn COSTS_N_INSNS(2);\n-      if (i > 0 && i <= 65535)\n-\treturn COSTS_N_INSNS(3);\n-      return COSTS_N_INSNS(4);\n-    case SYMBOL_REF:\n-      return COSTS_N_INSNS(4);\n-    case REG:\n-      return COSTS_N_INSNS(1);\n-    case PLUS:\n-      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)\n-\t{\n-\t  i = INTVAL (XEXP (addr, 1));\n-\t  if (i == 0)\n-\t    return COSTS_N_INSNS(1);\n-\t  if (i > 0 && i <= 255)\n-\t    return COSTS_N_INSNS(2);\n-\t  if (i > 0 && i <= 65535)\n-\t    return COSTS_N_INSNS(3);\n-\t}\n-      return COSTS_N_INSNS(4);\n-    default:\n-      return 0;\n-    }\n-}\n-\n-/* Defining the Output Assembler Language */\n-\n-/* Output of Data */\n-\n-/* We may have 24 bit sizes, which is the native address size.\n-   Currently unused, but provided for completeness.  */\n-#undef TARGET_ASM_INTEGER\n-#define TARGET_ASM_INTEGER m32c_asm_integer\n-static bool\n-m32c_asm_integer (rtx x, unsigned int size, int aligned_p)\n-{\n-  switch (size)\n-    {\n-    case 3:\n-      fprintf (asm_out_file, \"\\t.3byte\\t\");\n-      output_addr_const (asm_out_file, x);\n-      fputc ('\\n', asm_out_file);\n-      return true;\n-    case 4:\n-      if (GET_CODE (x) == SYMBOL_REF)\n-\t{\n-\t  fprintf (asm_out_file, \"\\t.long\\t\");\n-\t  output_addr_const (asm_out_file, x);\n-\t  fputc ('\\n', asm_out_file);\n-\t  return true;\n-\t}\n-      break;\n-    }\n-  return default_assemble_integer (x, size, aligned_p);\n-}\n-\n-/* Output of Assembler Instructions */\n-\n-/* We use a lookup table because the addressing modes are non-orthogonal.  */\n-\n-static struct\n-{\n-  char code;\n-  char const *pattern;\n-  char const *format;\n-}\n-const conversions[] = {\n-  { 0, \"r\", \"0\" },\n-\n-  { 0, \"mr\", \"z[1]\" },\n-  { 0, \"m+ri\", \"3[2]\" },\n-  { 0, \"m+rs\", \"3[2]\" },\n-  { 0, \"m+^Zrs\", \"5[4]\" },\n-  { 0, \"m+^Zri\", \"5[4]\" },\n-  { 0, \"m+^Z+ris\", \"7+6[5]\" },\n-  { 0, \"m+^Srs\", \"5[4]\" },\n-  { 0, \"m+^Sri\", \"5[4]\" },\n-  { 0, \"m+^S+ris\", \"7+6[5]\" },\n-  { 0, \"m+r+si\", \"4+5[2]\" },\n-  { 0, \"ms\", \"1\" },\n-  { 0, \"mi\", \"1\" },\n-  { 0, \"m+si\", \"2+3\" },\n-\n-  { 0, \"mmr\", \"[z[2]]\" },\n-  { 0, \"mm+ri\", \"[4[3]]\" },\n-  { 0, \"mm+rs\", \"[4[3]]\" },\n-  { 0, \"mm+r+si\", \"[5+6[3]]\" },\n-  { 0, \"mms\", \"[[2]]\" },\n-  { 0, \"mmi\", \"[[2]]\" },\n-  { 0, \"mm+si\", \"[4[3]]\" },\n-\n-  { 0, \"i\", \"#0\" },\n-  { 0, \"s\", \"#0\" },\n-  { 0, \"+si\", \"#1+2\" },\n-  { 0, \"l\", \"#0\" },\n-\n-  { 'l', \"l\", \"0\" },\n-  { 'd', \"i\", \"0\" },\n-  { 'd', \"s\", \"0\" },\n-  { 'd', \"+si\", \"1+2\" },\n-  { 'D', \"i\", \"0\" },\n-  { 'D', \"s\", \"0\" },\n-  { 'D', \"+si\", \"1+2\" },\n-  { 'x', \"i\", \"#0\" },\n-  { 'X', \"i\", \"#0\" },\n-  { 'm', \"i\", \"#0\" },\n-  { 'b', \"i\", \"#0\" },\n-  { 'B', \"i\", \"0\" },\n-  { 'p', \"i\", \"0\" },\n-\n-  { 0, 0, 0 }\n-};\n-\n-/* This is in order according to the bitfield that pushm/popm use.  */\n-static char const *pushm_regs[] = {\n-  \"fb\", \"sb\", \"a1\", \"a0\", \"r3\", \"r2\", \"r1\", \"r0\"\n-};\n-\n-/* Implements TARGET_PRINT_OPERAND.  */\n-\n-#undef TARGET_PRINT_OPERAND\n-#define TARGET_PRINT_OPERAND m32c_print_operand\n-\n-static void\n-m32c_print_operand (FILE * file, rtx x, int code)\n-{\n-  int i, j, b;\n-  const char *comma;\n-  HOST_WIDE_INT ival;\n-  int unsigned_const = 0;\n-  int force_sign;\n-\n-  /* Multiplies; constants are converted to sign-extended format but\n-   we need unsigned, so 'u' and 'U' tell us what size unsigned we\n-   need.  */\n-  if (code == 'u')\n-    {\n-      unsigned_const = 2;\n-      code = 0;\n-    }\n-  if (code == 'U')\n-    {\n-      unsigned_const = 1;\n-      code = 0;\n-    }\n-  /* This one is only for debugging; you can put it in a pattern to\n-     force this error.  */\n-  if (code == '!')\n-    {\n-      fprintf (stderr, \"dj: unreviewed pattern:\");\n-      if (current_output_insn)\n-\tdebug_rtx (current_output_insn);\n-      gcc_unreachable ();\n-    }\n-  /* PSImode operations are either .w or .l depending on the target.  */\n-  if (code == '&')\n-    {\n-      if (TARGET_A16)\n-\tfprintf (file, \"w\");\n-      else\n-\tfprintf (file, \"l\");\n-      return;\n-    }\n-  /* Inverted conditionals.  */\n-  if (code == 'C')\n-    {\n-      switch (GET_CODE (x))\n-\t{\n-\tcase LE:\n-\t  fputs (\"gt\", file);\n-\t  break;\n-\tcase LEU:\n-\t  fputs (\"gtu\", file);\n-\t  break;\n-\tcase LT:\n-\t  fputs (\"ge\", file);\n-\t  break;\n-\tcase LTU:\n-\t  fputs (\"geu\", file);\n-\t  break;\n-\tcase GT:\n-\t  fputs (\"le\", file);\n-\t  break;\n-\tcase GTU:\n-\t  fputs (\"leu\", file);\n-\t  break;\n-\tcase GE:\n-\t  fputs (\"lt\", file);\n-\t  break;\n-\tcase GEU:\n-\t  fputs (\"ltu\", file);\n-\t  break;\n-\tcase NE:\n-\t  fputs (\"eq\", file);\n-\t  break;\n-\tcase EQ:\n-\t  fputs (\"ne\", file);\n-\t  break;\n-\tdefault:\n-\t  gcc_unreachable ();\n-\t}\n-      return;\n-    }\n-  /* Regular conditionals.  */\n-  if (code == 'c')\n-    {\n-      switch (GET_CODE (x))\n-\t{\n-\tcase LE:\n-\t  fputs (\"le\", file);\n-\t  break;\n-\tcase LEU:\n-\t  fputs (\"leu\", file);\n-\t  break;\n-\tcase LT:\n-\t  fputs (\"lt\", file);\n-\t  break;\n-\tcase LTU:\n-\t  fputs (\"ltu\", file);\n-\t  break;\n-\tcase GT:\n-\t  fputs (\"gt\", file);\n-\t  break;\n-\tcase GTU:\n-\t  fputs (\"gtu\", file);\n-\t  break;\n-\tcase GE:\n-\t  fputs (\"ge\", file);\n-\t  break;\n-\tcase GEU:\n-\t  fputs (\"geu\", file);\n-\t  break;\n-\tcase NE:\n-\t  fputs (\"ne\", file);\n-\t  break;\n-\tcase EQ:\n-\t  fputs (\"eq\", file);\n-\t  break;\n-\tdefault:\n-\t  gcc_unreachable ();\n-\t}\n-      return;\n-    }\n-  /* Used in negsi2 to do HImode ops on the two parts of an SImode\n-     operand.  */\n-  if (code == 'h' && GET_MODE (x) == SImode)\n-    {\n-      x = m32c_subreg (HImode, x, SImode, 0);\n-      code = 0;\n-    }\n-  if (code == 'H' && GET_MODE (x) == SImode)\n-    {\n-      x = m32c_subreg (HImode, x, SImode, 2);\n-      code = 0;\n-    }\n-  if (code == 'h' && GET_MODE (x) == HImode)\n-    {\n-      x = m32c_subreg (QImode, x, HImode, 0);\n-      code = 0;\n-    }\n-  if (code == 'H' && GET_MODE (x) == HImode)\n-    {\n-      /* We can't actually represent this as an rtx.  Do it here.  */\n-      if (GET_CODE (x) == REG)\n-\t{\n-\t  switch (REGNO (x))\n-\t    {\n-\t    case R0_REGNO:\n-\t      fputs (\"r0h\", file);\n-\t      return;\n-\t    case R1_REGNO:\n-\t      fputs (\"r1h\", file);\n-\t      return;\n-\t    default:\n-\t      gcc_unreachable();\n-\t    }\n-\t}\n-      /* This should be a MEM.  */\n-      x = m32c_subreg (QImode, x, HImode, 1);\n-      code = 0;\n-    }\n-  /* This is for BMcond, which always wants word register names.  */\n-  if (code == 'h' && GET_MODE (x) == QImode)\n-    {\n-      if (GET_CODE (x) == REG)\n-\tx = gen_rtx_REG (HImode, REGNO (x));\n-      code = 0;\n-    }\n-  /* 'x' and 'X' need to be ignored for non-immediates.  */\n-  if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)\n-    code = 0;\n-\n-  encode_pattern (x);\n-  force_sign = 0;\n-  for (i = 0; conversions[i].pattern; i++)\n-    if (conversions[i].code == code\n-\t&& streq (conversions[i].pattern, pattern))\n-      {\n-\tfor (j = 0; conversions[i].format[j]; j++)\n-\t  /* backslash quotes the next character in the output pattern.  */\n-\t  if (conversions[i].format[j] == '\\\\')\n-\t    {\n-\t      fputc (conversions[i].format[j + 1], file);\n-\t      j++;\n-\t    }\n-\t  /* Digits in the output pattern indicate that the\n-\t     corresponding RTX is to be output at that point.  */\n-\t  else if (ISDIGIT (conversions[i].format[j]))\n-\t    {\n-\t      rtx r = patternr[conversions[i].format[j] - '0'];\n-\t      switch (GET_CODE (r))\n-\t\t{\n-\t\tcase REG:\n-\t\t  fprintf (file, \"%s\",\n-\t\t\t   reg_name_with_mode (REGNO (r), GET_MODE (r)));\n-\t\t  break;\n-\t\tcase CONST_INT:\n-\t\t  switch (code)\n-\t\t    {\n-\t\t    case 'b':\n-\t\t    case 'B':\n-\t\t      {\n-\t\t\tint v = INTVAL (r);\n-\t\t\tint i = (int) exact_log2 (v);\n-\t\t\tif (i == -1)\n-\t\t\t  i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);\n-\t\t\tif (i == -1)\n-\t\t\t  i = (int) exact_log2 ((v ^ 0xff) & 0xff);\n-\t\t\t/* Bit position.  */\n-\t\t\tfprintf (file, \"%d\", i);\n-\t\t      }\n-\t\t      break;\n-\t\t    case 'x':\n-\t\t      /* Unsigned byte.  */\n-\t\t      fprintf (file, HOST_WIDE_INT_PRINT_HEX,\n-\t\t\t       INTVAL (r) & 0xff);\n-\t\t      break;\n-\t\t    case 'X':\n-\t\t      /* Unsigned word.  */\n-\t\t      fprintf (file, HOST_WIDE_INT_PRINT_HEX,\n-\t\t\t       INTVAL (r) & 0xffff);\n-\t\t      break;\n-\t\t    case 'p':\n-\t\t      /* pushm and popm encode a register set into a single byte.  */\n-\t\t      comma = \"\";\n-\t\t      for (b = 7; b >= 0; b--)\n-\t\t\tif (INTVAL (r) & (1 << b))\n-\t\t\t  {\n-\t\t\t    fprintf (file, \"%s%s\", comma, pushm_regs[b]);\n-\t\t\t    comma = \",\";\n-\t\t\t  }\n-\t\t      break;\n-\t\t    case 'm':\n-\t\t      /* \"Minus\".  Output -X  */\n-\t\t      ival = (-INTVAL (r) & 0xffff);\n-\t\t      if (ival & 0x8000)\n-\t\t\tival = ival - 0x10000;\n-\t\t      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);\n-\t\t      break;\n-\t\t    default:\n-\t\t      ival = INTVAL (r);\n-\t\t      if (conversions[i].format[j + 1] == '[' && ival < 0)\n-\t\t\t{\n-\t\t\t  /* We can simulate negative displacements by\n-\t\t\t     taking advantage of address space\n-\t\t\t     wrapping when the offset can span the\n-\t\t\t     entire address range.  */\n-\t\t\t  rtx base =\n-\t\t\t    patternr[conversions[i].format[j + 2] - '0'];\n-\t\t\t  if (GET_CODE (base) == REG)\n-\t\t\t    switch (REGNO (base))\n-\t\t\t      {\n-\t\t\t      case A0_REGNO:\n-\t\t\t      case A1_REGNO:\n-\t\t\t\tif (TARGET_A24)\n-\t\t\t\t  ival = 0x1000000 + ival;\n-\t\t\t\telse\n-\t\t\t\t  ival = 0x10000 + ival;\n-\t\t\t\tbreak;\n-\t\t\t      case SB_REGNO:\n-\t\t\t\tif (TARGET_A16)\n-\t\t\t\t  ival = 0x10000 + ival;\n-\t\t\t\tbreak;\n-\t\t\t      }\n-\t\t\t}\n-\t\t      else if (code == 'd' && ival < 0 && j == 0)\n-\t\t\t/* The \"mova\" opcode is used to do addition by\n-\t\t\t   computing displacements, but again, we need\n-\t\t\t   displacements to be unsigned *if* they're\n-\t\t\t   the only component of the displacement\n-\t\t\t   (i.e. no \"symbol-4\" type displacement).  */\n-\t\t\tival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;\n-\n-\t\t      if (conversions[i].format[j] == '0')\n-\t\t\t{\n-\t\t\t  /* More conversions to unsigned.  */\n-\t\t\t  if (unsigned_const == 2)\n-\t\t\t    ival &= 0xffff;\n-\t\t\t  if (unsigned_const == 1)\n-\t\t\t    ival &= 0xff;\n-\t\t\t}\n-\t\t      if (streq (conversions[i].pattern, \"mi\")\n-\t\t\t  || streq (conversions[i].pattern, \"mmi\"))\n-\t\t\t{\n-\t\t\t  /* Integers used as addresses are unsigned.  */\n-\t\t\t  ival &= (TARGET_A24 ? 0xffffff : 0xffff);\n-\t\t\t}\n-\t\t      if (force_sign && ival >= 0)\n-\t\t\tfputc ('+', file);\n-\t\t      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);\n-\t\t      break;\n-\t\t    }\n-\t\t  break;\n-\t\tcase CONST_DOUBLE:\n-\t\t  /* We don't have const_double constants.  If it\n-\t\t     happens, make it obvious.  */\n-\t\t  fprintf (file, \"[const_double 0x%lx]\",\n-\t\t\t   (unsigned long) CONST_DOUBLE_HIGH (r));\n-\t\t  break;\n-\t\tcase SYMBOL_REF:\n-\t\t  assemble_name (file, XSTR (r, 0));\n-\t\t  break;\n-\t\tcase LABEL_REF:\n-\t\t  output_asm_label (r);\n-\t\t  break;\n-\t\tdefault:\n-\t\t  fprintf (stderr, \"don't know how to print this operand:\");\n-\t\t  debug_rtx (r);\n-\t\t  gcc_unreachable ();\n-\t\t}\n-\t    }\n-\t  else\n-\t    {\n-\t      if (conversions[i].format[j] == 'z')\n-\t\t{\n-\t\t  /* Some addressing modes *must* have a displacement,\n-\t\t     so insert a zero here if needed.  */\n-\t\t  int k;\n-\t\t  for (k = j + 1; conversions[i].format[k]; k++)\n-\t\t    if (ISDIGIT (conversions[i].format[k]))\n-\t\t      {\n-\t\t\trtx reg = patternr[conversions[i].format[k] - '0'];\n-\t\t\tif (GET_CODE (reg) == REG\n-\t\t\t    && (REGNO (reg) == SB_REGNO\n-\t\t\t\t|| REGNO (reg) == FB_REGNO\n-\t\t\t\t|| REGNO (reg) == SP_REGNO))\n-\t\t\t  fputc ('0', file);\n-\t\t      }\n-\t\t  continue;\n-\t\t}\n-\t      /* Signed displacements off symbols need to have signs\n-\t\t blended cleanly.  */\n-\t      if (conversions[i].format[j] == '+'\n-\t\t  && (!code || code == 'D' || code == 'd')\n-\t\t  && ISDIGIT (conversions[i].format[j + 1])\n-\t\t  && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])\n-\t\t      == CONST_INT))\n-\t\t{\n-\t\t  force_sign = 1;\n-\t\t  continue;\n-\t\t}\n-\t      fputc (conversions[i].format[j], file);\n-\t    }\n-\tbreak;\n-      }\n-  if (!conversions[i].pattern)\n-    {\n-      fprintf (stderr, \"unconvertible operand %c `%s'\", code ? code : '-',\n-\t       pattern);\n-      debug_rtx (x);\n-      fprintf (file, \"[%c.%s]\", code ? code : '-', pattern);\n-    }\n-\n-  return;\n-}\n-\n-/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P.\n-\n-   See m32c_print_operand above for descriptions of what these do.  */\n-\n-#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P\n-#define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32c_print_operand_punct_valid_p\n-\n-static bool\n-m32c_print_operand_punct_valid_p (unsigned char c)\n-{\n-  if (c == '&' || c == '!')\n-    return true;\n-\n-  return false;\n-}\n-\n-/* Implements TARGET_PRINT_OPERAND_ADDRESS.  Nothing unusual here.  */\n-\n-#undef TARGET_PRINT_OPERAND_ADDRESS\n-#define TARGET_PRINT_OPERAND_ADDRESS m32c_print_operand_address\n-\n-static void\n-m32c_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx address)\n-{\n-  if (GET_CODE (address) == MEM)\n-    address = XEXP (address, 0);\n-  else\n-    /* cf: gcc.dg/asm-4.c.  */\n-    gcc_assert (GET_CODE (address) == REG);\n-\n-  m32c_print_operand (stream, address, 0);\n-}\n-\n-/* Implements ASM_OUTPUT_REG_PUSH.  Control registers are pushed\n-   differently than general registers.  */\n-void\n-m32c_output_reg_push (FILE * s, int regno)\n-{\n-  if (regno == FLG_REGNO)\n-    fprintf (s, \"\\tpushc\\tflg\\n\");\n-  else\n-    fprintf (s, \"\\tpush.%c\\t%s\\n\",\n-\t     \" bwll\"[reg_push_size (regno)], reg_names[regno]);\n-}\n-\n-/* Likewise for ASM_OUTPUT_REG_POP.  */\n-void\n-m32c_output_reg_pop (FILE * s, int regno)\n-{\n-  if (regno == FLG_REGNO)\n-    fprintf (s, \"\\tpopc\\tflg\\n\");\n-  else\n-    fprintf (s, \"\\tpop.%c\\t%s\\n\",\n-\t     \" bwll\"[reg_push_size (regno)], reg_names[regno]);\n-}\n-\n-/* Defining target-specific uses of `__attribute__' */\n-\n-/* Used to simplify the logic below.  Find the attributes wherever\n-   they may be.  */\n-#define M32C_ATTRIBUTES(decl) \\\n-  (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \\\n-                : DECL_ATTRIBUTES (decl) \\\n-                  ? (DECL_ATTRIBUTES (decl)) \\\n-\t\t  : TYPE_ATTRIBUTES (TREE_TYPE (decl))\n-\n-/* Returns TRUE if the given tree has the \"interrupt\" attribute.  */\n-static int\n-interrupt_p (tree node ATTRIBUTE_UNUSED)\n-{\n-  tree list = M32C_ATTRIBUTES (node);\n-  while (list)\n-    {\n-      if (is_attribute_p (\"interrupt\", TREE_PURPOSE (list)))\n-\treturn 1;\n-      list = TREE_CHAIN (list);\n-    }\n-  return fast_interrupt_p (node);\n-}\n-\n-/* Returns TRUE if the given tree has the \"bank_switch\" attribute.  */\n-static int\n-bank_switch_p (tree node ATTRIBUTE_UNUSED)\n-{\n-  tree list = M32C_ATTRIBUTES (node);\n-  while (list)\n-    {\n-      if (is_attribute_p (\"bank_switch\", TREE_PURPOSE (list)))\n-\treturn 1;\n-      list = TREE_CHAIN (list);\n-    }\n-  return 0;\n-}\n-\n-/* Returns TRUE if the given tree has the \"fast_interrupt\" attribute.  */\n-static int\n-fast_interrupt_p (tree node ATTRIBUTE_UNUSED)\n-{\n-  tree list = M32C_ATTRIBUTES (node);\n-  while (list)\n-    {\n-      if (is_attribute_p (\"fast_interrupt\", TREE_PURPOSE (list)))\n-\treturn 1;\n-      list = TREE_CHAIN (list);\n-    }\n-  return 0;\n-}\n-\n-static tree\n-interrupt_handler (tree * node ATTRIBUTE_UNUSED,\n-\t\t   tree name ATTRIBUTE_UNUSED,\n-\t\t   tree args ATTRIBUTE_UNUSED,\n-\t\t   int flags ATTRIBUTE_UNUSED,\n-\t\t   bool * no_add_attrs ATTRIBUTE_UNUSED)\n-{\n-  return NULL_TREE;\n-}\n-\n-/* Returns TRUE if given tree has the \"function_vector\" attribute. */\n-int\n-m32c_special_page_vector_p (tree func)\n-{\n-  tree list;\n-\n-  if (TREE_CODE (func) != FUNCTION_DECL)\n-    return 0;\n-\n-  list = M32C_ATTRIBUTES (func);\n-  while (list)\n-    {\n-      if (is_attribute_p (\"function_vector\", TREE_PURPOSE (list)))\n-        return 1;\n-      list = TREE_CHAIN (list);\n-    }\n-  return 0;\n-}\n-\n-static tree\n-function_vector_handler (tree * node ATTRIBUTE_UNUSED,\n-                         tree name ATTRIBUTE_UNUSED,\n-                         tree args ATTRIBUTE_UNUSED,\n-                         int flags ATTRIBUTE_UNUSED,\n-                         bool * no_add_attrs ATTRIBUTE_UNUSED)\n-{\n-  if (TARGET_R8C)\n-    {\n-      /* The attribute is not supported for R8C target.  */\n-      warning (OPT_Wattributes,\n-                \"%qE attribute is not supported for R8C target\",\n-                name);\n-      *no_add_attrs = true;\n-    }\n-  else if (TREE_CODE (*node) != FUNCTION_DECL)\n-    {\n-      /* The attribute must be applied to functions only.  */\n-      warning (OPT_Wattributes,\n-                \"%qE attribute applies only to functions\",\n-                name);\n-      *no_add_attrs = true;\n-    }\n-  else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)\n-    {\n-      /* The argument must be a constant integer.  */\n-      warning (OPT_Wattributes,\n-                \"%qE attribute argument not an integer constant\",\n-                name);\n-      *no_add_attrs = true;\n-    }\n-  else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18\n-           || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)\n-    {\n-      /* The argument value must be between 18 to 255.  */\n-      warning (OPT_Wattributes,\n-                \"%qE attribute argument should be between 18 to 255\",\n-                name);\n-      *no_add_attrs = true;\n-    }\n-  return NULL_TREE;\n-}\n-\n-/* If the function is assigned the attribute 'function_vector', it\n-   returns the function vector number, otherwise returns zero.  */\n-int\n-current_function_special_page_vector (rtx x)\n-{\n-  int num;\n-\n-  if ((GET_CODE(x) == SYMBOL_REF)\n-      && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))\n-    {\n-      tree list;\n-      tree t = SYMBOL_REF_DECL (x);\n-\n-      if (TREE_CODE (t) != FUNCTION_DECL)\n-        return 0;\n-\n-      list = M32C_ATTRIBUTES (t);\n-      while (list)\n-        {\n-          if (is_attribute_p (\"function_vector\", TREE_PURPOSE (list)))\n-            {\n-              num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));\n-              return num;\n-            }\n-\n-          list = TREE_CHAIN (list);\n-        }\n-\n-      return 0;\n-    }\n-  else\n-    return 0;\n-}\n-\n-#undef TARGET_ATTRIBUTE_TABLE\n-#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table\n-TARGET_GNU_ATTRIBUTES (m32c_attribute_table, {\n-  /* { name, min_len, max_len, decl_req, type_req, fn_type_req,\n-       affects_type_identity, handler, exclude } */\n-  { \"interrupt\", 0, 0, false, false, false, false, interrupt_handler, NULL },\n-  { \"bank_switch\", 0, 0, false, false, false, false, interrupt_handler, NULL },\n-  { \"fast_interrupt\", 0, 0, false, false, false, false,\n-    interrupt_handler, NULL },\n-  { \"function_vector\", 1, 1, true,  false, false, false,\n-    function_vector_handler, NULL }\n-});\n-\n-#undef TARGET_COMP_TYPE_ATTRIBUTES\n-#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes\n-static int\n-m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,\n-\t\t\t   const_tree type2 ATTRIBUTE_UNUSED)\n-{\n-  /* 0=incompatible 1=compatible 2=warning */\n-  return 1;\n-}\n-\n-#undef TARGET_INSERT_ATTRIBUTES\n-#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes\n-static void\n-m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,\n-\t\t\ttree * attr_ptr ATTRIBUTE_UNUSED)\n-{\n-  unsigned addr;\n-  /* See if we need to make #pragma address variables volatile.  */\n-\n-  if (VAR_P (node))\n-    {\n-      const char *name = IDENTIFIER_POINTER (DECL_NAME (node));\n-      if (m32c_get_pragma_address  (name, &addr))\n-\t{\n-\t  TREE_THIS_VOLATILE (node) = true;\n-\t}\n-    }\n-}\n-\n-/* Hash table of pragma info.  */\n-static GTY(()) hash_map<nofree_string_hash, unsigned> *pragma_htab;\n-\n-void\n-m32c_note_pragma_address (const char *varname, unsigned address)\n-{\n-  if (!pragma_htab)\n-    pragma_htab = hash_map<nofree_string_hash, unsigned>::create_ggc (31);\n-\n-  const char *name = ggc_strdup (varname);\n-  unsigned int *slot = &pragma_htab->get_or_insert (name);\n-  *slot = address;\n-}\n-\n-static bool\n-m32c_get_pragma_address (const char *varname, unsigned *address)\n-{\n-  if (!pragma_htab)\n-    return false;\n-\n-  unsigned int *slot = pragma_htab->get (varname);\n-  if (slot)\n-    {\n-      *address = *slot;\n-      return true;\n-    }\n-  return false;\n-}\n-\n-void\n-m32c_output_aligned_common (FILE *stream, tree decl ATTRIBUTE_UNUSED,\n-\t\t\t    const char *name,\n-\t\t\t    int size, int align, int global)\n-{\n-  unsigned address;\n-\n-  if (m32c_get_pragma_address (name, &address))\n-    {\n-      /* We never output these as global.  */\n-      assemble_name (stream, name);\n-      fprintf (stream, \" = 0x%04x\\n\", address);\n-      return;\n-    }\n-  if (!global)\n-    {\n-      fprintf (stream, \"\\t.local\\t\");\n-      assemble_name (stream, name);\n-      fprintf (stream, \"\\n\");\n-    }\n-  fprintf (stream, \"\\t.comm\\t\");\n-  assemble_name (stream, name);\n-  fprintf (stream, \",%u,%u\\n\", size, align / BITS_PER_UNIT);\n-}\n-\n-/* Predicates */\n-\n-/* This is a list of legal subregs of hard regs.  */\n-static const struct {\n-  unsigned char outer_mode_size;\n-  unsigned char inner_mode_size;\n-  unsigned char byte_mask;\n-  unsigned char legal_when;\n-  unsigned int regno;\n-} legal_subregs[] = {\n-  {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */\n-  {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */\n-  {1, 2, 0x01, 1, A0_REGNO},\n-  {1, 2, 0x01, 1, A1_REGNO},\n-\n-  {1, 4, 0x01, 1, A0_REGNO},\n-  {1, 4, 0x01, 1, A1_REGNO},\n-\n-  {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */\n-  {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */\n-  {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */\n-  {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */\n-  {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */\n-\n-  {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */\n-};\n-\n-/* Returns TRUE if OP is a subreg of a hard reg which we don't\n-   support.  We also bail on MEMs with illegal addresses.  */\n-bool\n-m32c_illegal_subreg_p (rtx op)\n-{\n-  int offset;\n-  unsigned int i;\n-  machine_mode src_mode, dest_mode;\n-\n-  if (GET_CODE (op) == MEM\n-      && ! m32c_legitimate_address_p (Pmode, XEXP (op, 0), false))\n-    {\n-      return true;\n-    }\n-\n-  if (GET_CODE (op) != SUBREG)\n-    return false;\n-\n-  dest_mode = GET_MODE (op);\n-  offset = SUBREG_BYTE (op);\n-  op = SUBREG_REG (op);\n-  src_mode = GET_MODE (op);\n-\n-  if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))\n-    return false;\n-  if (GET_CODE (op) != REG)\n-    return false;\n-  if (REGNO (op) >= MEM0_REGNO)\n-    return false;\n-\n-  offset = (1 << offset);\n-\n-  for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)\n-    if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)\n-\t&& legal_subregs[i].regno == REGNO (op)\n-\t&& legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)\n-\t&& legal_subregs[i].byte_mask & offset)\n-      {\n-\tswitch (legal_subregs[i].legal_when)\n-\t  {\n-\t  case 1:\n-\t    return false;\n-\t  case 16:\n-\t    if (TARGET_A16)\n-\t      return false;\n-\t    break;\n-\t  case 24:\n-\t    if (TARGET_A24)\n-\t      return false;\n-\t    break;\n-\t  }\n-      }\n-  return true;\n-}\n-\n-/* Returns TRUE if we support a move between the first two operands.\n-   At the moment, we just want to discourage mem to mem moves until\n-   after reload, because reload has a hard time with our limited\n-   number of address registers, and we can get into a situation where\n-   we need three of them when we only have two.  */\n-bool\n-m32c_mov_ok (rtx * operands, machine_mode mode ATTRIBUTE_UNUSED)\n-{\n-  rtx op0 = operands[0];\n-  rtx op1 = operands[1];\n-\n-  if (TARGET_A24)\n-    return true;\n-\n-#define DEBUG_MOV_OK 0\n-#if DEBUG_MOV_OK\n-  fprintf (stderr, \"m32c_mov_ok %s\\n\", mode_name[mode]);\n-  debug_rtx (op0);\n-  debug_rtx (op1);\n-#endif\n-\n-  if (GET_CODE (op0) == SUBREG)\n-    op0 = XEXP (op0, 0);\n-  if (GET_CODE (op1) == SUBREG)\n-    op1 = XEXP (op1, 0);\n-\n-  if (GET_CODE (op0) == MEM\n-      && GET_CODE (op1) == MEM\n-      && ! reload_completed)\n-    {\n-#if DEBUG_MOV_OK\n-      fprintf (stderr, \" - no, mem to mem\\n\");\n-#endif\n-      return false;\n-    }\n-\n-#if DEBUG_MOV_OK\n-  fprintf (stderr, \" - ok\\n\");\n-#endif\n-  return true;\n-}\n-\n-/* Returns TRUE if two consecutive HImode mov instructions, generated\n-   for moving an immediate double data to a double data type variable\n-   location, can be combined into single SImode mov instruction.  */\n-bool\n-m32c_immd_dbl_mov (rtx * operands ATTRIBUTE_UNUSED,\n-\t\t   machine_mode mode ATTRIBUTE_UNUSED)\n-{\n-  /* ??? This relied on the now-defunct MEM_SCALAR and MEM_IN_STRUCT_P\n-     flags.  */\n-  return false;\n-}\n-\n-/* Expanders */\n-\n-/* Subregs are non-orthogonal for us, because our registers are all\n-   different sizes.  */\n-static rtx\n-m32c_subreg (machine_mode outer,\n-\t     rtx x, machine_mode inner, int byte)\n-{\n-  int r, nr = -1;\n-\n-  /* Converting MEMs to different types that are the same size, we\n-     just rewrite them.  */\n-  if (GET_CODE (x) == SUBREG\n-      && SUBREG_BYTE (x) == 0\n-      && GET_CODE (SUBREG_REG (x)) == MEM\n-      && (GET_MODE_SIZE (GET_MODE (x))\n-\t  == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))\n-    {\n-      rtx oldx = x;\n-      x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));\n-      MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));\n-    }\n-\n-  /* Push/pop get done as smaller push/pops.  */\n-  if (GET_CODE (x) == MEM\n-      && (GET_CODE (XEXP (x, 0)) == PRE_DEC\n-\t  || GET_CODE (XEXP (x, 0)) == POST_INC))\n-    return gen_rtx_MEM (outer, XEXP (x, 0));\n-  if (GET_CODE (x) == SUBREG\n-      && GET_CODE (XEXP (x, 0)) == MEM\n-      && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC\n-\t  || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))\n-    return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));\n-\n-  if (GET_CODE (x) != REG)\n-    {\n-      rtx r = simplify_gen_subreg (outer, x, inner, byte);\n-      if (GET_CODE (r) == SUBREG\n-\t  && GET_CODE (x) == MEM\n-\t  && MEM_VOLATILE_P (x))\n-\t{\n-\t  /* Volatile MEMs don't get simplified, but we need them to\n-\t     be.  We are little endian, so the subreg byte is the\n-\t     offset.  */\n-\t  r = adjust_address_nv (x, outer, byte);\n-\t}\n-      return r;\n-    }\n-\n-  r = REGNO (x);\n-  if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)\n-    return simplify_gen_subreg (outer, x, inner, byte);\n-\n-  if (IS_MEM_REGNO (r))\n-    return simplify_gen_subreg (outer, x, inner, byte);\n-\n-  /* This is where the complexities of our register layout are\n-     described.  */\n-  if (byte == 0)\n-    nr = r;\n-  else if (outer == HImode)\n-    {\n-      if (r == R0_REGNO && byte == 2)\n-\tnr = R2_REGNO;\n-      else if (r == R0_REGNO && byte == 4)\n-\tnr = R1_REGNO;\n-      else if (r == R0_REGNO && byte == 6)\n-\tnr = R3_REGNO;\n-      else if (r == R1_REGNO && byte == 2)\n-\tnr = R3_REGNO;\n-      else if (r == A0_REGNO && byte == 2)\n-\tnr = A1_REGNO;\n-    }\n-  else if (outer == SImode)\n-    {\n-      if (r == R0_REGNO && byte == 0)\n-\tnr = R0_REGNO;\n-      else if (r == R0_REGNO && byte == 4)\n-\tnr = R1_REGNO;\n-    }\n-  if (nr == -1)\n-    {\n-      fprintf (stderr, \"m32c_subreg %s %s %d\\n\",\n-\t       mode_name[outer], mode_name[inner], byte);\n-      debug_rtx (x);\n-      gcc_unreachable ();\n-    }\n-  return gen_rtx_REG (outer, nr);\n-}\n-\n-/* Used to emit move instructions.  We split some moves,\n-   and avoid mem-mem moves.  */\n-int\n-m32c_prepare_move (rtx * operands, machine_mode mode)\n-{\n-  if (far_addr_space_p (operands[0])\n-      && CONSTANT_P (operands[1]))\n-    {\n-      operands[1] = force_reg (GET_MODE (operands[0]), operands[1]);\n-    }\n-  if (TARGET_A16 && mode == PSImode)\n-    return m32c_split_move (operands, mode, 1);\n-  if ((GET_CODE (operands[0]) == MEM)\n-      && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))\n-    {\n-      rtx pmv = XEXP (operands[0], 0);\n-      rtx dest_reg = XEXP (pmv, 0);\n-      rtx dest_mod = XEXP (pmv, 1);\n-\n-      emit_insn (gen_rtx_SET (dest_reg, dest_mod));\n-      operands[0] = gen_rtx_MEM (mode, dest_reg);\n-    }\n-  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))\n-    operands[1] = copy_to_mode_reg (mode, operands[1]);\n-  return 0;\n-}\n-\n-#define DEBUG_SPLIT 0\n-\n-/* Returns TRUE if the given PSImode move should be split.  We split\n-   for all r8c/m16c moves, since it doesn't support them, and for\n-   POP.L as we can only *push* SImode.  */\n-int\n-m32c_split_psi_p (rtx * operands)\n-{\n-#if DEBUG_SPLIT\n-  fprintf (stderr, \"\\nm32c_split_psi_p\\n\");\n-  debug_rtx (operands[0]);\n-  debug_rtx (operands[1]);\n-#endif\n-  if (TARGET_A16)\n-    {\n-#if DEBUG_SPLIT\n-      fprintf (stderr, \"yes, A16\\n\");\n-#endif\n-      return 1;\n-    }\n-  if (GET_CODE (operands[1]) == MEM\n-      && GET_CODE (XEXP (operands[1], 0)) == POST_INC)\n-    {\n-#if DEBUG_SPLIT\n-      fprintf (stderr, \"yes, pop.l\\n\");\n-#endif\n-      return 1;\n-    }\n-#if DEBUG_SPLIT\n-  fprintf (stderr, \"no, default\\n\");\n-#endif\n-  return 0;\n-}\n-\n-/* Split the given move.  SPLIT_ALL is 0 if splitting is optional\n-   (define_expand), 1 if it is not optional (define_insn_and_split),\n-   and 3 for define_split (alternate api). */\n-int\n-m32c_split_move (rtx * operands, machine_mode mode, int split_all)\n-{\n-  rtx s[4], d[4];\n-  int parts, si, di, rev = 0;\n-  int rv = 0, opi = 2;\n-  machine_mode submode = HImode;\n-  rtx *ops, local_ops[10];\n-\n-  /* define_split modifies the existing operands, but the other two\n-     emit new insns.  OPS is where we store the operand pairs, which\n-     we emit later.  */\n-  if (split_all == 3)\n-    ops = operands;\n-  else\n-    ops = local_ops;\n-\n-  /* Else HImode.  */\n-  if (mode == DImode)\n-    submode = SImode;\n-\n-  /* Before splitting mem-mem moves, force one operand into a\n-     register.  */\n-  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))\n-    {\n-#if DEBUG0\n-      fprintf (stderr, \"force_reg...\\n\");\n-      debug_rtx (operands[1]);\n-#endif\n-      operands[1] = force_reg (mode, operands[1]);\n-#if DEBUG0\n-      debug_rtx (operands[1]);\n-#endif\n-    }\n-\n-  parts = 2;\n-\n-#if DEBUG_SPLIT\n-  fprintf (stderr, \"\\nsplit_move %d all=%d\\n\", !can_create_pseudo_p (),\n-\t   split_all);\n-  debug_rtx (operands[0]);\n-  debug_rtx (operands[1]);\n-#endif\n-\n-  /* Note that split_all is not used to select the api after this\n-     point, so it's safe to set it to 3 even with define_insn.  */\n-  /* None of the chips can move SI operands to sp-relative addresses,\n-     so we always split those.  */\n-  if (satisfies_constraint_Ss (operands[0]))\n-    split_all = 3;\n-\n-  if (TARGET_A16\n-      && (far_addr_space_p (operands[0])\n-\t  || far_addr_space_p (operands[1])))\n-    split_all |= 1;\n-\n-  /* We don't need to split these.  */\n-  if (TARGET_A24\n-      && split_all != 3\n-      && (mode == SImode || mode == PSImode)\n-      && !(GET_CODE (operands[1]) == MEM\n-\t   && GET_CODE (XEXP (operands[1], 0)) == POST_INC))\n-    return 0;\n-\n-  /* First, enumerate the subregs we'll be dealing with.  */\n-  for (si = 0; si < parts; si++)\n-    {\n-      d[si] =\n-\tm32c_subreg (submode, operands[0], mode,\n-\t\t     si * GET_MODE_SIZE (submode));\n-      s[si] =\n-\tm32c_subreg (submode, operands[1], mode,\n-\t\t     si * GET_MODE_SIZE (submode));\n-    }\n-\n-  /* Split pushes by emitting a sequence of smaller pushes.  */\n-  if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)\n-    {\n-      for (si = parts - 1; si >= 0; si--)\n-\t{\n-\t  ops[opi++] = gen_rtx_MEM (submode,\n-\t\t\t\t    gen_rtx_PRE_DEC (Pmode,\n-\t\t\t\t\t\t     gen_rtx_REG (Pmode,\n-\t\t\t\t\t\t\t\t  SP_REGNO)));\n-\t  ops[opi++] = s[si];\n-\t}\n-\n-      rv = 1;\n-    }\n-  /* Likewise for pops.  */\n-  else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)\n-    {\n-      for (di = 0; di < parts; di++)\n-\t{\n-\t  ops[opi++] = d[di];\n-\t  ops[opi++] = gen_rtx_MEM (submode,\n-\t\t\t\t    gen_rtx_POST_INC (Pmode,\n-\t\t\t\t\t\t      gen_rtx_REG (Pmode,\n-\t\t\t\t\t\t\t\t   SP_REGNO)));\n-\t}\n-      rv = 1;\n-    }\n-  else if (split_all)\n-    {\n-      /* if d[di] == s[si] for any di < si, we'll early clobber. */\n-      for (di = 0; di < parts - 1; di++)\n-\tfor (si = di + 1; si < parts; si++)\n-\t  if (reg_mentioned_p (d[di], s[si]))\n-\t    rev = 1;\n-\n-      if (rev)\n-\tfor (si = 0; si < parts; si++)\n-\t  {\n-\t    ops[opi++] = d[si];\n-\t    ops[opi++] = s[si];\n-\t  }\n-      else\n-\tfor (si = parts - 1; si >= 0; si--)\n-\t  {\n-\t    ops[opi++] = d[si];\n-\t    ops[opi++] = s[si];\n-\t  }\n-      rv = 1;\n-    }\n-  /* Now emit any moves we may have accumulated.  */\n-  if (rv && split_all != 3)\n-    {\n-      int i;\n-      for (i = 2; i < opi; i += 2)\n-\temit_move_insn (ops[i], ops[i + 1]);\n-    }\n-  return rv;\n-}\n-\n-/* The m32c has a number of opcodes that act like memcpy, strcmp, and\n-   the like.  For the R8C they expect one of the addresses to be in\n-   R1L:An so we need to arrange for that.  Otherwise, it's just a\n-   matter of picking out the operands we want and emitting the right\n-   pattern for them.  All these expanders, which correspond to\n-   patterns in blkmov.md, must return nonzero if they expand the insn,\n-   or zero if they should FAIL.  */\n-\n-/* This is a memset() opcode.  All operands are implied, so we need to\n-   arrange for them to be in the right registers.  The opcode wants\n-   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1\n-   the count (HI), and $2 the value (QI).  */\n-int\n-m32c_expand_setmemhi(rtx *operands)\n-{\n-  rtx desta, count, val;\n-  rtx desto, counto;\n-\n-  desta = XEXP (operands[0], 0);\n-  count = operands[1];\n-  val = operands[2];\n-\n-  desto = gen_reg_rtx (Pmode);\n-  counto = gen_reg_rtx (HImode);\n-\n-  if (GET_CODE (desta) != REG\n-      || REGNO (desta) < FIRST_PSEUDO_REGISTER)\n-    desta = copy_to_mode_reg (Pmode, desta);\n-\n-  /* This looks like an arbitrary restriction, but this is by far the\n-     most common case.  For counts 8..14 this actually results in\n-     smaller code with no speed penalty because the half-sized\n-     constant can be loaded with a shorter opcode.  */\n-  if (GET_CODE (count) == CONST_INT\n-      && GET_CODE (val) == CONST_INT\n-      && ! (INTVAL (count) & 1)\n-      && (INTVAL (count) > 1)\n-      && (INTVAL (val) <= 7 && INTVAL (val) >= -8))\n-    {\n-      unsigned v = INTVAL (val) & 0xff;\n-      v = v | (v << 8);\n-      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));\n-      val = copy_to_mode_reg (HImode, GEN_INT (v));\n-      if (TARGET_A16)\n-\temit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));\n-      else\n-\temit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));\n-      return 1;\n-    }\n-\n-  /* This is the generalized memset() case.  */\n-  if (GET_CODE (val) != REG\n-      || REGNO (val) < FIRST_PSEUDO_REGISTER)\n-    val = copy_to_mode_reg (QImode, val);\n-\n-  if (GET_CODE (count) != REG\n-      || REGNO (count) < FIRST_PSEUDO_REGISTER)\n-    count = copy_to_mode_reg (HImode, count);\n-\n-  if (TARGET_A16)\n-    emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));\n-  else\n-    emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));\n-\n-  return 1;\n-}\n-\n-/* This is a memcpy() opcode.  All operands are implied, so we need to\n-   arrange for them to be in the right registers.  The opcode wants\n-   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1\n-   is the source (MEM:BLK), and $2 the count (HI).  */\n-int\n-m32c_expand_cpymemhi(rtx *operands)\n-{\n-  rtx desta, srca, count;\n-  rtx desto, srco, counto;\n-\n-  desta = XEXP (operands[0], 0);\n-  srca = XEXP (operands[1], 0);\n-  count = operands[2];\n-\n-  desto = gen_reg_rtx (Pmode);\n-  srco = gen_reg_rtx (Pmode);\n-  counto = gen_reg_rtx (HImode);\n-\n-  if (GET_CODE (desta) != REG\n-      || REGNO (desta) < FIRST_PSEUDO_REGISTER)\n-    desta = copy_to_mode_reg (Pmode, desta);\n-\n-  if (GET_CODE (srca) != REG\n-      || REGNO (srca) < FIRST_PSEUDO_REGISTER)\n-    srca = copy_to_mode_reg (Pmode, srca);\n-\n-  /* Similar to setmem, but we don't need to check the value.  */\n-  if (GET_CODE (count) == CONST_INT\n-      && ! (INTVAL (count) & 1)\n-      && (INTVAL (count) > 1))\n-    {\n-      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));\n-      if (TARGET_A16)\n-\temit_insn (gen_cpymemhi_whi_op (desto, srco, counto, desta, srca, count));\n-      else\n-\temit_insn (gen_cpymemhi_wpsi_op (desto, srco, counto, desta, srca, count));\n-      return 1;\n-    }\n-\n-  /* This is the generalized memset() case.  */\n-  if (GET_CODE (count) != REG\n-      || REGNO (count) < FIRST_PSEUDO_REGISTER)\n-    count = copy_to_mode_reg (HImode, count);\n-\n-  if (TARGET_A16)\n-    emit_insn (gen_cpymemhi_bhi_op (desto, srco, counto, desta, srca, count));\n-  else\n-    emit_insn (gen_cpymemhi_bpsi_op (desto, srco, counto, desta, srca, count));\n-\n-  return 1;\n-}\n-\n-/* This is a stpcpy() opcode.  $0 is the destination (MEM:BLK) after\n-   the copy, which should point to the NUL at the end of the string,\n-   $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).\n-   Since our opcode leaves the destination pointing *after* the NUL,\n-   we must emit an adjustment.  */\n-int\n-m32c_expand_movstr(rtx *operands)\n-{\n-  rtx desta, srca;\n-  rtx desto, srco;\n-\n-  desta = XEXP (operands[1], 0);\n-  srca = XEXP (operands[2], 0);\n-\n-  desto = gen_reg_rtx (Pmode);\n-  srco = gen_reg_rtx (Pmode);\n-\n-  if (GET_CODE (desta) != REG\n-      || REGNO (desta) < FIRST_PSEUDO_REGISTER)\n-    desta = copy_to_mode_reg (Pmode, desta);\n-\n-  if (GET_CODE (srca) != REG\n-      || REGNO (srca) < FIRST_PSEUDO_REGISTER)\n-    srca = copy_to_mode_reg (Pmode, srca);\n-\n-  emit_insn (gen_movstr_op (desto, srco, desta, srca));\n-  /* desto ends up being a1, which allows this type of add through MOVA.  */\n-  emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));\n-\n-  return 1;\n-}\n-\n-/* This is a strcmp() opcode.  $0 is the destination (HI) which holds\n-   <=>0 depending on the comparison, $1 is one string (MEM:BLK), and\n-   $2 is the other (MEM:BLK).  We must do the comparison, and then\n-   convert the flags to a signed integer result.  */\n-int\n-m32c_expand_cmpstr(rtx *operands)\n-{\n-  rtx src1a, src2a;\n-\n-  src1a = XEXP (operands[1], 0);\n-  src2a = XEXP (operands[2], 0);\n-\n-  if (GET_CODE (src1a) != REG\n-      || REGNO (src1a) < FIRST_PSEUDO_REGISTER)\n-    src1a = copy_to_mode_reg (Pmode, src1a);\n-\n-  if (GET_CODE (src2a) != REG\n-      || REGNO (src2a) < FIRST_PSEUDO_REGISTER)\n-    src2a = copy_to_mode_reg (Pmode, src2a);\n-\n-  emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));\n-  emit_insn (gen_cond_to_int (operands[0]));\n-\n-  return 1;\n-}\n-\n-\n-typedef rtx (*shift_gen_func)(rtx, rtx, rtx);\n-\n-static shift_gen_func\n-shift_gen_func_for (int mode, int code)\n-{\n-#define GFF(m,c,f) if (mode == m && code == c) return f\n-  GFF(QImode,  ASHIFT,   gen_ashlqi3_i);\n-  GFF(QImode,  ASHIFTRT, gen_ashrqi3_i);\n-  GFF(QImode,  LSHIFTRT, gen_lshrqi3_i);\n-  GFF(HImode,  ASHIFT,   gen_ashlhi3_i);\n-  GFF(HImode,  ASHIFTRT, gen_ashrhi3_i);\n-  GFF(HImode,  LSHIFTRT, gen_lshrhi3_i);\n-  GFF(PSImode, ASHIFT,   gen_ashlpsi3_i);\n-  GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);\n-  GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);\n-  GFF(SImode,  ASHIFT,   TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);\n-  GFF(SImode,  ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);\n-  GFF(SImode,  LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);\n-#undef GFF\n-  gcc_unreachable ();\n-}\n-\n-/* The m32c only has one shift, but it takes a signed count.  GCC\n-   doesn't want this, so we fake it by negating any shift count when\n-   we're pretending to shift the other way.  Also, the shift count is\n-   limited to -8..8.  It's slightly better to use two shifts for 9..15\n-   than to load the count into r1h, so we do that too.  */\n-int\n-m32c_prepare_shift (rtx * operands, int scale, int shift_code)\n-{\n-  machine_mode mode = GET_MODE (operands[0]);\n-  shift_gen_func func = shift_gen_func_for (mode, shift_code);\n-  rtx temp;\n-\n-  if (GET_CODE (operands[2]) == CONST_INT)\n-    {\n-      int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;\n-      int count = INTVAL (operands[2]) * scale;\n-\n-      while (count > maxc)\n-\t{\n-\t  temp = gen_reg_rtx (mode);\n-\t  emit_insn (func (temp, operands[1], GEN_INT (maxc)));\n-\t  operands[1] = temp;\n-\t  count -= maxc;\n-\t}\n-      while (count < -maxc)\n-\t{\n-\t  temp = gen_reg_rtx (mode);\n-\t  emit_insn (func (temp, operands[1], GEN_INT (-maxc)));\n-\t  operands[1] = temp;\n-\t  count += maxc;\n-\t}\n-      emit_insn (func (operands[0], operands[1], GEN_INT (count)));\n-      return 1;\n-    }\n-\n-  temp = gen_reg_rtx (QImode);\n-  if (scale < 0)\n-    /* The pattern has a NEG that corresponds to this. */\n-    emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));\n-  else if (TARGET_A16 && mode == SImode)\n-    /* We do this because the code below may modify this, we don't\n-       want to modify the origin of this value.  */\n-    emit_move_insn (temp, operands[2]);\n-  else\n-    /* We'll only use it for the shift, no point emitting a move.  */\n-    temp = operands[2];\n-\n-  if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)\n-    {\n-      /* The m16c has a limit of -16..16 for SI shifts, even when the\n-\t shift count is in a register.  Since there are so many targets\n-\t of these shifts, it's better to expand the RTL here than to\n-\t call a helper function.\n-\n-\t The resulting code looks something like this:\n-\n-\t\tcmp.b\tr1h,-16\n-\t\tjge.b\t1f\n-\t\tshl.l\t-16,dest\n-\t\tadd.b\tr1h,16\n-\t1f:\tcmp.b\tr1h,16\n-\t\tjle.b\t1f\n-\t\tshl.l\t16,dest\n-\t\tsub.b\tr1h,16\n-\t1f:\tshl.l\tr1h,dest\n-\n-\t We take advantage of the fact that \"negative\" shifts are\n-\t undefined to skip one of the comparisons.  */\n-\n-      rtx count;\n-      rtx tempvar;\n-      rtx_insn *insn;\n-\n-      emit_move_insn (operands[0], operands[1]);\n-\n-      count = temp;\n-      rtx_code_label *label = gen_label_rtx ();\n-      LABEL_NUSES (label) ++;\n-\n-      tempvar = gen_reg_rtx (mode);\n-\n-      if (shift_code == ASHIFT)\n-\t{\n-\t  /* This is a left shift.  We only need check positive counts.  */\n-\t  emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),\n-\t\t\t\t\t  count, GEN_INT (16), label));\n-\t  emit_insn (func (tempvar, operands[0], GEN_INT (8)));\n-\t  emit_insn (func (operands[0], tempvar, GEN_INT (8)));\n-\t  insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));\n-\t  emit_label_after (label, insn);\n-\t}\n-      else\n-\t{\n-\t  /* This is a right shift.  We only need check negative counts.  */\n-\t  emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),\n-\t\t\t\t\t  count, GEN_INT (-16), label));\n-\t  emit_insn (func (tempvar, operands[0], GEN_INT (-8)));\n-\t  emit_insn (func (operands[0], tempvar, GEN_INT (-8)));\n-\t  insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));\n-\t  emit_label_after (label, insn);\n-\t}\n-      operands[1] = operands[0];\n-      emit_insn (func (operands[0], operands[0], count));\n-      return 1;\n-    }\n-\n-  operands[2] = temp;\n-  return 0;\n-}\n-\n-/* The m32c has a limited range of operations that work on PSImode\n-   values; we have to expand to SI, do the math, and truncate back to\n-   PSI.  Yes, this is expensive, but hopefully gcc will learn to avoid\n-   those cases.  */\n-void\n-m32c_expand_neg_mulpsi3 (rtx * operands)\n-{\n-  /* operands: a = b * i */\n-  rtx temp1; /* b as SI */\n-  rtx scale /* i as SI */;\n-  rtx temp2; /* a*b as SI */\n-\n-  temp1 = gen_reg_rtx (SImode);\n-  temp2 = gen_reg_rtx (SImode);\n-  if (GET_CODE (operands[2]) != CONST_INT)\n-    {\n-      scale = gen_reg_rtx (SImode);\n-      emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));\n-    }\n-  else\n-    scale = copy_to_mode_reg (SImode, operands[2]);\n-\n-  emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));\n-  temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);\n-  emit_insn (gen_truncsipsi2 (operands[0], temp2));\n-}\n-\n-/* Pattern Output Functions */\n-\n-int\n-m32c_expand_movcc (rtx *operands)\n-{\n-  rtx rel = operands[1];\n-\n-  if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)\n-    return 1;\n-  if (GET_CODE (operands[2]) != CONST_INT\n-      || GET_CODE (operands[3]) != CONST_INT)\n-    return 1;\n-  if (GET_CODE (rel) == NE)\n-    {\n-      rtx tmp = operands[2];\n-      operands[2] = operands[3];\n-      operands[3] = tmp;\n-      rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));\n-    }\n-\n-  emit_move_insn (operands[0],\n-\t\t  gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),\n-\t\t\t\t\trel,\n-\t\t\t\t\toperands[2],\n-\t\t\t\t\toperands[3]));\n-  return 0;\n-}\n-\n-/* Used for the \"insv\" pattern.  Return nonzero to fail, else done.  */\n-int\n-m32c_expand_insv (rtx *operands)\n-{\n-  rtx op0, src0, p;\n-  int mask;\n-\n-  if (INTVAL (operands[1]) != 1)\n-    return 1;\n-\n-  /* Our insv opcode (bset, bclr) can only insert a one-bit constant.  */\n-  if (GET_CODE (operands[3]) != CONST_INT)\n-    return 1;\n-  if (INTVAL (operands[3]) != 0\n-      && INTVAL (operands[3]) != 1\n-      && INTVAL (operands[3]) != -1)\n-    return 1;\n-\n-  mask = 1 << INTVAL (operands[2]);\n-\n-  op0 = operands[0];\n-  if (GET_CODE (op0) == SUBREG\n-      && SUBREG_BYTE (op0) == 0)\n-    {\n-      rtx sub = SUBREG_REG (op0);\n-      if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)\n-\top0 = sub;\n-    }\n-\n-  if (!can_create_pseudo_p ()\n-      || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))\n-    src0 = op0;\n-  else\n-    {\n-      src0 = gen_reg_rtx (GET_MODE (op0));\n-      emit_move_insn (src0, op0);\n-    }\n-\n-  if (GET_MODE (op0) == HImode\n-      && INTVAL (operands[2]) >= 8\n-      && GET_CODE (op0) == MEM)\n-    {\n-      /* We are little endian.  */\n-      rtx new_mem = gen_rtx_MEM (QImode, plus_constant (Pmode,\n-\t\t\t\t\t\t\tXEXP (op0, 0), 1));\n-      MEM_COPY_ATTRIBUTES (new_mem, op0);\n-      mask >>= 8;\n-    }\n-\n-  /* First, we generate a mask with the correct polarity.  If we are\n-     storing a zero, we want an AND mask, so invert it.  */\n-  if (INTVAL (operands[3]) == 0)\n-    {\n-      /* Storing a zero, use an AND mask */\n-      if (GET_MODE (op0) == HImode)\n-\tmask ^= 0xffff;\n-      else\n-\tmask ^= 0xff;\n-    }\n-  /* Now we need to properly sign-extend the mask in case we need to\n-     fall back to an AND or OR opcode.  */\n-  if (GET_MODE (op0) == HImode)\n-    {\n-      if (mask & 0x8000)\n-\tmask -= 0x10000;\n-    }\n-  else\n-    {\n-      if (mask & 0x80)\n-\tmask -= 0x100;\n-    }\n-\n-  switch (  (INTVAL (operands[3]) ? 4 : 0)\n-\t  + ((GET_MODE (op0) == HImode) ? 2 : 0)\n-\t  + (TARGET_A24 ? 1 : 0))\n-    {\n-    case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;\n-    case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;\n-    case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;\n-    case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;\n-    case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;\n-    case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;\n-    case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;\n-    case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;\n-    default: p = NULL_RTX; break; /* Not reached, but silences a warning.  */\n-    }\n-\n-  emit_insn (p);\n-  return 0;\n-}\n-\n-const char *\n-m32c_scc_pattern(rtx *operands, RTX_CODE code)\n-{\n-  static char buf[30];\n-  if (GET_CODE (operands[0]) == REG\n-      && REGNO (operands[0]) == R0_REGNO)\n-    {\n-      if (code == EQ)\n-\treturn \"stzx\\t#1,#0,r0l\";\n-      if (code == NE)\n-\treturn \"stzx\\t#0,#1,r0l\";\n-    }\n-  sprintf(buf, \"bm%s\\t0,%%h0\\n\\tand.b\\t#1,%%0\", GET_RTX_NAME (code));\n-  return buf;\n-}\n-\n-/* Encode symbol attributes of a SYMBOL_REF into its\n-   SYMBOL_REF_FLAGS. */\n-static void\n-m32c_encode_section_info (tree decl, rtx rtl, int first)\n-{\n-  int extra_flags = 0;\n-\n-  default_encode_section_info (decl, rtl, first);\n-  if (TREE_CODE (decl) == FUNCTION_DECL\n-      && m32c_special_page_vector_p (decl))\n-\n-    extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;\n-\n-  if (extra_flags)\n-    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;\n-}\n-\n-/* Returns TRUE if the current function is a leaf, and thus we can\n-   determine which registers an interrupt function really needs to\n-   save.  The logic below is mostly about finding the insn sequence\n-   that's the function, versus any sequence that might be open for the\n-   current insn.  */\n-static int\n-m32c_leaf_function_p (void)\n-{\n-  int rv;\n-\n-  push_topmost_sequence ();\n-  rv = leaf_function_p ();\n-  pop_topmost_sequence ();\n-  return rv;\n-}\n-\n-/* Returns TRUE if the current function needs to use the ENTER/EXIT\n-   opcodes.  If the function doesn't need the frame base or stack\n-   pointer, it can use the simpler RTS opcode.  */\n-static bool\n-m32c_function_needs_enter (void)\n-{\n-  rtx_insn *insn;\n-  rtx sp = gen_rtx_REG (Pmode, SP_REGNO);\n-  rtx fb = gen_rtx_REG (Pmode, FB_REGNO);\n-\n-  for (insn = get_topmost_sequence ()->first; insn; insn = NEXT_INSN (insn))\n-    if (NONDEBUG_INSN_P (insn))\n-      {\n-\tif (reg_mentioned_p (sp, insn))\n-\t  return true;\n-\tif (reg_mentioned_p (fb, insn))\n-\t  return true;\n-      }\n-  return false;\n-}\n-\n-/* Mark all the subexpressions of the PARALLEL rtx PAR as\n-   frame-related.  Return PAR.\n-\n-   dwarf2out.cc:dwarf2out_frame_debug_expr ignores sub-expressions of a\n-   PARALLEL rtx other than the first if they do not have the\n-   FRAME_RELATED flag set on them.  So this function is handy for\n-   marking up 'enter' instructions.  */\n-static rtx\n-m32c_all_frame_related (rtx par)\n-{\n-  int len = XVECLEN (par, 0);\n-  int i;\n-\n-  for (i = 0; i < len; i++)\n-    F (XVECEXP (par, 0, i));\n-\n-  return par;\n-}\n-\n-/* Emits the prologue.  See the frame layout comment earlier in this\n-   file.  We can reserve up to 256 bytes with the ENTER opcode, beyond\n-   that we manually update sp.  */\n-void\n-m32c_emit_prologue (void)\n-{\n-  int frame_size, extra_frame_size = 0, reg_save_size;\n-  int complex_prologue = 0;\n-\n-  cfun->machine->is_leaf = m32c_leaf_function_p ();\n-  if (interrupt_p (cfun->decl))\n-    {\n-      cfun->machine->is_interrupt = 1;\n-      complex_prologue = 1;\n-    }\n-  else if (bank_switch_p (cfun->decl))\n-    warning (OPT_Wattributes,\n-\t     \"%<bank_switch%> has no effect on non-interrupt functions\");\n-\n-  reg_save_size = m32c_pushm_popm (PP_justcount);\n-\n-  if (interrupt_p (cfun->decl))\n-    {\n-      if (bank_switch_p (cfun->decl))\n-\temit_insn (gen_fset_b ());\n-      else if (cfun->machine->intr_pushm)\n-\temit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));\n-    }\n-\n-  frame_size =\n-    m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;\n-  if (frame_size == 0\n-      && !m32c_function_needs_enter ())\n-    cfun->machine->use_rts = 1;\n-\n-  if (flag_stack_usage_info)\n-    current_function_static_stack_size = frame_size;\n-\n-  if (frame_size > 254)\n-    {\n-      extra_frame_size = frame_size - 254;\n-      frame_size = 254;\n-    }\n-  if (cfun->machine->use_rts == 0)\n-    F (emit_insn (m32c_all_frame_related\n-\t\t  (TARGET_A16\n-\t\t   ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))\n-\t\t   : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));\n-\n-  if (extra_frame_size)\n-    {\n-      complex_prologue = 1;\n-      if (TARGET_A16)\n-\tF (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),\n-\t\t\t\t  gen_rtx_REG (HImode, SP_REGNO),\n-\t\t\t\t  GEN_INT (-extra_frame_size))));\n-      else\n-\tF (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),\n-\t\t\t\t   gen_rtx_REG (PSImode, SP_REGNO),\n-\t\t\t\t   GEN_INT (-extra_frame_size))));\n-    }\n-\n-  complex_prologue += m32c_pushm_popm (PP_pushm);\n-\n-  /* This just emits a comment into the .s file for debugging.  */\n-  if (complex_prologue)\n-    emit_insn (gen_prologue_end ());\n-}\n-\n-/* Likewise, for the epilogue.  The only exception is that, for\n-   interrupts, we must manually unwind the frame as the REIT opcode\n-   doesn't do that.  */\n-void\n-m32c_emit_epilogue (void)\n-{\n-  int popm_count = m32c_pushm_popm (PP_justcount);\n-\n-  /* This just emits a comment into the .s file for debugging.  */\n-  if (popm_count > 0 || cfun->machine->is_interrupt)\n-    emit_insn (gen_epilogue_start ());\n-\n-  if (popm_count > 0)\n-    m32c_pushm_popm (PP_popm);\n-\n-  if (cfun->machine->is_interrupt)\n-    {\n-      machine_mode spmode = TARGET_A16 ? HImode : PSImode;\n-\n-      /* REIT clears B flag and restores $fp for us, but we still\n-\t have to fix up the stack.  USE_RTS just means we didn't\n-\t emit ENTER.  */\n-      if (!cfun->machine->use_rts)\n-\t{\n-\t  emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),\n-\t\t\t  gen_rtx_REG (spmode, FP_REGNO));\n-\t  emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),\n-\t\t\t  gen_rtx_REG (spmode, A0_REGNO));\n-\t  /* We can't just add this to the POPM because it would be in\n-\t     the wrong order, and wouldn't fix the stack if we're bank\n-\t     switching.  */\n-\t  if (TARGET_A16)\n-\t    emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));\n-\t  else\n-\t    emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));\n-\t}\n-      if (!bank_switch_p (cfun->decl) && cfun->machine->intr_pushm)\n-\temit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));\n-\n-      /* The FREIT (Fast REturn from InTerrupt) instruction should be\n-         generated only for M32C/M32CM targets (generate the REIT\n-         instruction otherwise).  */\n-      if (fast_interrupt_p (cfun->decl))\n-        {\n-          /* Check if fast_attribute is set for M32C or M32CM.  */\n-          if (TARGET_A24)\n-            {\n-              emit_jump_insn (gen_epilogue_freit ());\n-            }\n-          /* If fast_interrupt attribute is set for an R8C or M16C\n-             target ignore this attribute and generated REIT\n-             instruction.  */\n-          else\n-\t    {\n-\t      warning (OPT_Wattributes,\n-\t\t       \"%<fast_interrupt%> attribute directive ignored\");\n-\t      emit_jump_insn (gen_epilogue_reit_16 ());\n-\t    }\n-        }\n-      else if (TARGET_A16)\n-\temit_jump_insn (gen_epilogue_reit_16 ());\n-      else\n-\temit_jump_insn (gen_epilogue_reit_24 ());\n-    }\n-  else if (cfun->machine->use_rts)\n-    emit_jump_insn (gen_epilogue_rts ());\n-  else if (TARGET_A16)\n-    emit_jump_insn (gen_epilogue_exitd_16 ());\n-  else\n-    emit_jump_insn (gen_epilogue_exitd_24 ());\n-}\n-\n-void\n-m32c_emit_eh_epilogue (rtx ret_addr)\n-{\n-  /* R0[R2] has the stack adjustment.  R1[R3] has the address to\n-     return to.  We have to fudge the stack, pop everything, pop SP\n-     (fudged), and return (fudged).  This is actually easier to do in\n-     assembler, so punt to libgcc.  */\n-  emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));\n-  /*  emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */\n-}\n-\n-/* Indicate which flags must be properly set for a given conditional.  */\n-static int\n-flags_needed_for_conditional (rtx cond)\n-{\n-  switch (GET_CODE (cond))\n-    {\n-    case LE:\n-    case GT:\n-      return FLAGS_OSZ;\n-    case LEU:\n-    case GTU:\n-      return FLAGS_ZC;\n-    case LT:\n-    case GE:\n-      return FLAGS_OS;\n-    case LTU:\n-    case GEU:\n-      return FLAGS_C;\n-    case EQ:\n-    case NE:\n-      return FLAGS_Z;\n-    default:\n-      return FLAGS_N;\n-    }\n-}\n-\n-#define DEBUG_CMP 0\n-\n-/* Returns true if a compare insn is redundant because it would only\n-   set flags that are already set correctly.  */\n-static bool\n-m32c_compare_redundant (rtx_insn *cmp, rtx *operands)\n-{\n-  int flags_needed;\n-  int pflags;\n-  rtx_insn *prev;\n-  rtx pp, next;\n-  rtx op0, op1;\n-#if DEBUG_CMP\n-  int prev_icode, i;\n-#endif\n-\n-  op0 = operands[0];\n-  op1 = operands[1];\n-\n-#if DEBUG_CMP\n-  fprintf(stderr, \"\\n\\033[32mm32c_compare_redundant\\033[0m\\n\");\n-  debug_rtx(cmp);\n-  for (i=0; i<2; i++)\n-    {\n-      fprintf(stderr, \"operands[%d] = \", i);\n-      debug_rtx(operands[i]);\n-    }\n-#endif\n-\n-  next = next_nonnote_insn (cmp);\n-  if (!next || !INSN_P (next))\n-    {\n-#if DEBUG_CMP\n-      fprintf(stderr, \"compare not followed by insn\\n\");\n-      debug_rtx(next);\n-#endif\n-      return false;\n-    }\n-  if (GET_CODE (PATTERN (next)) == SET\n-      && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)\n-    {\n-      next = XEXP (XEXP (PATTERN (next), 1), 0);\n-    }\n-  else if (GET_CODE (PATTERN (next)) == SET)\n-    {\n-      /* If this is a conditional, flags_needed will be something\n-\t other than FLAGS_N, which we test below.  */\n-      next = XEXP (PATTERN (next), 1);\n-    }\n-  else\n-    {\n-#if DEBUG_CMP\n-      fprintf(stderr, \"compare not followed by conditional\\n\");\n-      debug_rtx(next);\n-#endif\n-      return false;\n-    }\n-#if DEBUG_CMP\n-  fprintf(stderr, \"conditional is: \");\n-  debug_rtx(next);\n-#endif\n-\n-  flags_needed = flags_needed_for_conditional (next);\n-  if (flags_needed == FLAGS_N)\n-    {\n-#if DEBUG_CMP\n-      fprintf(stderr, \"compare not followed by conditional\\n\");\n-      debug_rtx(next);\n-#endif\n-      return false;\n-    }\n-\n-  /* Compare doesn't set overflow and carry the same way that\n-     arithmetic instructions do, so we can't replace those.  */\n-  if (flags_needed & FLAGS_OC)\n-    return false;\n-\n-  prev = cmp;\n-  do {\n-    prev = prev_nonnote_insn (prev);\n-    if (!prev)\n-      {\n-#if DEBUG_CMP\n-\tfprintf(stderr, \"No previous insn.\\n\");\n-#endif\n-\treturn false;\n-      }\n-    if (!INSN_P (prev))\n-      {\n-#if DEBUG_CMP\n-\tfprintf(stderr, \"Previous insn is a non-insn.\\n\");\n-#endif\n-\treturn false;\n-      }\n-    pp = PATTERN (prev);\n-    if (GET_CODE (pp) != SET)\n-      {\n-#if DEBUG_CMP\n-\tfprintf(stderr, \"Previous insn is not a SET.\\n\");\n-#endif\n-\treturn false;\n-      }\n-    pflags = get_attr_flags (prev);\n-\n-    /* Looking up attributes of previous insns corrupted the recog\n-       tables.  */\n-    INSN_UID (cmp) = -1;\n-    recog (PATTERN (cmp), cmp, 0);\n-\n-    if (pflags == FLAGS_N\n-\t&& reg_mentioned_p (op0, pp))\n-      {\n-#if DEBUG_CMP\n-\tfprintf(stderr, \"intermediate non-flags insn uses op:\\n\");\n-\tdebug_rtx(prev);\n-#endif\n-\treturn false;\n-      }\n-\n-    /* Check for comparisons against memory - between volatiles and\n-       aliases, we just can't risk this one.  */\n-    if (GET_CODE (operands[0]) == MEM\n-\t|| GET_CODE (operands[0]) == MEM)\n-      {\n-#if DEBUG_CMP\n-\tfprintf(stderr, \"comparisons with memory:\\n\");\n-\tdebug_rtx(prev);\n-#endif\n-\treturn false;\n-      }\n-\n-    /* Check for PREV changing a register that's used to compute a\n-       value in CMP, even if it doesn't otherwise change flags.  */\n-    if (GET_CODE (operands[0]) == REG\n-\t&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))\n-      {\n-#if DEBUG_CMP\n-\tfprintf(stderr, \"sub-value affected, op0:\\n\");\n-\tdebug_rtx(prev);\n-#endif\n-\treturn false;\n-      }\n-    if (GET_CODE (operands[1]) == REG\n-\t&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))\n-      {\n-#if DEBUG_CMP\n-\tfprintf(stderr, \"sub-value affected, op1:\\n\");\n-\tdebug_rtx(prev);\n-#endif\n-\treturn false;\n-      }\n-\n-  } while (pflags == FLAGS_N);\n-#if DEBUG_CMP\n-  fprintf(stderr, \"previous flag-setting insn:\\n\");\n-  debug_rtx(prev);\n-  debug_rtx(pp);\n-#endif\n-\n-  if (GET_CODE (pp) == SET\n-      && GET_CODE (XEXP (pp, 0)) == REG\n-      && REGNO (XEXP (pp, 0)) == FLG_REGNO\n-      && GET_CODE (XEXP (pp, 1)) == COMPARE)\n-    {\n-      /* Adjacent cbranches must have the same operands to be\n-\t redundant.  */\n-      rtx pop0 = XEXP (XEXP (pp, 1), 0);\n-      rtx pop1 = XEXP (XEXP (pp, 1), 1);\n-#if DEBUG_CMP\n-      fprintf(stderr, \"adjacent cbranches\\n\");\n-      debug_rtx(pop0);\n-      debug_rtx(pop1);\n-#endif\n-      if (rtx_equal_p (op0, pop0)\n-\t  && rtx_equal_p (op1, pop1))\n-\treturn true;\n-#if DEBUG_CMP\n-      fprintf(stderr, \"prev cmp not same\\n\");\n-#endif\n-      return false;\n-    }\n-\n-  /* Else the previous insn must be a SET, with either the source or\n-     dest equal to operands[0], and operands[1] must be zero.  */\n-\n-  if (!rtx_equal_p (op1, const0_rtx))\n-    {\n-#if DEBUG_CMP\n-      fprintf(stderr, \"operands[1] not const0_rtx\\n\");\n-#endif\n-      return false;\n-    }\n-  if (GET_CODE (pp) != SET)\n-    {\n-#if DEBUG_CMP\n-      fprintf (stderr, \"pp not set\\n\");\n-#endif\n-      return false;\n-    }\n-  if (!rtx_equal_p (op0, SET_SRC (pp))\n-      && !rtx_equal_p (op0, SET_DEST (pp)))\n-    {\n-#if DEBUG_CMP\n-      fprintf(stderr, \"operands[0] not found in set\\n\");\n-#endif\n-      return false;\n-    }\n-\n-#if DEBUG_CMP\n-  fprintf(stderr, \"cmp flags %x prev flags %x\\n\", flags_needed, pflags);\n-#endif\n-  if ((pflags & flags_needed) == flags_needed)\n-    return true;\n-\n-  return false;\n-}\n-\n-/* Return the pattern for a compare.  This will be commented out if\n-   the compare is redundant, else a normal pattern is returned.  Thus,\n-   the assembler output says where the compare would have been.  */\n-char *\n-m32c_output_compare (rtx_insn *insn, rtx *operands)\n-{\n-  static char templ[] = \";cmp.b\\t%1,%0\";\n-  /*                             ^ 5  */\n-\n-  templ[5] = \" bwll\"[GET_MODE_SIZE(GET_MODE(operands[0]))];\n-  if (m32c_compare_redundant (insn, operands))\n-    {\n-#if DEBUG_CMP\n-      fprintf(stderr, \"cbranch: cmp not needed\\n\");\n-#endif\n-      return templ;\n-    }\n-\n-#if DEBUG_CMP\n-  fprintf(stderr, \"cbranch: cmp needed: `%s'\\n\", templ + 1);\n-#endif\n-  return templ + 1;\n-}\n-\n-#undef TARGET_ENCODE_SECTION_INFO\n-#define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info\n-\n-/* If the frame pointer isn't used, we detect it manually.  But the\n-   stack pointer doesn't have as flexible addressing as the frame\n-   pointer, so we always assume we have it.  */\n-\n-#undef TARGET_FRAME_POINTER_REQUIRED\n-#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true\n-\n-#undef TARGET_HARD_REGNO_NREGS\n-#define TARGET_HARD_REGNO_NREGS m32c_hard_regno_nregs\n-#undef TARGET_HARD_REGNO_MODE_OK\n-#define TARGET_HARD_REGNO_MODE_OK m32c_hard_regno_mode_ok\n-#undef TARGET_MODES_TIEABLE_P\n-#define TARGET_MODES_TIEABLE_P m32c_modes_tieable_p\n-\n-#undef TARGET_CAN_CHANGE_MODE_CLASS\n-#define TARGET_CAN_CHANGE_MODE_CLASS m32c_can_change_mode_class\n-\n-#undef TARGET_DOCUMENTATION_NAME\n-#define TARGET_DOCUMENTATION_NAME \"M32C\"\n-\n-/* The Global `targetm' Variable. */\n-\n-struct gcc_target targetm = TARGET_INITIALIZER;\n-\n-#include \"gt-m32c.h\"\ndiff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h\ndeleted file mode 100644\nindex 5c87b65a04a..00000000000\n--- a/gcc/config/m32c/m32c.h\n+++ /dev/null\n@@ -1,635 +0,0 @@\n-/* Target Definitions for R8C/M16C/M32C\n-   Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   You should have received a copy of the GNU General Public License\n-   along with GCC; see the file COPYING3.  If not see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-#ifndef GCC_M32C_H\n-#define GCC_M32C_H\n-\n-/* Controlling the Compilation Driver, `gcc'.  */\n-\n-#undef  STARTFILE_SPEC\n-#define STARTFILE_SPEC \"crt0.o%s crtbegin.o%s\"\n-\n-#undef  ENDFILE_SPEC\n-#define ENDFILE_SPEC \"crtend.o%s crtn.o%s\"\n-\n-#undef  LINK_SPEC\n-#define LINK_SPEC \"%{h*} %{v:-V} \\\n-\t\t   %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}\"\n-\n-/* There are four CPU series we support, but they basically break down\n-   into two families - the R8C/M16C families, with 16-bit address\n-   registers and one set of opcodes, and the M32CM/M32C group, with\n-   24-bit address registers and a different set of opcodes.  The\n-   assembler doesn't care except for which opcode set is needed; the\n-   big difference is in the memory maps, which we cover in\n-   LIB_SPEC.  */\n-\n-#undef  ASM_SPEC\n-#define ASM_SPEC \"\\\n-%{mcpu=r8c:--m16c} \\\n-%{mcpu=m16c:--m16c} \\\n-%{mcpu=m32cm:--m32c} \\\n-%{mcpu=m32c:--m32c} \"\n-\n-/* The default is R8C hardware.  We support a simulator, which has its\n-   own libgloss and link map, plus one default link map for each chip\n-   family.  Most of the logic here is making sure we do the right\n-   thing when no CPU is specified, which defaults to R8C.  */\n-#undef  LIB_SPEC\n-#define LIB_SPEC \"-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \\\n-%{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \\\n-       %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \\\n-%{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \\\n-\t       %{mcpu=m32cm:%Tm32cm.ld} \\\n-\t       %{mcpu=m32c:%Tm32c.ld} \\\n-\t       %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \\\n-\"\n-\n-/* Run-time Target Specification */\n-\n-/* Nothing unusual here.  */\n-#define TARGET_CPU_CPP_BUILTINS() \\\n-  { \\\n-    builtin_assert (\"cpu=m32c\"); \\\n-    builtin_assert (\"machine=m32c\"); \\\n-    builtin_define (\"__m32c__=1\"); \\\n-    if (TARGET_R8C) \\\n-      builtin_define (\"__r8c_cpu__=1\"); \\\n-    if (TARGET_M16C) \\\n-      builtin_define (\"__m16c_cpu__=1\"); \\\n-    if (TARGET_M32CM) \\\n-      builtin_define (\"__m32cm_cpu__=1\"); \\\n-    if (TARGET_M32C) \\\n-      builtin_define (\"__m32c_cpu__=1\"); \\\n-  }\n-\n-/* The pragma handlers need to know if we've started processing\n-   functions yet, as the memregs pragma should only be given at the\n-   beginning of the file.  This variable starts off TRUE and later\n-   becomes FALSE.  */\n-extern int ok_to_change_target_memregs;\n-\n-/* TARGET_CPU is a multi-way option set in m32c.opt.  While we could\n-   use enums or defines for this, this and m32c.opt are the only\n-   places that know (or care) what values are being used.  */\n-#define TARGET_R8C\t(target_cpu == 'r')\n-#define TARGET_M16C\t(target_cpu == '6')\n-#define TARGET_M32CM\t(target_cpu == 'm')\n-#define TARGET_M32C\t(target_cpu == '3')\n-\n-/* Address register sizes.  Warning: these are used all over the place\n-   to select between the two CPU families in general.  */\n-#define TARGET_A16\t(TARGET_R8C || TARGET_M16C)\n-#define TARGET_A24\t(TARGET_M32CM || TARGET_M32C)\n-\n-/* Defining data structures for per-function information */\n-\n-typedef struct GTY (()) machine_function\n-{\n-  /* How much we adjust the stack when returning from an exception\n-     handler.  */\n-  rtx eh_stack_adjust;\n-\n-  /* TRUE if the current function is an interrupt handler.  */\n-  int is_interrupt;\n-\n-  /* TRUE if the current function is a leaf function.  Currently, this\n-     only affects saving $a0 in interrupt functions.  */\n-  int is_leaf;\n-\n-  /* Bitmask that keeps track of which registers are used in an\n-     interrupt function, so we know which ones need to be saved and\n-     restored.  */\n-  int intr_pushm;\n-  /* Likewise, one element for each memreg that needs to be saved.  */\n-  char intr_pushmem[16];\n-\n-  /* TRUE if the current function can use a simple RTS to return, instead\n-     of the longer ENTER/EXIT pair.  */\n-  int use_rts;\n-}\n-machine_function;\n-\n-#define INIT_EXPANDERS m32c_init_expanders ()\n-\n-/* Storage Layout */\n-\n-#define BITS_BIG_ENDIAN 0\n-#define BYTES_BIG_ENDIAN 0\n-#define WORDS_BIG_ENDIAN 0\n-\n-/* We can do QI, HI, and SI operations pretty much equally well, but\n-   GCC expects us to have a \"native\" format, so we pick the one that\n-   matches \"int\".  Pointers are 16 bits for R8C/M16C (when TARGET_A16\n-   is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but\n-   24-bit pointers are stored in 32-bit words.  */\n-#define UNITS_PER_WORD 2\n-#define POINTER_SIZE (TARGET_A16 ? 16 : 32)\n-#define POINTERS_EXTEND_UNSIGNED 1\n-/* We have a problem with libgcc2.  It only defines two versions of\n-   each function, one for \"int\" and one for \"long long\".  Ie it assumes\n-   that \"sizeof (int) == sizeof (long)\".  For the M32C this is not true\n-   and we need a third set of functions.  We explicitly define\n-   LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting\n-   to get the SI and DI versions from the libgcc2.c sources, and we\n-   provide our own set of HI functions in m32c-lib2.c, which is why this\n-   definition is surrounded by #ifndef..#endif.  */\n-#ifndef LIBGCC2_UNITS_PER_WORD\n-#define LIBGCC2_UNITS_PER_WORD 4\n-#endif\n-\n-/* These match the alignment enforced by the two types of stack operations.  */\n-#define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)\n-#define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)\n-\n-/* We do this because we care more about space than about speed.  For\n-   the chips with 16-bit busses, we could set these to 16 if\n-   desired.  */\n-#define FUNCTION_BOUNDARY 8\n-#define BIGGEST_ALIGNMENT 8\n-\n-/* Since we have a maximum structure alignment of 8 there\n-   is no need to enforce any alignment of bitfield types.  */\n-#undef  PCC_BITFIELD_TYPE_MATTERS\n-#define PCC_BITFIELD_TYPE_MATTERS 0\n-\n-#define STRICT_ALIGNMENT 0\n-#define SLOW_BYTE_ACCESS 1\n-\n-/* Layout of Source Language Data Types */\n-\n-#define INT_TYPE_SIZE 16\n-#define SHORT_TYPE_SIZE 16\n-#define LONG_TYPE_SIZE 32\n-#define LONG_LONG_TYPE_SIZE 64\n-\n-#define DEFAULT_SIGNED_CHAR 1\n-\n-#undef PTRDIFF_TYPE\n-#define PTRDIFF_TYPE (TARGET_A16 ? \"int\" : \"long int\")\n-\n-#undef UINTPTR_TYPE\n-#define UINTPTR_TYPE (TARGET_A16 ? \"unsigned int\" : \"long unsigned int\")\n-\n-#undef  SIZE_TYPE\n-#define SIZE_TYPE \"unsigned int\"\n-\n-#undef  WCHAR_TYPE\n-#define WCHAR_TYPE \"long int\"\n-\n-#undef  WCHAR_TYPE_SIZE\n-#define WCHAR_TYPE_SIZE 32\n-\n-/* REGISTER USAGE */\n-\n-/* Register Basics */\n-\n-/* Register layout:\n-\n-        [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)\n-        [--------]  $r2  (16 bits)\n-        [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)\n-        [--------]  $r3  (16 bits)\n-   [---][--------]  $a0  (might be 24 bits)\n-   [---][--------]  $a1  (might be 24 bits)\n-   [---][--------]  $sb  (might be 24 bits)\n-   [---][--------]  $fb  (might be 24 bits)\n-   [---][--------]  $sp  (might be 24 bits)\n-   [-------------]  $pc  (20 or 24 bits)\n-             [---]  $flg (CPU flags)\n-   [---][--------]  $argp (virtual)\n-        [--------]  $mem0 (all 16 bits)\n-          . . .\n-        [--------]  $mem14\n-*/\n-\n-#define FIRST_PSEUDO_REGISTER   20\n-\n-/* Note that these two tables are modified based on which CPU family\n-   you select; see m32c_conditional_register_usage for details.  */\n-\n-/* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */\n-#define FIXED_REGISTERS     { 0, 0, 0, 0, \\\n-\t\t\t      0, 0, 1, 0, \\\n-\t\t\t      1, 1, 0, 1, \\\n-\t\t\t      0, 0, 0, 0, 0, 0, 0, 0 }\n-#define CALL_USED_REGISTERS { 1, 1, 1, 1, \\\n-\t\t\t      1, 1, 1, 0, \\\n-\t\t\t      1, 1, 1, 1, \\\n-\t\t\t      1, 1, 1, 1, 1, 1, 1, 1 }\n-\n-/* The *_REGNO theme matches m32c.md and most register number\n-   arguments; the PC_REGNUM is the odd one out.  */\n-#ifndef PC_REGNO\n-#define PC_REGNO 9\n-#endif\n-#define PC_REGNUM PC_REGNO\n-\n-/* Order of Allocation of Registers */\n-\n-#define REG_ALLOC_ORDER { \\\n-\t0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \\\n-        12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */\t\\\n-\t6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }\n-\n-/* How Values Fit in Registers */\n-\n-#define AVOID_CCMODE_COPIES\n-\n-/* Register Classes */\n-\n-/* Most registers are special purpose in some form or another, so this\n-   table is pretty big.  Class names are used for constraints also;\n-   for example the HL_REGS class (HL below) is \"Rhl\" in the md files.\n-   See m32c_reg_class_from_constraint for the mapping.  There's some\n-   duplication so that we can better isolate the reason for using\n-   constraints in the md files from the actual registers used; for\n-   example we may want to exclude a1a0 from SI_REGS in the future,\n-   without precluding their use as HImode registers.  */\n-\n-/* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */\n-/*       mmPAR */\n-#define REG_CLASS_CONTENTS \\\n-{ { 0x00000000 }, /* NO */\\\n-  { 0x00000100 }, /* SP  - sp */\\\n-  { 0x00000080 }, /* FB  - fb */\\\n-  { 0x00000040 }, /* SB  - sb */\\\n-  { 0x000001c0 }, /* CR  - sb fb sp */\\\n-  { 0x00000001 }, /* R0  - r0 */\\\n-  { 0x00000004 }, /* R1  - r1 */\\\n-  { 0x00000002 }, /* R2  - r2 */\\\n-  { 0x00000008 }, /* R3  - r3 */\\\n-  { 0x00000003 }, /* R02 - r0r2 */\\\n-  { 0x0000000c }, /* R13 - r1r3 */\\\n-  { 0x00000005 }, /* HL  - r0 r1 */\\\n-  { 0x0000000a }, /* R23 - r2 r3 */\\\n-  { 0x0000000f }, /* R03 - r0r2 r1r3 */\\\n-  { 0x00000010 }, /* A0  - a0 */\\\n-  { 0x00000020 }, /* A1  - a1 */\\\n-  { 0x00000030 }, /* A   - a0 a1 */\\\n-  { 0x000000f0 }, /* AD  - a0 a1 sb fp */\\\n-  { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\\\n-  { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \\\n-  { 0x0000003f }, /* RA  - r0 r1 r2 r3 a0 a1 */\\\n-  { 0x0000007f }, /* GENERAL */\\\n-  { 0x00000400 }, /* FLG */\\\n-  { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\\\n-  { 0x000ff000 }, /* MEM */\\\n-  { 0x000ff003 }, /* R02_A_MEM */\\\n-  { 0x000ff005 }, /* A_HL_MEM */\\\n-  { 0x000ff00c }, /* R1_R3_A_MEM */\\\n-  { 0x000ff00f }, /* R03_MEM */\\\n-  { 0x000ff03f }, /* A_HI_MEM */\\\n-  { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\\\n-  { 0x000ff5ff }, /* ALL */\\\n-}\n-\n-#define QI_REGS HL_REGS\n-#define HI_REGS RA_REGS\n-#define SI_REGS R03_REGS\n-#define DI_REGS R03_REGS\n-\n-enum reg_class\n-{\n-  NO_REGS,\n-  SP_REGS,\n-  FB_REGS,\n-  SB_REGS,\n-  CR_REGS,\n-  R0_REGS,\n-  R1_REGS,\n-  R2_REGS,\n-  R3_REGS,\n-  R02_REGS,\n-  R13_REGS,\n-  HL_REGS,\n-  R23_REGS,\n-  R03_REGS,\n-  A0_REGS,\n-  A1_REGS,\n-  A_REGS,\n-  AD_REGS,\n-  PS_REGS,\n-  R02A_REGS,\n-  RA_REGS,\n-  GENERAL_REGS,\n-  FLG_REGS,\n-  HC_REGS,\n-  MEM_REGS,\n-  R02_A_MEM_REGS,\n-  A_HL_MEM_REGS,\n-  R1_R3_A_MEM_REGS,\n-  R03_MEM_REGS,\n-  A_HI_MEM_REGS,\n-  A_AD_CR_MEM_SI_REGS,\n-  ALL_REGS,\n-  LIM_REG_CLASSES\n-};\n-\n-#define N_REG_CLASSES LIM_REG_CLASSES\n-\n-#define REG_CLASS_NAMES {\\\n-\"NO_REGS\", \\\n-\"SP_REGS\", \\\n-\"FB_REGS\", \\\n-\"SB_REGS\", \\\n-\"CR_REGS\", \\\n-\"R0_REGS\", \\\n-\"R1_REGS\", \\\n-\"R2_REGS\", \\\n-\"R3_REGS\", \\\n-\"R02_REGS\", \\\n-\"R13_REGS\", \\\n-\"HL_REGS\", \\\n-\"R23_REGS\", \\\n-\"R03_REGS\", \\\n-\"A0_REGS\", \\\n-\"A1_REGS\", \\\n-\"A_REGS\", \\\n-\"AD_REGS\", \\\n-\"PS_REGS\", \\\n-\"R02A_REGS\", \\\n-\"RA_REGS\", \\\n-\"GENERAL_REGS\", \\\n-\"FLG_REGS\", \\\n-\"HC_REGS\", \\\n-\"MEM_REGS\", \\\n-\"R02_A_MEM_REGS\", \\\n-\"A_HL_MEM_REGS\", \\\n-\"R1_R3_A_MEM_REGS\", \\\n-\"R03_MEM_REGS\", \\\n-\"A_HI_MEM_REGS\", \\\n-\"A_AD_CR_MEM_SI_REGS\", \\\n-\"ALL_REGS\", \\\n-}\n-\n-#define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)\n-\n-/* We support simple displacements off address registers, nothing else.  */\n-#define BASE_REG_CLASS A_REGS\n-#define INDEX_REG_CLASS NO_REGS\n-\n-/* We primarily use the new \"long\" constraint names, with the initial\n-   letter classifying the constraint type and following letters\n-   specifying which.  The types are:\n-\n-   I - integer values\n-   R - register classes\n-   S - memory references (M was used)\n-   A - addresses (currently unused)\n-*/\n-\n-#define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)\n-#define REGNO_OK_FOR_INDEX_P(NUM) 0\n-\n-#define LIMIT_RELOAD_CLASS(MODE,CLASS) \\\n-  (enum reg_class) m32c_limit_reload_class (MODE, CLASS)\n-\n-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \\\n-  (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)\n-\n-#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true\n-\n-/* STACK AND CALLING */\n-\n-/* Frame Layout */\n-\n-/* Standard push/pop stack, no surprises here.  */\n-\n-#define STACK_GROWS_DOWNWARD 1\n-#define STACK_PUSH_CODE PRE_DEC\n-#define FRAME_GROWS_DOWNWARD 1\n-\n-#define FIRST_PARM_OFFSET(F) 0\n-\n-#define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)\n-\n-#define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()\n-#define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)\n-\n-/* Exception Handling Support */\n-\n-#define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)\n-#define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()\n-\n-/* Registers That Address the Stack Frame */\n-\n-#ifndef FP_REGNO\n-#define FP_REGNO 7\n-#endif\n-#ifndef SP_REGNO\n-#define SP_REGNO 8\n-#endif\n-#define AP_REGNO 11\n-\n-#define STACK_POINTER_REGNUM\tSP_REGNO\n-#define FRAME_POINTER_REGNUM\tFP_REGNO\n-#define ARG_POINTER_REGNUM\tAP_REGNO\n-\n-/* The static chain must be pointer-capable.  */\n-#define STATIC_CHAIN_REGNUM A0_REGNO\n-\n-#define DWARF_FRAME_REGISTERS 20\n-#define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)\n-#define DEBUGGER_REGNO(N) m32c_dwarf_frame_regnum (N)\n-\n-#undef ASM_PREFERRED_EH_DATA_FORMAT\n-/* This is the same as the default in practice, except that by making\n-   it explicit we tell binutils what size pointers to use.  */\n-#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \\\n-  (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)\n-\n-/* Eliminating Frame Pointer and Arg Pointer */\n-\n-#define ELIMINABLE_REGS \\\n-  {{AP_REGNO, SP_REGNO}, \\\n-   {AP_REGNO, FB_REGNO}, \\\n-   {FB_REGNO, SP_REGNO}}\n-\n-#define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \\\n-\t(VAR) = m32c_initial_elimination_offset(FROM,TO)\n-\n-/* Passing Function Arguments on the Stack */\n-\n-#define PUSH_ROUNDING(N) m32c_push_rounding (N)\n-#define CALL_POPS_ARGS(C) 0\n-\n-/* Passing Arguments in Registers */\n-\n-typedef struct m32c_cumulative_args\n-{\n-  /* For address of return value buffer (structures are returned by\n-     passing the address of a buffer as an invisible first argument.\n-     This identifies it).  If set, the current parameter will be put\n-     on the stack, regardless of type.  */\n-  int force_mem;\n-  /* First parm is 1, parm 0 is hidden pointer for returning\n-     aggregates.  */\n-  int parm_num;\n-} m32c_cumulative_args;\n-\n-#define CUMULATIVE_ARGS m32c_cumulative_args\n-#define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \\\n-\tm32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)\n-#define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)\n-\n-/* How Large Values Are Returned */\n-\n-#define DEFAULT_PCC_STRUCT_RETURN 1\n-\n-/* Function Entry and Exit */\n-\n-#define EXIT_IGNORE_STACK 0\n-#define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)\n-#define EH_USES(REGNO) 0\t/* FIXME */\n-\n-/* Generating Code for Profiling */\n-\n-#define FUNCTION_PROFILER(FILE,LABELNO)\n-\n-/* Implementing the Varargs Macros */\n-\n-/* Trampolines for Nested Functions */\n-\n-#define TRAMPOLINE_SIZE m32c_trampoline_size ()\n-#define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()\n-\n-/* Addressing Modes */\n-\n-#define HAVE_PRE_DECREMENT 1\n-#define HAVE_POST_INCREMENT 1\n-#define MAX_REGS_PER_ADDRESS 1\n-\n-/* This is passed to the macros below, so that they can be implemented\n-   in m32c.cc.  */\n-#ifdef REG_OK_STRICT\n-#define REG_OK_STRICT_V 1\n-#else\n-#define REG_OK_STRICT_V 0\n-#endif\n-\n-#define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)\n-#define REG_OK_FOR_INDEX_P(X) 0\n-\n-/* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */\n-\n-#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \\\n-\tif (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \\\n-\t  goto WIN;\n-\n-/* Address spaces.  */\n-#define ADDR_SPACE_FAR\t1\n-\n-\n-/* Condition Code Status */\n-\n-#define REVERSIBLE_CC_MODE(MODE) 1\n-\n-/* Dividing the Output into Sections (Texts, Data, ...) */\n-\n-#define TEXT_SECTION_ASM_OP \".text\"\n-#define DATA_SECTION_ASM_OP \".data\"\n-#define BSS_SECTION_ASM_OP \".bss\"\n-\n-#define CTOR_LIST_BEGIN\n-#define CTOR_LIST_END\n-#define DTOR_LIST_BEGIN\n-#define DTOR_LIST_END\n-#define CTORS_SECTION_ASM_OP \"\\t.section\\t.init_array,\\\"aw\\\",%init_array\"\n-#define DTORS_SECTION_ASM_OP \"\\t.section\\t.fini_array,\\\"aw\\\",%fini_array\"\n-#define INIT_ARRAY_SECTION_ASM_OP \"\\t.section\\t.init_array,\\\"aw\\\",%init_array\"\n-#define FINI_ARRAY_SECTION_ASM_OP \"\\t.section\\t.fini_array,\\\"aw\\\",%fini_array\"\n-\n-/* The Overall Framework of an Assembler File */\n-\n-#define ASM_COMMENT_START \";\"\n-#define ASM_APP_ON \"\"\n-#define ASM_APP_OFF \"\"\n-\n-/* Output and Generation of Labels */\n-\n-#define GLOBAL_ASM_OP \"\\t.global\\t\"\n-\n-/* Output of Assembler Instructions */\n-\n-#define REGISTER_NAMES {\t\\\n-  \"r0\", \"r2\", \"r1\", \"r3\", \\\n-  \"a0\", \"a1\", \"sb\", \"fb\", \"sp\", \\\n-  \"pc\", \"flg\", \"argp\", \\\n-  \"mem0\",  \"mem2\",  \"mem4\",  \"mem6\",  \"mem8\",  \"mem10\",  \"mem12\",  \"mem14\", \\\n-}\n-\n-#define ADDITIONAL_REGISTER_NAMES { \\\n-  {\"r0l\", 0}, \\\n-  {\"r1l\", 2}, \\\n-  {\"r0r2\", 0}, \\\n-  {\"r1r3\", 2}, \\\n-  {\"a0a1\", 4}, \\\n-  {\"r0r2r1r3\", 0} }\n-\n-#undef USER_LABEL_PREFIX\n-#define USER_LABEL_PREFIX \"_\"\n-\n-#define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)\n-#define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)\n-\n-#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \\\n-\tm32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)\n-\n-#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \\\n-\tm32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)\n-\n-\n-/* Output of Dispatch Tables */\n-\n-#define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \\\n-\tfprintf (S, \"\\t.word L%d\\n\", V)\n-\n-/* Assembler Commands for Exception Regions */\n-\n-#define DWARF_CIE_DATA_ALIGNMENT -1\n-\n-/* Assembler Commands for Alignment */\n-\n-#define ASM_OUTPUT_ALIGN(STREAM,POWER) \\\n-\tfprintf (STREAM, \"\\t.p2align\\t%d\\n\", POWER);\n-\n-/* Controlling Debugging Information Format */\n-\n-#define DWARF2_ADDR_SIZE\t4\n-\n-/* Miscellaneous Parameters */\n-\n-#define HAS_LONG_COND_BRANCH false\n-#define HAS_LONG_UNCOND_BRANCH true\n-#define CASE_VECTOR_MODE SImode\n-#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND\n-\n-#define MOVE_MAX 4\n-\n-#define STORE_FLAG_VALUE 1\n-\n-/* 16- or 24-bit pointers */\n-#define Pmode (TARGET_A16 ? HImode : PSImode)\n-#define FUNCTION_MODE QImode\n-\n-#define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()\n-\n-#endif\ndiff --git a/gcc/config/m32c/m32c.md b/gcc/config/m32c/m32c.md\ndeleted file mode 100644\nindex f66deadf311..00000000000\n--- a/gcc/config/m32c/m32c.md\n+++ /dev/null\n@@ -1,79 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-(define_constants\n-  [(R0_REGNO 0)\n-   (R2_REGNO 1)\n-   (R1_REGNO 2)\n-   (R3_REGNO 3)\n-\n-   (A0_REGNO 4)\n-   (A1_REGNO 5)\n-   (SB_REGNO 6)\n-   (FB_REGNO 7)\n-\n-   (SP_REGNO 8)\n-   (PC_REGNO 9)\n-   (FLG_REGNO 10)\n-   (MEM0_REGNO 12)\n-   (MEM7_REGNO 19)\n-   ])\n-\n-(define_constants\n-  [(UNS_PROLOGUE_END 1)\n-   (UNS_EPILOGUE_START 2)\n-   (UNS_EH_EPILOGUE 3)\n-   (UNS_PUSHM 4)\n-   (UNS_POPM 5)\n-   (UNS_SMOVF 6)\n-   (UNS_SSTR 7)\n-   (UNS_SCMPU 8)\n-   (UNS_SMOVU 9)\n-   (UNS_FSETB 10)\n-   (UNS_FREIT 11)\n-   ])\n-\n-;; n = no change, x = clobbered.  The first 16 values are chosen such\n-;; that the enum has one bit set for each flag.\n-(define_attr \"flags\" \"x,c,z,zc,s,sc,sz,szc,o,oc,oz,ozc,os,osc,osz,oszc,n\" (const_string \"n\"))\n-(define_asm_attributes [(set_attr \"flags\" \"x\")])\n-\n-(define_mode_iterator QHI [QI HI])\n-(define_mode_iterator HPSI [(HI \"TARGET_A16\") (PSI \"TARGET_A24\")])\n-(define_mode_iterator QHPSI [QI HI (PSI \"TARGET_A24\")])\n-(define_mode_iterator QHSI [QI HI (SI \"TARGET_A24\")])\n-(define_mode_attr bwl [(QI \"b\") (HI \"w\") (PSI \"l\") (SI \"l\")])\n-\n-(define_code_iterator eqne_cond [eq ne])\n-\n-\n-(define_insn \"nop\"\n-  [(const_int 0)]\n-  \"\"\n-  \"nop\"\n-  [(set_attr \"flags\" \"n\")]\n-)\n-\n-(define_insn \"no_insn\"\n-  [(const_int 1)]\n-  \"\"\n-  \"\"\n-  [(set_attr \"flags\" \"n\")]\n-)\ndiff --git a/gcc/config/m32c/m32c.opt b/gcc/config/m32c/m32c.opt\ndeleted file mode 100644\nindex d43dd0c31fa..00000000000\n--- a/gcc/config/m32c/m32c.opt\n+++ /dev/null\n@@ -1,43 +0,0 @@\n-; Target Options for R8C/M16C/M32C\n-; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-; Contributed by Red Hat.\n-;\n-; This file is part of GCC.\n-;\n-; GCC is free software; you can redistribute it and/or modify it\n-; under the terms of the GNU General Public License as published\n-; by the Free Software Foundation; either version 3, or (at your\n-; option) any later version.\n-;\n-; GCC is distributed in the hope that it will be useful, but WITHOUT\n-; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-; License for more details.\n-;\n-; You should have received a copy of the GNU General Public License\n-; along with GCC; see the file COPYING3.  If not see\n-; <http://www.gnu.org/licenses/>.\n-\n-msim\n-Target\n--msim\tUse simulator runtime.\n-\n-mcpu=r8c\n-Target RejectNegative Var(target_cpu,'r') Init('r')\n--mcpu=r8c\tCompile code for R8C variants.\n-\n-mcpu=m16c\n-Target RejectNegative Var(target_cpu,'6')\n--mcpu=m16c\tCompile code for M16C variants.\n-\n-mcpu=m32cm\n-Target RejectNegative Var(target_cpu,'m')\n--mcpu=m32cm\tCompile code for M32CM variants.\n-\n-mcpu=m32c\n-Target RejectNegative Var(target_cpu,'3')\n--mcpu=m32c\tCompile code for M32C variants.\n-\n-memregs=\n-Target RejectNegative Joined UInteger Var(target_memregs) Init(16)\n--memregs=\tNumber of memreg bytes (default: 16, range: 0..16).\ndiff --git a/gcc/config/m32c/m32c.opt.urls b/gcc/config/m32c/m32c.opt.urls\ndeleted file mode 100644\nindex da1bc024f74..00000000000\n--- a/gcc/config/m32c/m32c.opt.urls\n+++ /dev/null\n@@ -1,8 +0,0 @@\n-; Autogenerated by regenerate-opt-urls.py from gcc/config/m32c/m32c.opt and generated HTML\n-\n-msim\n-UrlSuffix(gcc/M32C-Options.html#index-msim-4)\n-\n-memregs=\n-UrlSuffix(gcc/M32C-Options.html#index-memregs_003d)\n-\ndiff --git a/gcc/config/m32c/minmax.md b/gcc/config/m32c/minmax.md\ndeleted file mode 100644\nindex 5305b65358b..00000000000\n--- a/gcc/config/m32c/minmax.md\n+++ /dev/null\n@@ -1,57 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; min, max\n-\n-(define_insn \"sminqi3\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RhlSd,RhlSd,??Rmm,??Rmm,Raa,Raa\")\n-\t(smin:QI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-\t\t (match_operand:QI 2 \"mrai_operand\" \"iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"min.b\\t%2,%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"sminhi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,RhiSd,??Rmm,??Rmm\")\n-\t(smin:HI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0\")\n-\t\t (match_operand:HI 2 \"mrai_operand\" \"iRhiSd,?Rmm,iRhiSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"min.w\\t%2,%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"smaxqi3\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RhlSd,RhlSd,??Rmm,??Rmm,Raa,Raa\")\n-\t(smax:QI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\")\n-\t\t (match_operand:QI 2 \"mrai_operand\" \"iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"max.b\\t%2,%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"smaxhi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,RhiSd,??Rmm,??Rmm\")\n-\t(smax:HI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0\")\n-\t\t (match_operand:HI 2 \"mrai_operand\" \"iRhiSd,?Rmm,iRhiSd,?Rmm\")))]\n-  \"TARGET_A24\"\n-  \"max.w\\t%2,%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\ndiff --git a/gcc/config/m32c/mov.md b/gcc/config/m32c/mov.md\ndeleted file mode 100644\nindex db0a08c1bd5..00000000000\n--- a/gcc/config/m32c/mov.md\n+++ /dev/null\n@@ -1,490 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; move, push, extend, etc.\n-\n-;; Be careful to never create an alternative that has memory as both\n-;; src and dest, as that makes gcc think that mem-mem moves in general\n-;; are supported.  While the chip does support this, it only has two\n-;; address registers and sometimes gcc requires more than that.  One\n-;; example is code like this: a = *b where both a and b are spilled to\n-;; the stack.\n-\n-(define_insn \"mov<mode>_far_op1\"\n-  [(set (match_operand:QHI 0 \"register_operand\" \"=Rhi\")\n-\t(mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 1 \"register_operand\" \"Ra0\"))\n-\t\t\t (match_operand 2 \"immediate_operand\" \"si\"))))\n-   ]\n-  \"\"\n-  \"lde.<bwl>\\t%D2[%1],%0\"\n-  [(set_attr \"flags\" \"sz\")]\n-  )\n-\n-(define_insn \"mov<mode>_far_op2\"\n-  [(set (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 0 \"register_operand\" \"Ra0\"))\n-\t\t\t (match_operand 1 \"immediate_operand\" \"si\")))\n-\t(match_operand:QHI 2 \"register_operand\"\n-\t\t\t  \"=Rhi\"))\n-   ]\n-  \"\"\n-  \"ste.<bwl>\\t%2,%D1[%0]\"\n-  [(set_attr \"flags\" \"sz\")]\n-  )\n-\n-;; Match push/pop before mov.b for passing char as arg,\n-;; e.g. stdlib/efgcvt.c.\n-(define_insn \"movqi_op\"\n-  [(set (match_operand:QI 0 \"m32c_nonimmediate_operand\"\n-\t\t\t  \"=SF,Rhi*Rmm, Rqi*Rmm, <,          RqiSd*Rmm, SdSs,    Rqi*Rmm, Sd\")\n-\t(match_operand:QI 1 \"m32c_any_operand\"\n-\t\t\t  \"Rhi*Rmm,SF, iRqi*Rmm, iRqiSd*Rmm, >,         Rqi*Rmm, SdSs,    i\"))]\n-  \"m32c_mov_ok (operands, QImode)\"\n-  \"@\n-    lde.b\\t%1,%0\n-    ste.b\\t%1,%0\n-    mov.b\\t%1,%0\n-    push.b\\t%1\n-    pop.b\\t%0\n-    mov.b\\t%1,%0\n-    mov.b\\t%1,%0\n-    mov.b\\t%1,%0\"\n-  [(set_attr \"flags\" \"sz,sz,sz,*,*,sz,sz,sz\")]\n-  )\n-\n-(define_expand \"movqi\"\n-  [(set (match_operand:QI 0 \"nonimmediate_operand\" \"=RqiSd*Rmm\")\n-\t(match_operand:QI 1 \"general_operand\" \"iRqiSd*Rmm\"))]\n-  \"\"\n-  \"if (m32c_prepare_move (operands, QImode)) DONE;\"\n-  )\n-\n-\n-(define_insn \"movhi_op\"\n-  [(set (match_operand:HI 0 \"m32c_nonimmediate_operand\"\n-\t\t\t  \"=SF,Rhi*Rmm, Rhi*Rmm,     Sd, SdSs,   *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr\")\n-\t(match_operand:HI 1 \"m32c_any_operand\"\n-\t\t\t  \" Rhi*Rmm,SF, iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >\"))]\n-  \"m32c_mov_ok (operands, HImode)\"\n-  \"@\n-   ste.w\\t%1,%0\n-   lde.w\\t%1,%0\n-   mov.w\\t%1,%0\n-   mov.w\\t%1,%0\n-   mov.w\\t%1,%0\n-   ldc\\t%1,%0\n-   stc\\t%1,%0\n-   push.w\\t%1\n-   pop.w\\t%0\n-   pushc\\t%1\n-   popc\\t%0\"\n-  [(set_attr \"flags\" \"sz,sz,sz,sz,sz,n,n,n,n,n,n\")]\n-  )\n-\n-(define_expand \"movhi\"\n-  [(set (match_operand:HI 0 \"m32c_nonimmediate_operand\" \"=RhiSd*Rmm\")\n-\t(match_operand:HI 1 \"m32c_any_operand\" \"iRhiSd*Rmm\"))]\n-  \"\"\n-  \"if (m32c_prepare_move (operands, HImode)) DONE;\"\n-  )\n-\n-\n-(define_insn \"movpsi_op\"\n-  [(set (match_operand:PSI 0 \"m32c_nonimmediate_operand\"\n-\t\t\t   \"=Raa, SdRmmRpi,  Rcl,  RpiSd*Rmm, <,       <, Rcl, RpiRaa*Rmm\")\n-\t(match_operand:PSI 1 \"m32c_any_operand\"\n-\t\t\t   \"sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >\"))]\n-  \"TARGET_A24 && m32c_mov_ok (operands, PSImode)\"\n-  \"@\n-   mov.l:s\\t%1,%0\n-   mov.l\\t%1,%0\n-   ldc\\t%1,%0\n-   stc\\t%1,%0\n-   push.l\\t%1\n-   pushc\\t%1\n-   popc\\t%0\n-   #\"\n-  [(set_attr \"flags\" \"sz,sz,n,n,n,n,n,*\")]\n-  )\n-\n-\n-;; The intention here is to combine the add with the move to create an\n-;; indexed move.  GCC doesn't always figure this out itself.\n-\n-(define_peephole2\n-  [(set (match_operand:HPSI 0 \"register_operand\" \"\")\n-\t(plus:HPSI (match_operand:HPSI 1 \"register_operand\" \"\")\n-\t\t   (match_operand:HPSI 2 \"immediate_operand\" \"\")))\n-   (set (match_operand:QHSI 3 \"nonimmediate_operand\" \"\")\n-\t(mem:QHSI (match_operand:HPSI 4 \"register_operand\" \"\")))]\n-  \"REGNO (operands[0]) == REGNO (operands[1])\n-   && REGNO (operands[0]) == REGNO (operands[4])\n-   && (rtx_equal_p (operands[0], operands[3])\n-       || (dead_or_set_p (peep2_next_insn (1), operands[4])\n-          && ! reg_mentioned_p (operands[0], operands[3])))\"\n-  [(set (match_dup 3)\n-\t(mem:QHSI (plus:HPSI (match_dup 1)\n-\t\t\t     (match_dup 2))))]\n-  \"\")\n-\n-(define_peephole2\n-  [(set (match_operand:HPSI 0 \"register_operand\" \"\")\n-\t(plus:HPSI (match_operand:HPSI 1 \"register_operand\" \"\")\n-\t\t   (match_operand:HPSI 2 \"immediate_operand\" \"\")))\n-   (set (mem:QHSI (match_operand:HPSI 4 \"register_operand\" \"\"))\n-\t(match_operand:QHSI 3 \"m32c_any_operand\" \"\"))]\n-  \"REGNO (operands[0]) == REGNO (operands[1])\n-   && REGNO (operands[0]) == REGNO (operands[4])\n-   && dead_or_set_p (peep2_next_insn (1), operands[4])\n-   && ! reg_mentioned_p (operands[0], operands[3])\"\n-  [(set (mem:QHSI (plus:HPSI (match_dup 1)\n-\t\t\t     (match_dup 2)))\n-\t(match_dup 3))]\n-  \"\")\n-\n-; Peephole to generate SImode mov instructions for storing an\n-; immediate double data to a memory location.\n-(define_peephole2\n-  [(set (match_operand:HI 0 \"memory_operand\" \"\")\n-        (match_operand:HI 1 \"const_int_operand\" \"\"))\n-   (set (match_operand:HI 2 \"memory_operand\" \"\")\n-        (match_operand:HI 3 \"const_int_operand\" \"\"))]\n-   \"TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)\"\n-   [(set (match_dup 4) (match_dup 5))]\n-   \"\"\n-)\n-\n-; Some PSI moves must be split.\n-(define_split\n-  [(set (match_operand:PSI 0 \"m32c_nonimmediate_operand\" \"\")\n-\t(match_operand:PSI 1 \"m32c_any_operand\" \"\"))]\n-  \"reload_completed && m32c_split_psi_p (operands)\"\n-  [(set (match_dup 2)\n-\t(match_dup 3))\n-   (set (match_dup 4)\n-\t(match_dup 5))]\n-  \"m32c_split_move (operands, PSImode, 3);\"\n-  )\n-\n-(define_expand \"movpsi\"\n-  [(set (match_operand:PSI 0 \"m32c_nonimmediate_operand\" \"\")\n-\t(match_operand:PSI 1 \"m32c_any_operand\" \"\"))]\n-  \"\"\n-  \"if (m32c_prepare_move (operands, PSImode)) DONE;\"\n-  )\n-\n-\n-\n-(define_expand \"movsi\"\n-  [(set (match_operand:SI 0 \"m32c_nonimmediate_operand\" \"=RsiSd*Rmm\")\n-\t(match_operand:SI 1 \"m32c_any_operand\" \"iRsiSd*Rmm\"))]\n-  \"\"\n-  \"if (m32c_split_move (operands, SImode, 0)) DONE;\"\n-  )\n-\n-; All SI moves are split if TARGET_A16\n-(define_insn_and_split \"movsi_splittable\"\n-  [(set (match_operand:SI 0 \"m32c_nonimmediate_operand\" \"=RsiRaa<*Rmm,  RsiRaaSd*Rmm,  Ss\")\n-\t(match_operand:SI 1 \"m32c_any_operand\" \"iRsiRaaSd*Rmm,  iRsiRaa>*Rmm,  RsiRaa*Rmm\"))]\n-  \"TARGET_A16\"\n-  \"#\"\n-  \"TARGET_A16\"\n-  [(pc)]\n-  \"m32c_split_move (operands, SImode, 1); DONE;\"\n-  )\n-\n-; The movsi pattern doesn't always match because sometimes the modes\n-; don't match.\n-(define_insn \"push_a01_l\"\n-  [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))\n-\t(match_operand:SI 0 \"a_operand\" \"Raa\"))]\n-  \"\"\n-  \"push.l\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"movsi_24\"\n-  [(set (match_operand:SI 0 \"m32c_nonimmediate_operand\"  \"=Rsi*Rmm,   Sd,       RsiSd*Rmm,     <\")\n-\t(match_operand:SI 1 \"m32c_any_operand\" \"iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm\"))]\n-  \"TARGET_A24\"\n-  \"@\n-   mov.l\\t%1,%0\n-   mov.l\\t%1,%0\n-   #\n-   push.l\\t%1\"\n-  [(set_attr \"flags\" \"sz,sz,*,n\")]\n-  )\n-\n-(define_expand \"movdi\"\n-  [(set (match_operand:DI 0 \"m32c_nonimmediate_operand\" \"=RdiSd*Rmm\")\n-\t(match_operand:DI 1 \"m32c_any_operand\" \"iRdiSd*Rmm\"))]\n-  \"\"\n-  \"if (m32c_split_move (operands, DImode, 0)) DONE;\"\n-  )\n-\n-(define_insn_and_split \"movdi_splittable\"\n-  [(set (match_operand:DI 0 \"m32c_nonimmediate_operand\" \"=Rdi<*Rmm,RdiSd*Rmm\")\n-\t(match_operand:DI 1 \"m32c_any_operand\" \"iRdiSd*Rmm,iRdi>*Rmm\"))]\n-  \"\"\n-  \"#\"\n-  \"reload_completed\"\n-  [(pc)]\n-  \"m32c_split_move (operands, DImode, 1); DONE;\"\n-  )\n-\n-\n-\n-\n-(define_insn \"pushqi\"\n-  [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))\n-        (match_operand:QI 0 \"mrai_operand\" \"iRqiSd*Rmm\"))]\n-  \"\"\n-  \"push.b\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_expand \"pushhi\"\n-  [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))\n-        (match_operand:HI 0 \"\" \"\"))]\n-  \"\"\n-  \"if (TARGET_A16)\n-     gen_pushhi_16 (operands[0]);\n-   else\n-     gen_pushhi_24 (operands[0]);\n-   DONE;\"\n-  )\n-\n-(define_insn \"pushhi_16\"\n-  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))\n-        (match_operand:HI 0 \"mrai_operand\" \"iRhiSd*Rmm,Rcr\"))]\n-  \"TARGET_A16\"\n-  \"@\n-   push.w\\t%0\n-   pushc\\t%0\"\n-  [(set_attr \"flags\" \"n,n\")]\n-  )\n-\n-(define_insn \"pushhi_24\"\n-  [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))\n-        (match_operand:HI 0 \"mrai_operand\" \"iRhiSd*Rmm\"))]\n-  \"TARGET_A24\"\n-  \"push.w\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-;(define_insn \"pushpi\"\n-;  [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))\n-;        (match_operand:PI 0 \"mrai_operand\" \"iRaa,Rcr\"))]\n-;  \"TARGET_A24\"\n-;  \"@\n-;   push.l\\t%0\n-;   pushc\\t%0\"\n-;  )\n-\n-(define_insn \"pushsi\"\n-  [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))\n-        (match_operand:SI 0 \"mrai_operand\" \"iRsiSd*Rmm\"))]\n-  \"TARGET_A24\"\n-  \"push.l\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_expand \"pophi\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd*Rmm,Rcr\")\n-        (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]\n-  \"\"\n-  \"if (TARGET_A16)\n-     gen_pophi_16 (operands[0]);\n-   else\n-     gen_pophi_24 (operands[0]);\n-   DONE;\"\n-  )\n-\n-(define_insn \"pophi_16\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd*Rmm,Rcr\")\n-        (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]\n-  \"TARGET_A16\"\n-  \"@\n-   pop.w\\t%0\n-   popc\\t%0\"\n-  [(set_attr \"flags\" \"n,n\")]\n-  )\n-\n-(define_insn \"pophi_24\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd*Rmm\")\n-        (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]\n-  \"TARGET_A24\"\n-  \"pop.w\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"poppsi\"\n-  [(set (match_operand:PSI 0 \"cr_operand\" \"=Rcl\")\n-        (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]\n-  \"TARGET_A24\"\n-  \"popc\\t%0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-\n-;; Rhl used here as an HI-mode Rxl\n-(define_insn \"extendqihi2\"\n-[(set (match_operand:HI 0 \"m32c_nonimmediate_operand\" \"=RhlSd*Rmm\")\n-\t(sign_extend:HI (match_operand:QI 1 \"mra_operand\" \"0\")))]\n-  \"\"\n-  \"exts.b\\t%1\"\n-  [(set_attr \"flags\" \"sz\")]\n-  )\n-\n-(define_insn \"extendhisi2\"\n-  [(set (match_operand:SI 0 \"register_operand\" \"=R03\")\n-\t(sign_extend:SI (match_operand:HI 1 \"r0123_operand\" \"0\")))]\n-  \"\"\n-  \"*\n-   if (REGNO(operands[0]) == 0) return \\\"exts.w\\t%1\\\";\n-   else return \\\"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\\\";\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"extendhipsi2\"\n-  [(set (match_operand:PSI 0 \"register_operand\" \"=R03\")\n-\t(sign_extend:PSI (match_operand:HI 1 \"register_operand\" \"0\")))]\n-  \"\"\n-  \"*\n-   if (REGNO(operands[0]) == 0) return \\\"exts.w\\t%1\\\";\n-   else return \\\"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\\\";\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"extendpsisi2\"\n-  [(set (match_operand:SI 0 \"mr_operand\" \"=R03Sd*Rmm\")\n-\t(sign_extend:SI (match_operand:PSI 1 \"mr_operand\" \"0\")))]\n-  \"\"\n-  \"; expand psi %1 to si %0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"zero_extendpsisi2\"\n-  [(set (match_operand:SI 0 \"mr_operand\" \"=R03Sd*Rmm\")\n-\t(zero_extend:SI (match_operand:PSI 1 \"mr_operand\" \"0\")))]\n-  \"\"\n-  \"; expand psi %1 to si %0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"zero_extendhipsi2\"\n-  [(set (match_operand:PSI 0 \"register_operand\" \"=Raa\")\n-\t(truncate:PSI (zero_extend:SI (match_operand:HI 1 \"register_operand\" \"R03\"))))]\n-  \"\"\n-  \"mov.w\\t%1,%0\"\n-  [(set_attr \"flags\" \"sz\")]\n-  )\n-\n-(define_insn \"zero_extendhisi2\"\n-  [(set (match_operand:SI 0 \"m32c_nonimmediate_operand\" \"=RsiSd\")\n-\t(zero_extend:SI (match_operand:HI 1 \"nonimmediate_operand\" \"0\")))]\n-  \"\"\n-  \"mov.w\\t#0,%H0\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"zero_extendqihi2\"\n-  [(set (match_operand:HI 0 \"m32c_nonimmediate_operand\" \"=?Rhl,RhiSd*Rmm\")\n-\t(zero_extend:HI (match_operand:QI 1 \"nonimmediate_operand\" \"0,0\")))]\n-  \"\"\n-  \"@\n-   mov.b\\t#0,%H0\n-   and.w\\t#255,%0\"\n-  [(set_attr \"flags\" \"x,x\")]\n-  )\n-\n-(define_insn \"truncsipsi2_16\"\n-  [(set (match_operand:PSI 0 \"m32c_nonimmediate_operand\" \"=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm\")\n-\t(truncate:PSI (match_operand:SI 1 \"nonimmediate_operand\" \"0,RsiSd*Rmm,RsiSd*Rmm,Rcr\")))]\n-  \"TARGET_A16\"\n-  \"@\n-   ; no-op trunc si %1 to psi %0\n-   #\n-   ldc\\t%1,%0\n-   stc\\t%1,%0\"\n-  [(set_attr \"flags\" \"n,*,n,n\")]\n-  )\n-\n-(define_insn \"trunchiqi2\"\n-  [(set (match_operand:QI 0 \"m32c_nonimmediate_operand\" \"=RqiRmmSd\")\n-\t(truncate:QI (match_operand:HI 1 \"mra_qi_operand\" \"0\")))]\n-  \"\"\n-  \"; no-op trunc hi %1 to qi %0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"truncsipsi2_24\"\n-  [(set (match_operand:PSI 0              \"m32c_nonimmediate_operand\" \"=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm\")\n-\t(truncate:PSI (match_operand:SI 1 \"m32c_nonimmediate_operand\" \"0,RsiSd*Rmm,RsiSd*Rmm,!Rcl\")))]\n-  \"TARGET_A24\"\n-  \"@\n-   ; no-op trunc si %1 to psi %0\n-   mov.l\\t%1,%0\n-   ldc\\t%1,%0\n-   stc\\t%1,%0\"\n-  [(set_attr \"flags\" \"n,sz,n,n\")]\n-  )\n-\n-(define_expand \"truncsipsi2\"\n-  [(set (match_operand:PSI 0 \"m32c_nonimmediate_operand\" \"=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm\")\n-\t(truncate:PSI (match_operand:SI 1 \"m32c_nonimmediate_operand\" \"0,RsiSd*Rmm,RsiSd*Rmm,Rcr\")))]\n-  \"\"\n-  \"\"\n-  )\n-\n-(define_expand \"reload_inqi\"\n-  [(set (match_operand:QI 2 \"\" \"=&Rqi\")\n-\t(match_operand:QI 1 \"\" \"\"))\n-   (set (match_operand:QI 0 \"\" \"\")\n-\t(match_dup 2))\n-   ]\n-  \"\"\n-  \"\")\n-\n-(define_expand \"reload_outqi\"\n-  [(set (match_operand:QI 2 \"\" \"=&Rqi\")\n-\t(match_operand:QI 1 \"\" \"\"))\n-   (set (match_operand:QI 0 \"\" \"\")\n-\t(match_dup 2))\n-   ]\n-  \"\"\n-  \"\")\n-\n-(define_expand \"reload_inhi\"\n-  [(set (match_operand:HI 2 \"\" \"=&Rhi\")\n-\t(match_operand:HI 1 \"\" \"\"))\n-   (set (match_operand:HI 0 \"\" \"\")\n-\t(match_dup 2))\n-   ]\n-  \"\"\n-  \"\")\n-\n-(define_expand \"reload_outhi\"\n-  [(set (match_operand:HI 2 \"\" \"=&Rhi\")\n-\t(match_operand:HI 1 \"\" \"\"))\n-   (set (match_operand:HI 0 \"\" \"\")\n-\t(match_dup 2))\n-   ]\n-  \"\"\n-  \"\")\ndiff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md\ndeleted file mode 100644\nindex 4affab8e71b..00000000000\n--- a/gcc/config/m32c/muldiv.md\n+++ /dev/null\n@@ -1,287 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; multiply and divide\n-\n-; Here is the pattern for the const_int.\n-(define_insn \"mulqihi3_c\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,??Rmm\")\n-        (mult:HI (sign_extend:HI (match_operand:QI 1 \"mra_operand\" \"%0,0\"))\n-                 (match_operand 2 \"immediate_operand\" \"i,i\")))]\n-  \"\"\n-  \"mul.b\\t%2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-; Here is the pattern for registers and such.\n-(define_insn \"mulqihi3_r\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa\")\n-        (mult:HI (sign_extend:HI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\"))\n-                 (sign_extend:HI (match_operand:QI 2 \"mra_operand\" \"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm\"))))]\n-  \"\"\n-  \"mul.b\\t%2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-; Don't try to sign_extend a const_int.  Same for all other multiplies.\n-(define_expand \"mulqihi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa\")\n-        (mult:HI (sign_extend:HI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\"))\n-                 (match_operand:QI 2 \"mra_operand\" \"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm\")))]\n-  \"\"\n-  \"{ if (GET_MODE (operands[2]) != VOIDmode)\n-      operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }\"\n-)\n-\n-(define_insn \"umulqihi3_c\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,??Rmm\")\n-        (mult:HI (zero_extend:HI (match_operand:QI 1 \"mra_operand\" \"%0,0\"))\n-                 (match_operand 2 \"immediate_operand\" \"i,i\")))]\n-  \"\"\n-  \"mulu.b\\t%U2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_insn \"umulqihi3_r\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa\")\n-        (mult:HI (zero_extend:HI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\"))\n-                 (zero_extend:HI (match_operand:QI 2 \"mra_operand\" \"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm\"))))]\n-  \"\"\n-  \"mulu.b\\t%U2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_expand \"umulqihi3\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa\")\n-        (mult:HI (zero_extend:HI (match_operand:QI 1 \"mra_operand\" \"%0,0,0,0,0,0\"))\n-                 (match_operand:QI 2 \"mra_operand\" \"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm\")))]\n-  \"\"\n-  \"{ if (GET_MODE (operands[2]) != VOIDmode)\n-      operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }\"\n-)\n-\n-(define_insn \"mulhisi3_c\"\n-  [(set (match_operand:SI 0 \"ra_operand\" \"=Rsi\")\n-        (mult:SI (sign_extend:SI (match_operand:HI 1 \"mra_operand\" \"%0\"))\n-                 (match_operand:HI 2 \"immediate_operand\" \"i\")))]\n-  \"\"\n-  \"mul.w\\t%2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_insn \"mulhisi3_r\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=Rsi,Rsi\")\n-        (mult:SI (sign_extend:SI (match_operand:HI 1 \"mra_operand\" \"%0,0\"))\n-                 (sign_extend:SI (match_operand:HI 2 \"mra_operand\" \"RhiSd,?Rmm\"))))]\n-  \"\"\n-  \"mul.w\\t%2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_expand \"mulhisi3\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm\")\n-        (mult:SI (sign_extend:SI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0\"))\n-                 (match_operand:HI 2 \"mra_operand\" \"RhiSd,?Rmm,RhiSd,?Rmm\")))]\n-  \"\"\n-  \"{ if (GET_MODE (operands[2]) != VOIDmode)\n-      operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }\"\n-)\n-\n-(define_insn \"umulhisi3_c\"\n-  [(set (match_operand:SI 0 \"ra_operand\" \"=Rsi\")\n-        (mult:SI (zero_extend:SI (match_operand:HI 1 \"mra_operand\" \"%0\"))\n-                 (match_operand 2 \"immediate_operand\" \"i\")))]\n-  \"\"\n-  \"mulu.w\\t%u2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_insn \"umulhisi3_r\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=Rsi,Rsi\")\n-        (mult:SI (zero_extend:SI (match_operand:HI 1 \"mra_operand\" \"%0,0\"))\n-                 (zero_extend:SI (match_operand:HI 2 \"mra_operand\" \"RhiSd,?Rmm\"))))]\n-  \"\"\n-  \"mulu.w\\t%u2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_expand \"umulhisi3\"\n-  [(set (match_operand:SI 0 \"mra_operand\" \"=RsiSd,RsiSd,??Rmm,??Rmm\")\n-        (mult:SI (zero_extend:SI (match_operand:HI 1 \"mra_operand\" \"%0,0,0,0\"))\n-                 (match_operand:HI 2 \"mra_operand\" \"RhiSd,?Rmm,RhiSd,?Rmm\")))]\n-  \"\"\n-  \"{ if (GET_MODE (operands[2]) != VOIDmode)\n-      operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }\"\n-)\n-\n-\n-; GCC expects to be able to multiply pointer-sized integers too, but\n-; fortunately it only multiplies by powers of two, although sometimes\n-; they're negative.\n-(define_insn \"mulpsi3_op\"\n-  [(set (match_operand:PSI 0 \"mra_operand\" \"=RsiSd\")\n-\t(mult:PSI (match_operand:PSI 1 \"mra_operand\" \"%0\")\n-\t\t  (match_operand 2 \"m32c_psi_scale\" \"Ilb\")))]\n-  \"TARGET_A24\"\n-  \"shl.l\\t%b2,%0\"\n-  [(set_attr \"flags\" \"szc\")]\n-  )\n-\n-(define_expand \"mulpsi3\"\n-  [(set (match_operand:PSI 0 \"mra_operand\" \"=RsiSd\")\n-\t(mult:PSI (match_operand:PSI 1 \"mra_operand\" \"%0\")\n-\t\t  (match_operand 2 \"m32c_psi_scale\" \"Ilb\")))]\n-  \"TARGET_A24\"\n-  \"if (GET_CODE (operands[2]) != CONST_INT\n-       || ! m32c_psi_scale (operands[2], PSImode))\n-     {\n-       m32c_expand_neg_mulpsi3 (operands);\n-       DONE;\n-     }\"\n-  )\n-\n-(define_insn \"mulsi3\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R02,R02\")\n-        (mult:SI (match_operand:SI 1 \"r0123_operand\" \"%0,0\")\n-                 (match_operand:SI 2 \"mra_operand\" \"RsiSd,?Rmm\")))]\n-  \"TARGET_M32C\"\n-  \"mul.l\\t%2,%1\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_expand \"divmodqi4\"\n-  [(set (match_dup 4)\n-\t(sign_extend:HI (match_operand:QI 1 \"register_operand\" \"0,0\")))\n-   (parallel [(set (match_operand:QI 0 \"register_operand\" \"=R0w,R0w\")\n-\t\t   (div:QI (match_dup 4)\n-\t\t\t   (match_operand:QI 2 \"general_operand\" \"iRqiSd,?Rmm\")))\n-\t      (set (match_operand:QI 3 \"register_operand\" \"=&R0h,&R0h\")\n-\t\t   (mod:QI (match_dup 4) (match_dup 2)))\n-\t      ])]\n-  \"0\"\n-  \"operands[4] = gen_reg_rtx (HImode);\"\n-  )\n-\n-(define_insn \"divmodqi4_n\"\n-  [(set (match_operand:QI 0 \"register_operand\" \"=R0l,R0l\")\n-\t(div:QI (match_operand:HI 1 \"register_operand\" \"R0w,R0w\")\n-\t\t(match_operand:QI 2 \"general_operand\" \"iRqiSd,?Rmm\")))\n-   (set (match_operand:QI 3 \"register_operand\" \"=R0h,R0h\")\n-\t(mod:QI (match_dup 1) (match_dup 2)))\n-   ]\n-  \"0\"\n-  \"div.b\\t%2\"\n-  [(set_attr \"flags\" \"o\")]\n-  )\n-\n-(define_expand \"udivmodqi4\"\n-  [(set (match_dup 4)\n-\t(zero_extend:HI (match_operand:QI 1 \"register_operand\" \"0,0\")))\n-   (parallel [(set (match_operand:QI 0 \"register_operand\" \"=R0l,R0l\")\n-\t\t   (udiv:QI (match_dup 4)\n-\t\t\t   (match_operand:QI 2 \"general_operand\" \"iRqiSd,?Rmm\")))\n-\t      (set (match_operand:QI 3 \"register_operand\" \"=&R0h,&R0h\")\n-\t\t   (umod:QI (match_dup 4) (match_dup 2)))\n-\t      ])]\n-  \"0\"\n-  \"operands[4] = gen_reg_rtx (HImode);\"\n-  )\n-\n-(define_insn \"udivmodqi4_n\"\n-  [(set (match_operand:QI 0 \"register_operand\" \"=R0l,R0l\")\n-\t(udiv:QI (match_operand:HI 1 \"register_operand\" \"R0w,R0w\")\n-\t\t(match_operand:QI 2 \"general_operand\" \"iRqiSd,?Rmm\")))\n-   (set (match_operand:QI 3 \"register_operand\" \"=R0h,R0h\")\n-\t(umod:QI (match_dup 1) (match_dup 2)))\n-   ]\n-  \"0\"\n-  \"divu.b\\t%2\"\n-  [(set_attr \"flags\" \"o\")]\n-  )\n-\n-(define_expand \"divmodhi4\"\n-  [(set (match_dup 4)\n-\t(sign_extend:SI (match_operand:HI 1 \"register_operand\" \"0,0\")))\n-   (parallel [(set (match_operand:HI 0 \"register_operand\" \"=R0w,R0w\")\n-\t\t   (div:HI (match_dup 4)\n-\t\t\t   (match_operand:HI 2 \"general_operand\" \"iRhiSd,?Rmm\")))\n-\t      (set (match_operand:HI 3 \"register_operand\" \"=R2w,R2w\")\n-\t\t   (mod:HI (match_dup 4) (match_dup 2)))\n-\t      ])]\n-  \"\"\n-  \"operands[4] = gen_reg_rtx (SImode);\"\n-  )\n-\n-(define_insn \"divmodhi4_n\"\n-  [(set (match_operand:HI 0 \"m32c_r0_operand\" \"=R0w,R0w\")\n-\t(div:HI (match_operand:SI 1 \"m32c_r0_operand\" \"R02,R02\")\n-\t\t(match_operand:HI 2 \"m32c_notr2_operand\" \"iR1wR3wRaaSd,?Rmm\")))\n-   (set (match_operand:HI 3 \"m32c_r2_operand\" \"=R2w,R2w\")\n-\t(mod:HI (match_dup 1) (match_dup 2)))\n-   ]\n-  \"\"\n-  \"div.w\\t%2\"\n-  [(set_attr \"flags\" \"o\")]\n-  )\n-\n-(define_expand \"udivmodhi4\"\n-  [(set (match_dup 4)\n-\t(zero_extend:SI (match_operand:HI 1 \"register_operand\" \"0,0\")))\n-   (parallel [(set (match_operand:HI 0 \"register_operand\" \"=R0w,R0w\")\n-\t\t   (udiv:HI (match_dup 4)\n-\t\t\t   (match_operand:HI 2 \"general_operand\" \"iRhiSd,?Rmm\")))\n-\t      (set (match_operand:HI 3 \"register_operand\" \"=R2w,R2w\")\n-\t\t   (umod:HI (match_dup 4) (match_dup 2)))\n-\t      ])]\n-  \"\"\n-  \"operands[4] = gen_reg_rtx (SImode);\"\n-  )\n-\n-(define_insn \"udivmodhi4_n\"\n-  [(set (match_operand:HI 0 \"m32c_r0_operand\" \"=R0w,R0w\")\n-\t(udiv:HI (match_operand:SI 1 \"m32c_r0_operand\" \"R02,R02\")\n-\t\t(match_operand:HI 2 \"m32c_notr2_operand\" \"iR1wR3wRaaSd,?Rmm\")))\n-   (set (match_operand:HI 3 \"m32c_r2_operand\" \"=R2w,R2w\")\n-\t(umod:HI (match_dup 1) (match_dup 2)))\n-   ]\n-  \"\"\n-  \"divu.w\\t%2\"\n-  [(set_attr \"flags\" \"o\")]\n-  )\n-\n-(define_insn \"divsi3\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R02,R02\")\n-        (div:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-                (match_operand:SI 2 \"mra_operand\" \"RsiSd,?Rmm\")))]\n-  \"TARGET_M32C\"\n-  \"div.l\\t%2\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-(define_insn \"udivsi3\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R02,R02\")\n-        (udiv:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-                 (match_operand:SI 2 \"mra_operand\" \"RsiSd,?Rmm\")))]\n-  \"TARGET_M32C\"\n-  \"divu.l\\t%2\"\n-  [(set_attr \"flags\" \"o\")]\n-)\n-\n-\ndiff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md\ndeleted file mode 100644\nindex b8382c9a359..00000000000\n--- a/gcc/config/m32c/predicates.md\n+++ /dev/null\n@@ -1,294 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; Predicates\n-\n-; TRUE for any valid operand.  We do this because general_operand\n-; refuses to match volatile memory refs.\n-\n-(define_predicate \"m32c_any_operand\"\n-  (ior (match_operand 0 \"general_operand\")\n-       (match_code \"mem,const_int,const_double\"))\n-  {\n-    return ! m32c_illegal_subreg_p (op);\n-  }\n-)\n-\n-; Likewise for nonimmediate_operand.\n-\n-(define_predicate \"m32c_nonimmediate_operand\"\n-  (ior (match_operand 0 \"nonimmediate_operand\")\n-       (match_code \"mem\"))\n-  {\n-    return ! m32c_illegal_subreg_p (op);\n-  }\n-)\n-\n-; TRUE if the operand is a pseudo-register.\n-(define_predicate \"m32c_pseudo\"\n-  (ior (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) >= FIRST_PSEUDO_REGISTER\"))\n-       (and (match_code \"subreg\")\n-\t    (and (match_test \"GET_CODE (XEXP (op, 0)) == REG\")\n-\t\t (match_test \"REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER\")))))\n-       \n-\n-; Returning true causes many predicates to NOT match.  We allow\n-; subregs for type changing, but not for size changing.\n-(define_predicate \"m32c_wide_subreg\"\n-  (and (match_code \"subreg\")\n-       (not (match_operand 0 \"m32c_pseudo\")))\n-  {\n-    unsigned int sizeo = GET_MODE_SIZE (GET_MODE (op));\n-    unsigned int sizei = GET_MODE_SIZE (GET_MODE (XEXP (op, 0)));\n-    sizeo = (sizeo + UNITS_PER_WORD - 1) / UNITS_PER_WORD;\n-    sizei = (sizei + UNITS_PER_WORD - 1) / UNITS_PER_WORD;\n-    return sizeo != sizei;\n-  })\n-\n-; TRUE for r0 through r3, or a pseudo that reload could put in r0\n-; through r3 (likewise for the next couple too)\n-(define_predicate \"r0123_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) <= R3_REGNO\"))))\n-\n-; TRUE for r0\n-(define_predicate \"m32c_r0_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) == R0_REGNO\"))))\n-\n-; TRUE for r1\n-(define_predicate \"m32c_r1_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) == R1_REGNO\"))))\n-\n-; TRUE for HL_CLASS (r0 or r1)\n-(define_predicate \"m32c_hl_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) == R0_REGNO || REGNO(op) == R1_REGNO\"))))\n-\n-\n-; TRUE for r2\n-(define_predicate \"m32c_r2_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) == R2_REGNO\"))))\n-\n-; TRUE for r3\n-(define_predicate \"m32c_r3_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) == R3_REGNO\"))))\n-\n-; TRUE for any general operand except r2.\n-(define_predicate \"m32c_notr2_operand\"\n-  (and (match_operand 0 \"general_operand\")\n-       (ior (not (match_code \"reg\"))\n-\t    (match_test \"REGNO(op) != R2_REGNO\"))))\n-\n-; TRUE for the stack pointer.\n-(define_predicate \"m32c_sp_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) == SP_REGNO\"))))\n-\n-; TRUE for control registers.\n-(define_predicate \"cr_operand\"\n-  (match_code \"reg\")\n-  \"return (REGNO (op) >= SB_REGNO\n-           && REGNO (op) <= FLG_REGNO);\")\n-\n-; TRUE for $a0 or $a1.\n-(define_predicate \"a_operand\"\n-  (and (match_code \"reg\")\n-       (match_test \"REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO\")))\n-\n-; TRUE for $a0 or $a1 or a pseudo\n-(define_predicate \"ap_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO\"))))\n-\n-; TRUE for r0 through r3, or a0 or a1.\n-(define_predicate \"ra_operand\"\n-  (and (and (match_operand 0 \"register_operand\" \"\")\n-\t    (not (match_operand 1 \"cr_operand\" \"\")))\n-       (not (match_operand 2 \"m32c_wide_subreg\" \"\"))))\n-\n-; Likewise, plus TRUE for memory references.\n-(define_predicate \"mra_operand\"\n-  (and (and (match_operand 0 \"m32c_nonimmediate_operand\" \"\")\n-\t    (not (match_operand 1 \"cr_operand\" \"\")))\n-       (not (match_operand 2 \"m32c_wide_subreg\" \"\"))))\n-\n-; Likewise, plus TRUE for subregs.\n-(define_predicate \"mras_operand\"\n-  (and (match_operand 0 \"nonimmediate_operand\" \"\")\n-       (not (match_operand 1 \"cr_operand\" \"\"))))\n-\n-; As above, but no push/pop operations\n-(define_predicate \"mra_nopp_operand\"\n-  (match_operand 0 \"mra_operand\" \"\")\n-{\n-  if (GET_CODE (op) == MEM\n-      && (GET_CODE (XEXP (op, 0)) == PRE_DEC\n-\t  || (GET_CODE (XEXP (op, 0)) == POST_INC)))\n-    return 0;\n-  return 1;\n-})\n-\n-; TRUE for memory, r0..r3, a0..a1, or immediates.\n-(define_predicate \"mrai_operand\"\n-  (and (and (match_operand 0 \"m32c_any_operand\" \"\")\n-\t    (not (match_operand 1 \"cr_operand\" \"\")))\n-       (not (match_operand 2 \"m32c_wide_subreg\" \"\"))))\n-\n-; Likewise, plus true for subregs.\n-(define_predicate \"mrasi_operand\"\n-  (and (match_operand 0 \"general_operand\" \"\")\n-       (not (match_operand 1 \"cr_operand\" \"\"))))\n-\n-; TRUE for r0..r3 or memory.\n-(define_predicate \"mr_operand\"\n-  (and (match_operand 0 \"mra_operand\" \"\")\n-       (not (match_operand 1 \"a_operand\" \"\"))))\n-\n-; TRUE for a0..a1 or memory.\n-(define_predicate \"ma_operand\"\n-  (ior (match_operand 0 \"a_operand\" \"\")\n-       (match_operand 1 \"memory_operand\" \"\")))\n-\n-; TRUE for memory operands that are not indexed\n-(define_predicate \"memsym_operand\"\n-  (and (match_operand 0 \"memory_operand\" \"\")\n-       (match_test \"satisfies_constraint_Si (op)\")))\n-\n-; TRUE for memory operands with small integer addresses\n-(define_predicate \"memimmed_operand\"\n-  (and (match_operand 0 \"memory_operand\" \"\")\n-       (match_test \"satisfies_constraint_Sp (op)\")))\n-\n-; TRUE for r1h.  This is complicated since r1h isn't a register GCC\n-; normally knows about.\n-(define_predicate \"r1h_operand\"\n-  (match_code \"zero_extract\")\n-  {\n-    rtx reg = XEXP (op, 0);\n-    rtx size = XEXP (op, 1);\n-    rtx pos = XEXP (op, 2);\n-    return (GET_CODE (reg) == REG\n-\t    && REGNO (reg) == R1_REGNO\n-\t    && GET_CODE (size) == CONST_INT\n-\t    && INTVAL (size) == 8\n-\t    && GET_CODE (pos) == CONST_INT\n-\t    && INTVAL (pos) == 8);\n-  })\n-\n-; TRUE if we can shift by this amount.  Constant shift counts have a\n-; limited range.\n-(define_predicate \"shiftcount_operand\"\n-  (ior (match_operand 0 \"mra_operand\" \"\")\n-       (and (match_operand 2 \"const_int_operand\" \"\")\n-\t    (match_test \"INTVAL (op) >= -8 && INTVAL (op) && INTVAL (op) <= 8\"))))\n-(define_predicate \"longshiftcount_operand\"\n-  (ior (match_operand 0 \"mra_operand\" \"\")\n-       (and (match_operand 2 \"const_int_operand\" \"\")\n-\t    (match_test \"INTVAL (op) >= -32 && INTVAL (op) && INTVAL (op) <= 32\"))))\n-\n-; TRUE for r0..r3, a0..a1, or sp.\n-(define_predicate \"mra_or_sp_operand\"\n-  (and (ior (match_operand 0 \"mra_operand\")\n-\t    (match_operand 1 \"m32c_sp_operand\"))\n-       (not (match_operand 2 \"m32c_wide_subreg\" \"\"))))\n-\n-\n-; TRUE for r2 or r3.\n-(define_predicate \"m32c_r2r3_operand\"\n-  (ior (and (match_code \"reg\")\n-\t    (ior (match_test \"REGNO(op) == R2_REGNO\")\n-\t\t (match_test \"REGNO(op) == R3_REGNO\")))\n-       (and (match_code \"subreg\")\n-\t    (match_test \"GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)\"))))\n-\n-; Likewise, plus TRUE for a0..a1.\n-(define_predicate \"m32c_r2r3a_operand\"\n-  (ior (match_operand 0 \"m32c_r2r3_operand\" \"\")\n-       (match_operand 0 \"a_operand\" \"\")))\n-\n-; These two are only for movqi - no subreg limit\n-(define_predicate \"mra_qi_operand\"\n-  (and (and (match_operand 0 \"m32c_nonimmediate_operand\" \"\")\n-\t    (not (match_operand 1 \"cr_operand\" \"\")))\n-       (not (match_operand 1 \"m32c_r2r3a_operand\" \"\"))))\n-\n-(define_predicate \"mrai_qi_operand\"\n-  (and (and (match_operand 0 \"m32c_any_operand\" \"\")\n-\t    (not (match_operand 1 \"cr_operand\" \"\")))\n-       (not (match_operand 1 \"m32c_r2r3a_operand\" \"\"))))\n-\n-(define_predicate \"a_qi_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (match_operand 1 \"a_operand\" \"\")))\n-\n-; TRUE for comparisons we support.\n-(define_predicate \"m32c_cmp_operator\"\n-  (match_code \"eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu\"))\n-\n-(define_predicate \"m32c_eqne_operator\"\n-  (match_code \"eq,ne\"))\n-\n-; TRUE for mem0\n-(define_predicate \"m32c_mem0_operand\"\n-  (ior (match_operand 0 \"m32c_pseudo\" \"\")\n-       (and (match_code \"reg\")\n-\t    (match_test \"REGNO(op) == MEM0_REGNO\"))))\n-\n-; TRUE for things the call patterns can return.\n-(define_predicate \"m32c_return_operand\"\n-  (ior (match_operand 0 \"m32c_r0_operand\")\n-       (ior (match_operand 0 \"m32c_mem0_operand\")\n-\t    (match_code \"parallel\"))))\n-\n-; TRUE for constants we can multiply pointers by\n-(define_predicate \"m32c_psi_scale\"\n-  (and (match_operand 0 \"const_int_operand\")\n-       (match_test \"satisfies_constraint_Ilb (op)\")))\n-\n-; TRUE for one bit set (bit) or clear (mask) out of N bits.\n-\n-(define_predicate \"m32c_1bit8_operand\"\n-  (and (match_operand 0 \"const_int_operand\")\n-       (match_test \"satisfies_constraint_Ilb (op)\")))\n-\n-(define_predicate \"m32c_1bit16_operand\"\n-  (and (match_operand 0 \"const_int_operand\")\n-       (match_test \"satisfies_constraint_Ilw (op)\")))\n-\n-(define_predicate \"m32c_1mask8_operand\"\n-  (and (match_operand 0 \"const_int_operand\")\n-       (match_test \"satisfies_constraint_ImB (op)\")))\n-\n-(define_predicate \"m32c_1mask16_operand\"\n-  (and (match_operand 0 \"const_int_operand\")\n-       (match_test \"satisfies_constraint_Imw (op)\")))\ndiff --git a/gcc/config/m32c/prologue.md b/gcc/config/m32c/prologue.md\ndeleted file mode 100644\nindex 922e8cad6a6..00000000000\n--- a/gcc/config/m32c/prologue.md\n+++ /dev/null\n@@ -1,201 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; Prologue and epilogue patterns\n-\n-(define_expand \"prologue\"\n-  [(const_int 1)]\n-  \"\"\n-  \"m32c_emit_prologue(); DONE;\"\n-  )\n-\n-; For the next two, operands[0] is the amount of stack space we want\n-; to reserve.\n-\n-; We assume dwarf2out will process each set in sequence.\n-(define_insn \"prologue_enter_16\"\n-  [(set (mem:HI (plus:HI (reg:HI SP_REGNO) (const_int -2)))\n-\t(reg:HI FB_REGNO))\n-   (set (reg:HI FB_REGNO)\n-\t(plus:HI (reg:HI SP_REGNO) (const_int -2)))\n-   (set (reg:HI SP_REGNO)\n-\t(minus:HI (reg:HI SP_REGNO)\n-\t           (match_operand 0 \"const_int_operand\" \"i\")))\n-   ]\n-  \"TARGET_A16\"\n-  {\n-    /* This is due to binutils bug gas/4659.  */\n-    if (INTVAL (operands[0]) == 2)\n-      return \"enter\\t#0\";\n-    return \"enter\\t%0-2\";\n-  }\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"prologue_enter_24\"\n-  [(set (mem:SI (plus:PSI (reg:PSI SP_REGNO) (const_int -4)))\n-\t(reg:SI FB_REGNO))\n-   (set (reg:PSI FB_REGNO)\n-\t(plus:PSI (reg:PSI SP_REGNO) (const_int -4)))\n-   (set (reg:PSI SP_REGNO)\n-\t(minus:PSI (reg:PSI SP_REGNO)\n-\t           (match_operand 0 \"const_int_operand\" \"i\")))\n-   ]\n-  \"TARGET_A24\"\n-  {\n-    /* This is due to binutils bug gas/4659.  */\n-    if (INTVAL (operands[0]) == 4)\n-      return \"enter\\t#0\";\n-    return \"enter\\t%0-4\";\n-  }\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-; Just a comment, for debugging the assembler output.\n-(define_insn \"prologue_end\"\n-  [(unspec_volatile [(const_int 0)] UNS_PROLOGUE_END)]\n-  \"\"\n-  \"; end of prologue\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-\n-\n-(define_expand \"epilogue\"\n-  [(const_int 1)]\n-  \"\"\n-  \"m32c_emit_epilogue(); DONE;\"\n-  )\n-\n-(define_expand \"eh_return\"\n-  [(match_operand:PSI 0 \"\" \"\")]\n-  \"\"\n-  \"m32c_emit_eh_epilogue(operands[0]);\n-   emit_barrier ();\n-   DONE;\"\n-  )\n-\n-(define_insn \"eh_epilogue\"\n-  [(set (pc)\n-\t(unspec_volatile [(match_operand 0 \"m32c_r1_operand\" \"\")\n-\t\t\t  (match_operand 1 \"m32c_r0_operand\" \"\")\n-\t\t\t  ] UNS_EH_EPILOGUE))\n-   (return)]\n-  \"\"\n-  \"jmp.a\\t__m32c_eh_return\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"epilogue_exitd_16\"\n-  [(set (reg:HI SP_REGNO)\n-\t(plus:HI (reg:HI FB_REGNO)\n-\t      (const_int 2)))\n-   (set (reg:HI FB_REGNO)\n-\t(mem:HI (reg:HI FB_REGNO)))\n-   (return)\n-   ]\n-  \"TARGET_A16\"\n-  \"exitd\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"epilogue_reit_16\"\n-  [(set (reg:HI SP_REGNO)\n-\t(plus:HI (reg:HI SP_REGNO)\n-\t      (const_int 4)))\n-   (return)\n-   ]\n-  \"TARGET_A16\"\n-  \"reit\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"epilogue_exitd_24\"\n-  [(set (reg:PSI SP_REGNO)\n-\t(plus:PSI (reg:PSI FB_REGNO)\n-\t      (const_int 4)))\n-   (set (reg:PSI FB_REGNO)\n-\t(mem:PSI (reg:PSI FB_REGNO)))\n-   (return)\n-   ]\n-  \"TARGET_A24\"\n-  \"exitd\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"epilogue_reit_24\"\n-  [(set (reg:PSI SP_REGNO)\n-\t(plus:PSI (reg:PSI SP_REGNO)\n-\t      (const_int 6)))\n-   (return)\n-   ]\n-  \"TARGET_A24\"\n-  \"reit\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"epilogue_freit\"\n-  [(unspec [(const_int 0)] UNS_FREIT)\n-   (return)\n-   ]\n-  \"\"\n-  \"freit\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"epilogue_rts\"\n-  [(return)\n-   ]\n-  \"\"\n-  \"rts\"\n-  [(set_attr \"flags\" \"x\")]\n-  )\n-\n-(define_insn \"epilogue_start\"\n-  [(unspec_volatile [(const_int 0)] UNS_EPILOGUE_START)]\n-  \"\"\n-  \"; start of epilogue\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-\n-; These are used by the prologue/epilogue code.\n-\n-(define_insn \"pushm\"\n-  [(unspec [(match_operand 0 \"const_int_operand\" \"i\")] UNS_PUSHM)]\n-  \"\"\n-  \"pushm\\t%p0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"popm\"\n-  [(unspec [(match_operand 0 \"const_int_operand\" \"i\")] UNS_POPM)]\n-  \"\"\n-  \"popm\\t%p0\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\n-(define_insn \"fset_b\"\n-  [(unspec [(const_int 0)] UNS_FSETB)]\n-  \"\"\n-  \"fset\\tB\"\n-  [(set_attr \"flags\" \"n\")]\n-  )\n-\ndiff --git a/gcc/config/m32c/shift.md b/gcc/config/m32c/shift.md\ndeleted file mode 100644\nindex c80bf401cb1..00000000000\n--- a/gcc/config/m32c/shift.md\n+++ /dev/null\n@@ -1,351 +0,0 @@\n-;; Machine Descriptions for R8C/M16C/M32C\n-;; Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-;; Contributed by Red Hat.\n-;;\n-;; This file is part of GCC.\n-;;\n-;; GCC is free software; you can redistribute it and/or modify it\n-;; under the terms of the GNU General Public License as published\n-;; by the Free Software Foundation; either version 3, or (at your\n-;; option) any later version.\n-;;\n-;; GCC is distributed in the hope that it will be useful, but WITHOUT\n-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-;; License for more details.\n-;;\n-;; You should have received a copy of the GNU General Public License\n-;; along with GCC; see the file COPYING3.  If not see\n-;; <http://www.gnu.org/licenses/>.\n-\n-;; bit shifting\n-\n-; Shifts are unusual for m32c.  We only support shifting in one\n-; \"direction\" but the shift count is signed.  Also, immediate shift\n-; counts have a limited range, and variable shift counts have to be in\n-; $r1h which GCC normally doesn't even know about.\n-\n-; Other than compensating for the above, the patterns below are pretty\n-; straightforward.\n-\n-(define_insn \"ashlqi3_i\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RqiSd*Rmm,RqiSd*Rmm\")\n-\t(ashift:QI (match_operand:QI 1 \"mra_operand\" \"0,0\")\n-\t\t   (match_operand:QI 2 \"mrai_operand\" \"In4,RqiSd\")))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"\"\n-  \"@\n-   sha.b\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.b\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"ashrqi3_i\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RqiSd*Rmm,RqiSd*Rmm\")\n-\t(ashiftrt:QI (match_operand:QI 1 \"mra_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"mrai_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"\"\n-  \"@\n-   sha.b\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.b\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"lshrqi3_i\"\n-  [(set (match_operand:QI 0 \"mra_operand\" \"=RqiSd*Rmm,RqiSd*Rmm\")\n-\t(lshiftrt:QI (match_operand:QI 1 \"mra_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"mrai_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"\"\n-  \"@\n-   shl.b\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tshl.b\\tr1h,%0\"\n-  [(set_attr \"flags\" \"szc,szc\")]\n-  )\n-\n-\n-(define_expand \"ashlqi3\"\n-  [(parallel [(set (match_operand:QI 0 \"mra_operand\" \"\")\n-\t(ashift:QI (match_operand:QI 1 \"mra_operand\" \"\")\n-\t\t   (match_operand:QI 2 \"general_operand\" \"\")))\n-   (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, 1, ASHIFT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"ashrqi3\"\n-  [(parallel [(set (match_operand:QI 0 \"mra_operand\" \"\")\n-\t(ashiftrt:QI (match_operand:QI 1 \"mra_operand\" \"\")\n-\t\t     (neg:QI (match_operand:QI 2 \"general_operand\" \"\"))))\n-   (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, -1, ASHIFTRT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"lshrqi3\"\n-  [(parallel [(set (match_operand:QI 0 \"mra_operand\" \"\")\n-\t\t   (lshiftrt:QI (match_operand:QI 1 \"mra_operand\" \"\")\n-\t\t\t\t(neg:QI (match_operand:QI 2 \"general_operand\" \"\"))))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, -1, LSHIFTRT))\n-     DONE;\"\n-  )\n-\n-; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n-\n-(define_insn \"ashlhi3_i\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=SdRhi*Rmm,SdRhi*Rmm\")\n-\t(ashift:HI (match_operand:HI 1 \"mra_operand\" \"0,0\")\n-\t\t   (match_operand:QI 2 \"mrai_operand\" \"In4,RqiSd\")))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"\"\n-  \"@\n-   sha.w\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.w\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"ashrhi3_i\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=SdRhi*Rmm,SdRhi*Rmm\")\n-\t(ashiftrt:HI (match_operand:HI 1 \"mra_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"mrai_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"\"\n-  \"@\n-   sha.w\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.w\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"lshrhi3_i\"\n-  [(set (match_operand:HI 0 \"mra_operand\" \"=RhiSd*Rmm,RhiSd*Rmm\")\n-\t(lshiftrt:HI (match_operand:HI 1 \"mra_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"mrai_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"\"\n-  \"@\n-   shl.w\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tshl.w\\tr1h,%0\"\n-  [(set_attr \"flags\" \"szc,szc\")]\n-  )\n-\n-\n-(define_expand \"ashlhi3\"\n-  [(parallel [(set (match_operand:HI 0 \"mra_operand\" \"\")\n-\t\t   (ashift:HI (match_operand:HI 1 \"mra_operand\" \"\")\n-\t\t\t      (match_operand:QI 2 \"general_operand\" \"\")))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, 1, ASHIFT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"ashrhi3\"\n-  [(parallel [(set (match_operand:HI 0 \"mra_operand\" \"\")\n-\t\t   (ashiftrt:HI (match_operand:HI 1 \"mra_operand\" \"\")\n-\t\t\t\t(neg:QI (match_operand:QI 2 \"general_operand\" \"\"))))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, -1, ASHIFTRT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"lshrhi3\"\n-  [(parallel [(set (match_operand:HI 0 \"mra_operand\" \"\")\n-\t\t   (lshiftrt:HI (match_operand:HI 1 \"mra_operand\" \"\")\n-\t\t\t\t(neg:QI (match_operand:QI 2 \"general_operand\" \"\"))))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, -1, LSHIFTRT))\n-     DONE;\"\n-  )\n-\n-\n-\n-\n-; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n-\n-\n-(define_insn \"ashlpsi3_i\"\n-  [(set (match_operand:PSI 0 \"mra_operand\" \"=R02RaaSd*Rmm,R02RaaSd*Rmm\")\n-\t(ashift:PSI (match_operand:PSI 1 \"mra_operand\" \"0,0\")\n-\t\t    (match_operand:QI 2 \"shiftcount_operand\" \"In4,RqiSd\")))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A24\"\n-  \"@\n-   sha.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.l\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"ashrpsi3_i\"\n-  [(set (match_operand:PSI 0 \"mra_operand\" \"=R02RaaSd*Rmm,R02RaaSd*Rmm\")\n-\t(ashiftrt:PSI (match_operand:PSI 1 \"mra_operand\" \"0,0\")\n-\t\t      (neg:QI (match_operand:QI 2 \"shiftcount_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A24\"\n-  \"@\n-   sha.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.l\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"lshrpsi3_i\"\n-  [(set (match_operand:PSI 0 \"mra_operand\" \"=R02RaaSd,??Rmm\")\n-\t(lshiftrt:PSI (match_operand:PSI 1 \"mra_operand\" \"0,0\")\n-\t\t      (neg:QI (match_operand:QI 2 \"shiftcount_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A24\"\n-  \"@\n-   shl.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tshl.l\\tr1h,%0\"\n-  [(set_attr \"flags\" \"szc,szc\")]\n-  )\n-\n-\n-(define_expand \"ashlpsi3\"\n-  [(parallel [(set (match_operand:PSI 0 \"mra_operand\" \"\")\n-\t\t   (ashift:PSI (match_operand:PSI 1 \"mra_operand\" \"\")\n-\t\t\t       (match_operand:QI 2 \"shiftcount_operand\" \"\")))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"TARGET_A24\"\n-  \"if (m32c_prepare_shift (operands, 1, ASHIFT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"ashrpsi3\"\n-  [(parallel [(set (match_operand:PSI 0 \"mra_operand\" \"\")\n-\t\t   (ashiftrt:PSI (match_operand:PSI 1 \"mra_operand\" \"\")\n-\t\t\t\t (neg:QI (match_operand:QI 2 \"shiftcount_operand\" \"\"))))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"TARGET_A24\"\n-  \"if (m32c_prepare_shift (operands, -1, ASHIFTRT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"lshrpsi3\"\n-  [(parallel [(set (match_operand:PSI 0 \"mra_operand\" \"\")\n-\t\t   (lshiftrt:PSI (match_operand:PSI 1 \"mra_operand\" \"\")\n-\t\t\t\t (neg:QI (match_operand:QI 2 \"shiftcount_operand\" \"\"))))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"TARGET_A24\"\n-  \"if (m32c_prepare_shift (operands, -1, LSHIFTRT))\n-     DONE;\"\n-  )\n-\n-; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n-\n-; The m16c has a maximum shift count of -16..16, even when in a\n-; register.  It's optimal to use multiple shifts of -8..8 rather than\n-; loading larger constants into R1H multiple time.  The m32c can shift\n-; -32..32 either via immediates or in registers.  Hence, separate\n-; patterns.\n-\n-\n-(define_insn \"ashlsi3_16\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R03,R03\")\n-\t(ashift:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-\t\t   (match_operand:QI 2 \"shiftcount_operand\" \"In4,RqiSd\")))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A16\"\n-  \"@\n-   sha.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.l\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"ashrsi3_16\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R03,R03\")\n-\t(ashiftrt:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"shiftcount_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A16\"\n-  \"@\n-   sha.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.l\\tr1h,%0\"\n-  [(set_attr \"flags\" \"oszc,oszc\")]\n-  )\n-\n-(define_insn \"lshrsi3_16\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R03,R03\")\n-\t(lshiftrt:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"shiftcount_operand\" \"In4,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A16\"\n-  \"@\n-   shl.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tshl.l\\tr1h,%0\"\n-  [(set_attr \"flags\" \"szc,szc\")]\n-  )\n-\n-\n-\n-(define_insn \"ashlsi3_24\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R03,R03\")\n-\t(ashift:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-\t\t   (match_operand:QI 2 \"longshiftcount_operand\" \"In6,RqiSd\")))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A24\"\n-  \"@\n-   sha.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.l\\tr1h,%0\"\n-  )\n-\n-(define_insn \"ashrsi3_24\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R03,R03\")\n-\t(ashiftrt:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"longshiftcount_operand\" \"In6,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A24\"\n-  \"@\n-   sha.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tsha.l\\tr1h,%0\"\n-  )\n-\n-(define_insn \"lshrsi3_24\"\n-  [(set (match_operand:SI 0 \"r0123_operand\" \"=R03,R03\")\n-\t(lshiftrt:SI (match_operand:SI 1 \"r0123_operand\" \"0,0\")\n-\t\t     (neg:QI (match_operand:QI 2 \"longshiftcount_operand\" \"In6,RqiSd\"))))\n-   (clobber (match_scratch:HI 3 \"=X,R1w\"))]\n-  \"TARGET_A24\"\n-  \"@\n-   shl.l\\t%2,%0\n-   mov.b\\t%2,r1h\\n\\tshl.l\\tr1h,%0\"\n-  )\n-\n-\n-\n-\n-(define_expand \"ashlsi3\"\n-  [(parallel [(set (match_operand:SI 0 \"r0123_operand\" \"\")\n-\t\t   (ashift:SI (match_operand:SI 1 \"r0123_operand\" \"\")\n-\t\t\t      (match_operand:QI 2 \"mrai_operand\" \"\")))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, 1, ASHIFT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"ashrsi3\"\n-  [(parallel [(set (match_operand:SI 0 \"r0123_operand\" \"\")\n-\t\t   (ashiftrt:SI (match_operand:SI 1 \"r0123_operand\" \"\")\n-\t\t\t\t(neg:QI (match_operand:QI 2 \"mrai_operand\" \"\"))))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, -1, ASHIFTRT))\n-     DONE;\"\n-  )\n-\n-(define_expand \"lshrsi3\"\n-  [(parallel [(set (match_operand:SI 0 \"r0123_operand\" \"\")\n-\t\t   (lshiftrt:SI (match_operand:SI 1 \"r0123_operand\" \"\")\n-\t\t\t\t(neg:QI (match_operand:QI 2 \"mrai_operand\" \"\"))))\n-\t      (clobber (match_scratch:HI 3 \"\"))])]\n-  \"\"\n-  \"if (m32c_prepare_shift (operands, -1, LSHIFTRT))\n-     DONE;\"\n-  )\ndiff --git a/gcc/config/m32c/t-m32c b/gcc/config/m32c/t-m32c\ndeleted file mode 100644\nindex b3431b7a31e..00000000000\n--- a/gcc/config/m32c/t-m32c\n+++ /dev/null\n@@ -1,42 +0,0 @@\n-# Target Makefile Fragment for R8C/M16C/M32C\n-# Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-# Contributed by Red Hat.\n-#\n-# This file is part of GCC.\n-#\n-# GCC is free software; you can redistribute it and/or modify it\n-# under the terms of the GNU General Public License as published\n-# by the Free Software Foundation; either version 3, or (at your\n-# option) any later version.\n-#\n-# GCC is distributed in the hope that it will be useful, but WITHOUT\n-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-# License for more details.\n-#\n-# You should have received a copy of the GNU General Public License\n-# along with GCC; see the file COPYING3.  If not see\n-# <http://www.gnu.org/licenses/>.\n-\n-# target-specific files\n-\n-md_file = $(srcdir)/common.md md\n-\n-MD_FILES = m32c constraints predicates addsub bitops blkmov cond jump minmax mov muldiv prologue shift\n-\n-# Doing it this way lets the gen* programs report the right line numbers.\n-\n-md : $(MD_FILES:%=$(srcdir)/config/m32c/%.md) $(srcdir)/config/m32c/t-m32c\n-\tfor md in $(MD_FILES); do \\\n-\t  echo \"(include \\\"$(srcdir)/config/m32c/$$md.md\\\")\"; \\\n-\tdone > md\n-\n-m32c-pragma.o: $(srcdir)/config/m32c/m32c-pragma.cc $(RTL_H) $(TREE_H) $(CONFIG_H) $(TM_H)\n-\t$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<\n-\n-# We support four CPU series, but R8C and M16C share one multilib, and\n-# M32C and M32CM share another.\n-\n-MULTILIB_OPTIONS = mcpu=m32cm\n-MULTILIB_DIRNAMES = m32cm\n-MULTILIB_MATCHES = mcpu?m32cm=mcpu?m32c mcpu?r8c=mcpu?m16c\ndiff --git a/gcc/config/microblaze/microblaze.opt.urls b/gcc/config/microblaze/microblaze.opt.urls\nindex a62891a65c5..122bf3514a5 100644\n--- a/gcc/config/microblaze/microblaze.opt.urls\n+++ b/gcc/config/microblaze/microblaze.opt.urls\n@@ -10,7 +10,7 @@ msmall-divides\n UrlSuffix(gcc/MicroBlaze-Options.html#index-msmall-divides)\n \n mcpu=\n-UrlSuffix(gcc/MicroBlaze-Options.html#index-mcpu_003d-3)\n+UrlSuffix(gcc/MicroBlaze-Options.html#index-mcpu_003d-2)\n \n mmemcpy\n UrlSuffix(gcc/MicroBlaze-Options.html#index-mmemcpy-1)\ndiff --git a/gcc/config/msp430/msp430.cc b/gcc/config/msp430/msp430.cc\nindex a9e565e9e58..d78430f9368 100644\n--- a/gcc/config/msp430/msp430.cc\n+++ b/gcc/config/msp430/msp430.cc\n@@ -3165,8 +3165,7 @@ msp430_expand_epilogue (int is_eh)\n   emit_jump_insn (gen_msp430_return ());\n }\n \n-/* Implements EH_RETURN_STACKADJ_RTX.  Saved and used later in\n-   m32c_emit_eh_epilogue.  */\n+/* Implements EH_RETURN_STACKADJ_RTX.  */\n rtx\n msp430_eh_return_stackadj_rtx (void)\n {\ndiff --git a/gcc/config/msp430/msp430.opt.urls b/gcc/config/msp430/msp430.opt.urls\nindex 88791fe28e6..b08d0ef0228 100644\n--- a/gcc/config/msp430/msp430.opt.urls\n+++ b/gcc/config/msp430/msp430.opt.urls\n@@ -1,7 +1,7 @@\n ; Autogenerated by regenerate-opt-urls.py from gcc/config/msp430/msp430.opt and generated HTML\n \n msim\n-UrlSuffix(gcc/MSP430-Options.html#index-msim-5)\n+UrlSuffix(gcc/MSP430-Options.html#index-msim-4)\n \n mtiny-printf\n UrlSuffix(gcc/MSP430-Options.html#index-mtiny-printf)\ndiff --git a/gcc/config/nds32/nds32.opt.urls b/gcc/config/nds32/nds32.opt.urls\nindex 6f81b46161a..4250942ae09 100644\n--- a/gcc/config/nds32/nds32.opt.urls\n+++ b/gcc/config/nds32/nds32.opt.urls\n@@ -76,7 +76,7 @@ march=\n UrlSuffix(gcc/NDS32-Options.html#index-march_003d-1)\n \n mcpu=\n-UrlSuffix(gcc/NDS32-Options.html#index-mcpu_003d-4)\n+UrlSuffix(gcc/NDS32-Options.html#index-mcpu_003d-3)\n \n mconfig-fpu=\n UrlSuffix(gcc/NDS32-Options.html#index-mconfig-fpu_003d)\ndiff --git a/gcc/config/rl78/rl78.opt.urls b/gcc/config/rl78/rl78.opt.urls\nindex 18e0f0421d6..41539afb961 100644\n--- a/gcc/config/rl78/rl78.opt.urls\n+++ b/gcc/config/rl78/rl78.opt.urls\n@@ -1,7 +1,7 @@\n ; Autogenerated by regenerate-opt-urls.py from gcc/config/rl78/rl78.opt and generated HTML\n \n msim\n-UrlSuffix(gcc/RL78-Options.html#index-msim-6)\n+UrlSuffix(gcc/RL78-Options.html#index-msim-5)\n \n mmul=\n UrlSuffix(gcc/RL78-Options.html#index-mmul-1)\ndiff --git a/gcc/config/rs6000/sysv4.opt.urls b/gcc/config/rs6000/sysv4.opt.urls\nindex 5ed170ea892..223ddc5bf71 100644\n--- a/gcc/config/rs6000/sysv4.opt.urls\n+++ b/gcc/config/rs6000/sysv4.opt.urls\n@@ -48,7 +48,7 @@ msdata\n UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-msdata-3)\n \n msim\n-UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-msim-7)\n+UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-msim-6)\n \n mads\n UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mads)\ndiff --git a/gcc/config/rx/elf.opt.urls b/gcc/config/rx/elf.opt.urls\nindex c43973a9d49..fcfb915edc7 100644\n--- a/gcc/config/rx/elf.opt.urls\n+++ b/gcc/config/rx/elf.opt.urls\n@@ -1,7 +1,7 @@\n ; Autogenerated by regenerate-opt-urls.py from gcc/config/rx/elf.opt and generated HTML\n \n msim\n-UrlSuffix(gcc/RX-Options.html#index-msim-8)\n+UrlSuffix(gcc/RX-Options.html#index-msim-7)\n \n mas100-syntax\n UrlSuffix(gcc/RX-Options.html#index-mas100-syntax)\ndiff --git a/gcc/config/stormy16/stormy16.opt.urls b/gcc/config/stormy16/stormy16.opt.urls\nindex 6f47d4c5c18..abbd926722f 100644\n--- a/gcc/config/stormy16/stormy16.opt.urls\n+++ b/gcc/config/stormy16/stormy16.opt.urls\n@@ -1,5 +1,5 @@\n ; Autogenerated by regenerate-opt-urls.py from gcc/config/stormy16/stormy16.opt and generated HTML\n \n msim\n-UrlSuffix(gcc/Xstormy16-Options.html#index-msim-10)\n+UrlSuffix(gcc/Xstormy16-Options.html#index-msim-9)\n \ndiff --git a/gcc/config/visium/visium.opt.urls b/gcc/config/visium/visium.opt.urls\nindex 80c9bd5e2ac..47f4b7c20cf 100644\n--- a/gcc/config/visium/visium.opt.urls\n+++ b/gcc/config/visium/visium.opt.urls\n@@ -4,7 +4,7 @@ mdebug\n UrlSuffix(gcc/Visium-Options.html#index-mdebug-2)\n \n msim\n-UrlSuffix(gcc/Visium-Options.html#index-msim-9)\n+UrlSuffix(gcc/Visium-Options.html#index-msim-8)\n \n mfpu\n UrlSuffix(gcc/Visium-Options.html#index-mfpu-5)\ndiff --git a/gcc/configure b/gcc/configure\nindex ef780a23c2f..a5c078e13ac 100755\n--- a/gcc/configure\n+++ b/gcc/configure\n@@ -31852,7 +31852,7 @@ esac\n # ??? Once 2.11 is released, probably need to add first known working\n # version to the per-target configury.\n case \"$cpu_type\" in\n-  aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | m32c \\\n+  aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch \\\n   | m68k | microblaze | mips | nds32 | pa | riscv | rs6000 | score | sparc \\\n   | visium | xstormy16 | xtensa | ft32)\n     insn=\"nop\"\ndiff --git a/gcc/configure.ac b/gcc/configure.ac\nindex cdf2997cb5f..90a22f7e7f1 100644\n--- a/gcc/configure.ac\n+++ b/gcc/configure.ac\n@@ -5629,7 +5629,7 @@ esac\n # ??? Once 2.11 is released, probably need to add first known working\n # version to the per-target configury.\n case \"$cpu_type\" in\n-  aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | m32c \\\n+  aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch \\\n   | m68k | microblaze | mips | nds32 | pa | riscv | rs6000 | score | sparc \\\n   | visium | xstormy16 | xtensa | ft32)\n     insn=\"nop\"\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 47e0865c676..c9c4afd3c2b 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -1379,7 +1379,7 @@ As an extension, GNU C supports named address spaces as\n defined in the N1275 draft of ISO/IEC DTR 18037.  Support for named\n address spaces in GCC will evolve as the draft technical report\n changes.  Calling conventions for any target might also change.  At\n-present, only the AVR, M32C, PRU, RL78, and x86 targets support\n+present, only the AVR, PRU, RL78, and x86 targets support\n address spaces other than the generic address space.\n \n Address space identifiers may be used exactly like any other C type\n@@ -1558,15 +1558,6 @@ Attribute @code{progmem} is supported but works differently.\n \n @end itemize\n \n-@subsection M32C Named Address Spaces\n-@cindex @code{__far} M32C Named Address Spaces\n-\n-On the M32C target, with the R8C and M16C CPU variants, variables\n-qualified with @code{__far} are accessed using 32-bit addresses in\n-order to access memory beyond the first 64@tie{}Ki bytes.  If\n-@code{__far} is used with the M32CM or M32C CPU variants, it has no\n-effect.\n-\n @subsection PRU Named Address Spaces\n @cindex @code{__regio_symbol} PRU Named Address Spaces\n \n@@ -5709,7 +5700,6 @@ The default for the attribute is controlled by @option{-fzero-call-used-regs}.\n * H8/300 Attributes::\n * IA-64 Attributes::\n * LoongArch Attributes::\n-* M32C Attributes::\n * M32R/D Attributes::\n * m68k Attributes::\n * MicroBlaze Attributes::\n@@ -7383,78 +7373,6 @@ specially.  Currently the only supported values of @var{name} are\n @code{normal} and @code{extreme}.\n @end table\n \n-@anchor{M32C Function Attributes}\n-@node M32C Attributes\n-@subsubsection M32C Attributes\n-\n-These attributes are supported by the M32C back end:\n-\n-@table @code\n-@atindex @code{bank_switch}, M32C\n-@item bank_switch\n-This attribute applies to functions.\n-\n-When added to an interrupt handler with the M32C port, causes the\n-prologue and epilogue to use bank switching to preserve the registers\n-rather than saving them on the stack.\n-\n-@atindex @code{fast_interrupt}, M32C\n-@item fast_interrupt\n-This attribute applies to functions.\n-\n-Use this attribute on the M32C port to indicate that the specified\n-function is a fast interrupt handler.  This is just like the\n-@code{interrupt} attribute, except that @code{freit} is used to return\n-instead of @code{reit}.\n-\n-@atindex @code{function_vector}, M16C/M32C\n-@item function_vector\n-This attribute applies to functions.\n-\n-On M16C/M32C targets, the @code{function_vector} attribute declares a\n-special page subroutine call function. Use of this attribute reduces\n-the code size by 2 bytes for each call generated to the\n-subroutine. The argument to the attribute is the vector number entry\n-from the special page vector table which contains the 16 low-order\n-bits of the subroutine's entry address. Each vector table has special\n-page number (18 to 255) that is used in @code{jsrs} instructions.\n-Jump addresses of the routines are generated by adding 0x0F0000 (in\n-case of M16C targets) or 0xFF0000 (in case of M32C targets), to the\n-2-byte addresses set in the vector table. Therefore you need to ensure\n-that all the special page vector routines should get mapped within the\n-address range 0x0F0000 to 0x0FFFFF (for M16C) and 0xFF0000 to 0xFFFFFF\n-(for M32C).\n-\n-In the following example 2 bytes are saved for each call to\n-function @code{foo}.\n-\n-@smallexample\n-void foo (void) __attribute__((function_vector(0x18)));\n-void foo (void)\n-@{\n-@}\n-\n-void bar (void)\n-@{\n-    foo();\n-@}\n-@end smallexample\n-\n-If functions are defined in one file and are called in another file,\n-then be sure to write this declaration in both files.\n-\n-This attribute is ignored for R8C target.\n-\n-@atindex @code{interrupt}, M32C\n-@item interrupt\n-This attribute applies to functions.\n-\n-It indicates\n-that the specified function is an interrupt handler.  The compiler generates\n-function entry and exit sequences suitable for use in an interrupt handler\n-when this attribute is present.\n-@end table\n-\n @anchor{M32R/D Function Attributes}\n @anchor{M32R/D Variable Attributes}\n @node M32R/D Attributes\n@@ -10094,7 +10012,6 @@ option is specified.  @xref{OpenMP}, and @ref{OpenACC}.\n * AArch64 Pragmas::\n * ARM Pragmas::\n * LoongArch Pragmas::\n-* M32C Pragmas::\n * PRU Pragmas::\n * RS/6000 and PowerPC Pragmas::\n * S/390 Pragmas::\n@@ -10158,36 +10075,6 @@ Example:\n #pragma GCC target(\"strict-align\")\n @end smallexample\n \n-@node M32C Pragmas\n-@subsection M32C Pragmas\n-\n-@table @code\n-@cindex pragma, memregs\n-@item GCC memregs @var{number}\n-Overrides the command-line option @code{-memregs=} for the current\n-file.  Use with care!  This pragma must be before any function in the\n-file, and mixing different memregs values in different objects may\n-make them incompatible.  This pragma is useful when a\n-performance-critical function uses a memreg for temporary values,\n-as it may allow you to reduce the number of memregs used.\n-\n-@cindex pragma, address\n-@item ADDRESS @var{name} @var{address}\n-For any declared symbols matching @var{name}, this does three things\n-to that symbol: it forces the symbol to be located at the given\n-address (a number), it forces the symbol to be volatile, and it\n-changes the symbol's scope to be static.  This pragma exists for\n-compatibility with other compilers, but note that the common\n-@code{1234H} numeric syntax is not supported (use @code{0x1234}\n-instead).  Example:\n-\n-@smallexample\n-#pragma ADDRESS port3 0x103\n-char port3;\n-@end smallexample\n-\n-@end table\n-\n @node PRU Pragmas\n @subsection PRU Pragmas\n \ndiff --git a/gcc/doc/install.texi b/gcc/doc/install.texi\nindex 001d16fe67a..c54d487e834 100644\n--- a/gcc/doc/install.texi\n+++ b/gcc/doc/install.texi\n@@ -872,7 +872,7 @@ Here are the possible CPU types:\n @quotation\n aarch64, aarch64_be, alpha, alpha64, amdgcn, arc, arceb, arm, armeb, avr, bfin,\n bpf, cris, csky, epiphany, fido, fr30, frv, ft32, h8300, hppa, hppa2.0,\n-hppa64, i486, i686, ia64, iq2000, lm32, loongarch64, m32c, m32r, m32rle, m68k,\n+hppa64, i486, i686, ia64, iq2000, lm32, loongarch64, m32r, m32rle, m68k,\n mcore, microblaze, microblazeel, mips, mips64, mips64el, mips64octeon,\n mips64orion, mips64vr, mipsel, mipsisa32, mipsisa32r2, mipsisa64, mipsisa64r2,\n mipsisa64r2el, mipsisa64sb1, mipsisa64sr71k, mipstx39, mmix, mn10300, moxie,\n@@ -3999,8 +3999,6 @@ information have to.\n @item\n @uref{#lm32-x-uclinux,,lm32-*-uclinux}\n @item\n-@uref{#m32c-x-elf,,m32c-*-elf}\n-@item\n @uref{#m32r-x-elf,,m32r-*-elf}\n @item\n @uref{#m68k-x-x,,m68k-*-*}\n@@ -4618,14 +4616,6 @@ Same as @code{loongarch64-linux-gnuf64} for legacy support.\n More information about LoongArch can be found at\n @uref{https://github.com/loongson/LoongArch-Documentation}.\n \n-@html\n-<hr />\n-@end html\n-@anchor{m32c-x-elf}\n-@heading m32c-*-elf\n-Renesas M32C processor.\n-This configuration is intended for embedded systems.\n-\n @html\n <hr />\n @end html\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 9207a021e64..8610c4c3c88 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -1174,9 +1174,6 @@ Objective-C and Objective-C++ Dialects}.\n @emph{LynxOS Options} (@ref{LynxOS Options})\n @gccoptlist{-mshared  -mthreads  -mlegacy-threads}\n \n-@emph{M32C Options} (@ref{M32C Options})\n-@gccoptlist{-mcpu=@var{cpu}  -msim  -memregs=@var{number}}\n-\n @emph{M32R/D Options} (@ref{M32R/D Options})\n @gccoptlist{-m32r2  -m32rx  -m32r\n -mdebug\n@@ -21191,7 +21188,6 @@ other compilers on the same platform.\n * LM32 Options::\n * LoongArch Options::\n * LynxOS Options::\n-* M32C Options::\n * M32R/D Options::\n * M680x0 Options::\n * MCore Options::\n@@ -27966,39 +27962,6 @@ Support legacy multi-threading.\n This option is incompatible with @option{-mthreads}.\n @end table\n \n-@node M32C Options\n-@subsection M32C Options\n-@cindex M32C options\n-\n-@table @gcctabopt\n-@opindex mcpu=\n-@item -mcpu=@var{name}\n-Select the CPU for which code is generated.  @var{name} may be one of\n-@samp{r8c} for the R8C/Tiny series, @samp{m16c} for the M16C (up to\n-/60) series, @samp{m32cm} for the M16C/80 series, or @samp{m32c} for\n-the M32C/80 series.\n-\n-@opindex msim\n-@opindex mno-sim\n-@item -msim\n-Specifies that the program will be run on the simulator.  This causes\n-an alternate runtime library to be linked in which supports, for\n-example, file I/O@.  You must not use this option when generating\n-programs that will run on real hardware; you must provide your own\n-runtime library for whatever I/O functions are needed.\n-\n-@opindex memregs=\n-@item -memregs=@var{number}\n-Specifies the number of memory-based pseudo-registers GCC uses\n-during code generation.  These pseudo-registers are used like real\n-registers, so there is a tradeoff between GCC's ability to fit the\n-code into available registers, and the performance penalty of using\n-memory instead of registers.  Note that all modules in a program must\n-be compiled with the same value for this option.  Because of that, you\n-must not use this option with GCC's default runtime libraries.\n-\n-@end table\n-\n @node M32R/D Options\n @subsection M32R/D Options\n @cindex M32R/D options\ndiff --git a/gcc/doc/md.texi b/gcc/doc/md.texi\nindex 6af646e3e01..c4fc53458d9 100644\n--- a/gcc/doc/md.texi\n+++ b/gcc/doc/md.texi\n@@ -2782,135 +2782,6 @@ now roughly the same as @samp{m} when not used together with @samp{<}\n or @samp{>}.\n @end table\n \n-@item M32C---@file{config/m32c/m32c.cc}\n-@table @code\n-@item Rsp\n-@itemx Rfb\n-@itemx Rsb\n-@samp{$sp}, @samp{$fb}, @samp{$sb}.\n-\n-@item Rcr\n-Any control register, when they're 16 bits wide (nothing if control\n-registers are 24 bits wide)\n-\n-@item Rcl\n-Any control register, when they're 24 bits wide.\n-\n-@item R0w\n-@itemx R1w\n-@itemx R2w\n-@itemx R3w\n-$r0, $r1, $r2, $r3.\n-\n-@item R02\n-$r0 or $r2, or $r2r0 for 32 bit values.\n-\n-@item R13\n-$r1 or $r3, or $r3r1 for 32 bit values.\n-\n-@item Rdi\n-A register that can hold a 64 bit value.\n-\n-@item Rhl\n-$r0 or $r1 (registers with addressable high/low bytes)\n-\n-@item R23\n-$r2 or $r3\n-\n-@item Raa\n-Address registers\n-\n-@item Raw\n-Address registers when they're 16 bits wide.\n-\n-@item Ral\n-Address registers when they're 24 bits wide.\n-\n-@item Rqi\n-Registers that can hold QI values.\n-\n-@item Rad\n-Registers that can be used with displacements ($a0, $a1, $sb).\n-\n-@item Rsi\n-Registers that can hold 32 bit values.\n-\n-@item Rhi\n-Registers that can hold 16 bit values.\n-\n-@item Rhc\n-Registers chat can hold 16 bit values, including all control\n-registers.\n-\n-@item Rra\n-$r0 through R1, plus $a0 and $a1.\n-\n-@item Rfl\n-The flags register.\n-\n-@item Rmm\n-The memory-based pseudo-registers $mem0 through $mem15.\n-\n-@item Rpi\n-Registers that can hold pointers (16 bit registers for r8c, m16c; 24\n-bit registers for m32cm, m32c).\n-\n-@item Rpa\n-Matches multiple registers in a PARALLEL to form a larger register.\n-Used to match function return values.\n-\n-@item Is3\n-@minus{}8 @dots{} 7\n-\n-@item IS1\n-@minus{}128 @dots{} 127\n-\n-@item IS2\n-@minus{}32768 @dots{} 32767\n-\n-@item IU2\n-0 @dots{} 65535\n-\n-@item In4\n-@minus{}8 @dots{} @minus{}1 or 1 @dots{} 8\n-\n-@item In5\n-@minus{}16 @dots{} @minus{}1 or 1 @dots{} 16\n-\n-@item In6\n-@minus{}32 @dots{} @minus{}1 or 1 @dots{} 32\n-\n-@item IM2\n-@minus{}65536 @dots{} @minus{}1\n-\n-@item Ilb\n-An 8 bit value with exactly one bit set.\n-\n-@item Ilw\n-A 16 bit value with exactly one bit set.\n-\n-@item Sd\n-The common src/dest memory addressing modes.\n-\n-@item Sa\n-Memory addressed using $a0 or $a1.\n-\n-@item Si\n-Memory addressed with immediate addresses.\n-\n-@item Ss\n-Memory addressed using the stack pointer ($sp).\n-\n-@item Sf\n-Memory addressed using the frame base register ($fb).\n-\n-@item Ss\n-Memory addressed using the small base register ($sb).\n-\n-@item S1\n-$r1h\n-@end table\n-\n @item LoongArch---@file{config/loongarch/constraints.md}\n @table @code\n @item f\ndiff --git a/gcc/explow.cc b/gcc/explow.cc\nindex 2d228d199e9..755c1d2e6dc 100644\n--- a/gcc/explow.cc\n+++ b/gcc/explow.cc\n@@ -898,7 +898,7 @@ promote_mode (const_tree type ATTRIBUTE_UNUSED, machine_mode mode,\n \n   /* FIXME: this is the same logic that was there until GCC 4.4, but we\n      probably want to test POINTERS_EXTEND_UNSIGNED even if PROMOTE_MODE\n-     is not defined.  The affected targets are M32C, S390, SPARC.  */\n+     is not defined.  The affected targets are S390, SPARC.  */\n #ifdef PROMOTE_MODE\n   code = TREE_CODE (type);\n   unsignedp = *punsignedp;\ndiff --git a/gcc/regenerate-opt-urls.py b/gcc/regenerate-opt-urls.py\nindex 967968ece68..bd28d9c0b0f 100755\n--- a/gcc/regenerate-opt-urls.py\n+++ b/gcc/regenerate-opt-urls.py\n@@ -245,7 +245,6 @@ TARGET_SPECIFIC_PAGES = {\n     'gcc/HPPA-Options.html' : 'gcc/config/pa/',\n     'gcc/IA-64-Options.html' : 'gcc/config/ia64/',\n     'gcc/LoongArch-Options.html' : 'gcc/config/loongarch/',\n-    'gcc/M32C-Options.html' : 'gcc/config/m32c/',\n     'gcc/M32R_002fD-Options.html' : 'gcc/config/m32r/',\n     'gcc/M680x0-Options.html' : 'gcc/config/m68k/',\n     'gcc/MCore-Options.html' : 'gcc/config/mcore/',\ndiff --git a/gcc/testsuite/gcc.c-torture/compile/20000804-1.c b/gcc/testsuite/gcc.c-torture/compile/20000804-1.c\nindex c6f6497b7a7..6fddddf1149 100644\n--- a/gcc/testsuite/gcc.c-torture/compile/20000804-1.c\n+++ b/gcc/testsuite/gcc.c-torture/compile/20000804-1.c\n@@ -2,7 +2,6 @@\n    statement to force a 'long long' (64-bits) to go in a register.  */\n /* { dg-do assemble } */\n /* { dg-skip-if \"\" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } } */\n-/* { dg-skip-if \"No 64-bit registers\" { m32c-*-* } } */\n /* { dg-skip-if \"Not enough 64-bit registers\" { pdp11-*-* } { \"-O0\" } { \"\" } } */\n /* { dg-xfail-if \"Inconsistent constraint on asm\" { csky-*-* } { \"-O0\" } { \"\" } } */\n /* { dg-xfail-if \"Inconsistent constraint on asm\" { bpf-*-* } { \"-O0\" } { \"\" } } */\ndiff --git a/gcc/testsuite/gcc.c-torture/compile/20001226-1.c b/gcc/testsuite/gcc.c-torture/compile/20001226-1.c\nindex 234cdbf1b14..ce92bfb6ee9 100644\n--- a/gcc/testsuite/gcc.c-torture/compile/20001226-1.c\n+++ b/gcc/testsuite/gcc.c-torture/compile/20001226-1.c\n@@ -1,7 +1,6 @@\n /* { dg-do assemble } */\n /* { dg-skip-if \"too much code for avr\" { \"avr-*-*\" } } */\n /* { dg-skip-if \"too much code for pdp11\" { \"pdp11-*-*\" } } */\n-/* { dg-skip-if \"\" { m32c-*-* } } */\n /* { dg-skip-if \"jumps too far for eBPF\" { bpf-*-* } } */\n /* { dg-timeout-factor 4.0 } */\n \ndiff --git a/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c b/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c\nindex 0828fc35aef..4b80b632d9f 100644\n--- a/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c\n+++ b/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c\n@@ -1,4 +1,4 @@\n-/* { dg-skip-if \"Array too big\" { avr-*-* m32c-*-* pdp11-*-* msp430-*-* } } */ \n+/* { dg-skip-if \"Array too big\" { avr-*-* pdp11-*-* msp430-*-* } } */ \n \n #define STR2 \"012345678901234567890123456789012345678901234567890123456789\\\n 0123456789012345678901234567890123456789\"\ndiff --git a/gcc/testsuite/gcc.c-torture/execute/20020404-1.c b/gcc/testsuite/gcc.c-torture/execute/20020404-1.c\nindex 95b0adc0244..1ca679afa21 100644\n--- a/gcc/testsuite/gcc.c-torture/execute/20020404-1.c\n+++ b/gcc/testsuite/gcc.c-torture/execute/20020404-1.c\n@@ -1,6 +1,5 @@\n /* { dg-require-effective-target int32plus } */\n /* { dg-additional-options \"-std=gnu17\" } */\n-/* { dg-skip-if \"pointers can be truncated\" { m32c-*-* } } */\n /* Extracted from GDB sources. */\n \n void abort (void);\ndiff --git a/gcc/testsuite/gcc.dg/20020312-2.c b/gcc/testsuite/gcc.dg/20020312-2.c\nindex 16a04c17ba9..1764062a7b6 100644\n--- a/gcc/testsuite/gcc.dg/20020312-2.c\n+++ b/gcc/testsuite/gcc.dg/20020312-2.c\n@@ -95,8 +95,6 @@ extern void abort (void);\n # define PIC_REG  \"r12\"\n #elif defined(__x86_64__)\n /* No pic register.  */\n-#elif defined(__m32c__)\n-/* No pic register.  */\n #elif defined (__frv__)\n # ifdef __FRV_FDPIC__\n #  define PIC_REG \"gr15\"\ndiff --git a/gcc/testsuite/gcc.dg/max-1.c b/gcc/testsuite/gcc.dg/max-1.c\nindex 9823dca597e..d4f68261bcf 100644\n--- a/gcc/testsuite/gcc.dg/max-1.c\n+++ b/gcc/testsuite/gcc.dg/max-1.c\n@@ -4,8 +4,6 @@\n /* { dg-options \"-O1 \" } */\n /* Option -fno-tree-lrs removed By Andrew MacLeod since it is no longer \n    supported in the compiler beginning with GCC 4.3.  */\n-/* m32c has varying sized pointers */\n-/* { dg-skip-if \"\" { \"m32c-*-*\" } { \"*\" } { \"-mcpu=m32c\" \"-mcpu=m32cm\" } } */\n \n __extension__ typedef __INTPTR_TYPE__ intptr_t;\n \ndiff --git a/gcc/testsuite/gcc.dg/torture/pr26565.c b/gcc/testsuite/gcc.dg/torture/pr26565.c\nindex 12332d4f6ed..6b7bde169c8 100644\n--- a/gcc/testsuite/gcc.dg/torture/pr26565.c\n+++ b/gcc/testsuite/gcc.dg/torture/pr26565.c\n@@ -1,6 +1,4 @@\n /* { dg-do run } */\n-/* m32c is already packed.  */\n-/* { dg-skip-if \"\" { \"m32c-*-*\" } } */\n \n void *memcpy(void *dest, const void *src, __SIZE_TYPE__ n);\n \ndiff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-32.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-32.c\nindex 545f316bebd..2a73cf7b963 100644\n--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-32.c\n+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-32.c\n@@ -1,4 +1,4 @@\n-/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*\"} } } */\n+/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*\"} } } */\n \n /* { dg-options \"-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1 -fno-bit-tests\" } */\n /* { dg-additional-options \"-mbranch-cost=2\" { target branch_cost } } */\ndiff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c\nindex a89e0689e7b..f44754ca970 100644\n--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c\n+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c\n@@ -1,4 +1,4 @@\n-/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k-*-*-* pru*-*-*\"} } } */\n+/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k-*-*-* pru*-*-*\"} } } */\n \n /* { dg-options \"-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1\" } */\n /* { dg-additional-options \"-mbranch-cost=2\" { target branch_cost } } */\ndiff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c\nindex 1c4041b7484..dfa6d51b35a 100644\n--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c\n+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c\n@@ -1,4 +1,4 @@\n-/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*\"} } } */\n+/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*\"} } } */\n \n /* { dg-options \"-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1\" } */\n /* { dg-additional-options \"-mbranch-cost=2\" { target branch_cost } } */\ndiff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c\nindex a81846c1722..3813cbac65b 100644\n--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c\n+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c\n@@ -1,4 +1,4 @@\n-/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*\"} } } */\n+/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*\"} } } */\n \n /* { dg-options \"-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1\" } */\n /* { dg-additional-options \"-mbranch-cost=2\" { target branch_cost } } */\ndiff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c\nindex a0489b9c4f7..83a1e258046 100644\n--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c\n+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c\n@@ -1,4 +1,4 @@\n-/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*\"} } } */\n+/* { dg-do run { target { ! \"m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*\"} } } */\n \n /* { dg-options \"-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1\" } */\n /* { dg-additional-options \"-mbranch-cost=2\" { target branch_cost } } */\ndiff --git a/gcc/testsuite/gcc.dg/utf-array-short-wchar.c b/gcc/testsuite/gcc.dg/utf-array-short-wchar.c\nindex 81b452a33a1..c286f270720 100644\n--- a/gcc/testsuite/gcc.dg/utf-array-short-wchar.c\n+++ b/gcc/testsuite/gcc.dg/utf-array-short-wchar.c\n@@ -35,9 +35,9 @@ const char32_t\ts32_4[]\t= u8\"ab\";\t/* { dg-error \"from a string literal with type\n \n const char32_t\ts32_5[0] = U\"ab\";\t/* { dg-warning \" is too long\" } */\n const char32_t\ts32_6[1] = U\"ab\";\t/* { dg-warning \" is too long\" } */\n-const char32_t\ts32_7[2] = U\"ab\";\t/* { dg-warning \" is too long\" \"\" { target \"m32c-*-*\" } } */\n-const char32_t\ts32_8[3] = U\"ab\";\t/* { dg-warning \" is too long\" \"\" { target \"m32c-*-*\" } } */\n-const char32_t\ts32_9[4] = U\"ab\";\t/* { dg-warning \" is too long\" \"\" { target \"m32c-*-*\" } } */\n+const char32_t\ts32_7[2] = U\"ab\";\n+const char32_t\ts32_8[3] = U\"ab\";\n+const char32_t\ts32_9[4] = U\"ab\";\n \n const wchar_t\tsw_0[]\t= \"ab\";\t\t/* { dg-error \"from a string literal with type array of .char.\" } */\n const wchar_t\tsw_1[]\t= u\"ab\";\ndiff --git a/gcc/testsuite/gcc.dg/utf-array.c b/gcc/testsuite/gcc.dg/utf-array.c\nindex 7f0cb915e04..0e8024901d9 100644\n--- a/gcc/testsuite/gcc.dg/utf-array.c\n+++ b/gcc/testsuite/gcc.dg/utf-array.c\n@@ -35,9 +35,9 @@ const char32_t\ts32_4[]\t= u8\"ab\";\t/* { dg-error \"from a string literal with type\n \n const char32_t\ts32_5[0] = U\"ab\";\t/* { dg-warning \" is too long\" } */\n const char32_t\ts32_6[1] = U\"ab\";\t/* { dg-warning \" is too long\" } */\n-const char32_t\ts32_7[2] = U\"ab\";\t/* { dg-warning \" is too long\" \"\" { target \"m32c-*-*\" } } */\n-const char32_t\ts32_8[3] = U\"ab\";\t/* { dg-warning \" is too long\" \"\" { target \"m32c-*-*\" } } */\n-const char32_t\ts32_9[4] = U\"ab\";\t/* { dg-warning \" is too long\" \"\" { target \"m32c-*-*\" } } */\n+const char32_t\ts32_7[2] = U\"ab\";\n+const char32_t\ts32_8[3] = U\"ab\";\n+const char32_t\ts32_9[4] = U\"ab\";\n \n const wchar_t\tsw_0[]\t= \"ab\";\t\t/* { dg-error \"from a string literal with type array of .char.\" } */\n const wchar_t\tsw_1[]\t= u\"ab\";\t/* { dg-error \"from a string literal with type array of\" \"\" { target { ! wchar_t_char16_t_compatible } } } */\ndiff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex 55775d036cd..ee06aa05f29 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -670,7 +670,6 @@ proc check_effective_target_variadic_mi_thunk { } {\n \t || [istarget h8300-*-*]\n \t || [istarget iq2000-*-*]\n \t || [istarget lm32-*-*]\n-\t || [istarget m32c-*-*]\n \t || [istarget m32r-*-*]\n \t || [istarget mcore-*-*]\n \t || [istarget moxie-*-*]\n@@ -860,7 +859,6 @@ proc check_profiling_available { test_what } {\n \t     || [istarget fido-*-elf]\n \t     || [istarget h8300-*-*]\n \t     || [istarget lm32-*-*]\n-\t     || [istarget m32c-*-elf]\n \t     || [istarget m68k-*-elf]\n \t     || [istarget m68k-*-uclinux*]\n \t     || [istarget mips*-*-elf*]\n@@ -9218,7 +9216,6 @@ proc check_effective_target_natural_alignment_32 { } {\n \t   || [istarget rl78-*-*]\n \t   || [istarget pdp11-*-*]\n \t   || [istarget msp430-*-*]\n-\t   || [istarget m32c-*-*]\n \t   || [istarget cris-*-*] } {\n \t   return 0\n \t } else {\ndiff --git a/libgcc/config.host b/libgcc/config.host\nindex ac10ccc4340..f97340481a0 100644\n--- a/libgcc/config.host\n+++ b/libgcc/config.host\n@@ -81,10 +81,6 @@ unwind_header=unwind-generic.h\n # Set default cpu_type so it can be updated in each machine entry.\n cpu_type=`echo ${host} | sed 's/-.*$//'`\n case ${host} in\n-m32c*-*-*)\n-        cpu_type=m32c\n-\ttmake_file=t-fdpbit\n-        ;;\n aarch64*-*-*)\n \tcpu_type=aarch64\n \t;;\n@@ -1567,9 +1563,6 @@ am33_2.0-*-linux*)\n \textra_parts=\"crtbegin.o crtend.o crtbeginS.o crtendS.o\"\n \ttmake_file=\"$tmake_file t-fdpbit\"\n \t;;\n-m32c-*-elf*)\n-\ttmake_file=\"$tmake_file m32c/t-m32c\"\n- \t;;\n nvptx-*)\n \ttmake_file=\"$tmake_file nvptx/t-nvptx\"\n \textra_parts=\"crt0.o\"\ndiff --git a/libgcc/config/m32c/lib1funcs.S b/libgcc/config/m32c/lib1funcs.S\ndeleted file mode 100644\nindex f60cdc9eb86..00000000000\n--- a/libgcc/config/m32c/lib1funcs.S\n+++ /dev/null\n@@ -1,230 +0,0 @@\n-/* libgcc routines for R8C/M16C/M32C\n-   Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   Under Section 7 of GPL version 3, you are granted additional\n-   permissions described in the GCC Runtime Library Exception, version\n-   3.1, as published by the Free Software Foundation.\n-\n-   You should have received a copy of the GNU General Public License and\n-   a copy of the GCC Runtime Library Exception along with this program;\n-   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-#if defined(__r8c_cpu__) || defined(__m16c_cpu__)\n-#define A16\n-#define A(n,w) n\n-#define W w\n-#else\n-#define A24\n-#define A(n,w) w\n-#define W l\n-#endif\n-\n-\n-#ifdef L__m32c_memregs\n-\n-/* Warning: these memory locations are used as a register bank.  They\n-   *must* end up consecutive in any final executable, so you may *not*\n-   use the otherwise obvious \".comm\" directive to allocate space for\n-   them. */\n-\n-\t.bss\n-\t.global\tmem0\n-mem0:\t.space\t1\n-\t.global\tmem1\n-mem1:\t.space\t1\n-\t.global\tmem2\n-mem2:\t.space\t1\n-\t.global\tmem3\n-mem3:\t.space\t1\n-\t.global\tmem4\n-mem4:\t.space\t1\n-\t.global\tmem5\n-mem5:\t.space\t1\n-\t.global\tmem6\n-mem6:\t.space\t1\n-\t.global\tmem7\n-mem7:\t.space\t1\n-\t.global\tmem8\n-mem8:\t.space\t1\n-\t.global\tmem9\n-mem9:\t.space\t1\n-\t.global\tmem10\n-mem10:\t.space\t1\n-\t.global\tmem11\n-mem11:\t.space\t1\n-\t.global\tmem12\n-mem12:\t.space\t1\n-\t.global\tmem13\n-mem13:\t.space\t1\n-\t.global\tmem14\n-mem14:\t.space\t1\n-\t.global\tmem15\n-mem15:\t.space\t1\n-\n-#endif\n-\n-#ifdef L__m32c_eh_return\n-\t.text\n-\t.global __m32c_eh_return\n-__m32c_eh_return:\t\n-\n-\t/* At this point, r0 has the stack adjustment, r1r3 has the\n-\t   address to return to.  The stack looks like this:\n-\n-\t   old_ra\n-\t   old_fp\n-\t   <- unwound sp\n-\t   ...\n-\t   fb\n-\t   through\n-\t   r0\n-\t   <- sp\n-\n-\t   What we need to do is restore all the registers, update the\n-\t   stack, and return to the right place.\n-\t*/\n-\n-\tstc\tsp,a0\n-\t\n-\tadd.W\tA(#16,#24),a0\n-\t/* a0 points to the current stack, just above the register\n-\t   save areas */\n-\n-\tmov.w\ta0,a1\n-\texts.w\tr0\n-\tsub.W\tA(r0,r2r0),a1\n-\tsub.W\tA(#3,#4),a1\n-\t/* a1 points to the new stack.  */\n-\n-\t/* This is for the \"rts\" below.  */\n-\tmov.w\tr1,[a1]\n-#ifdef A16\n-\tmov.w\tr2,r1\n-\tmov.b\tr1l,2[a1]\n-#else\n-\tmov.w\tr2,2[a1]\n-#endif\n-\n-\t/* This is for the \"popc sp\" below.  */\n-\tmov.W\ta1,[a0]\t\n-\n-\tpopm    r0,r1,r2,r3,a0,a1,sb,fb\n-\tpopc\tsp\n-\trts\n-#endif\n-\n-/* SImode arguments for SI foo(SI,SI) functions.  */\n-#ifdef A16\n-#define SAL  5[fb]\n-#define SAH  7[fb]\n-#define SBL  9[fb]\n-#define SBH 11[fb]\n-#else\n-#define SAL  8[fb]\n-#define SAH 10[fb]\n-#define SBL 12[fb]\n-#define SBH 14[fb]\n-#endif\n-\n-#ifdef L__m32c_mulsi3\n-\t.text\n-\t.global ___mulsi3\n-___mulsi3:\n-\tenter\t#0\n-\tpush.w\tr2\n-\tmov.w\tSAL,r0\n-\tmulu.w\tSBL,r0\t\t/* writes to r2r0 */\n-\tmov.w\tr0,mem0\n-\tmov.w\tr2,mem2\n-\tmov.w\tSAL,r0\n-\tmulu.w\tSBH,r0\t\t/* writes to r2r0 */\n-\tadd.w\tr0,mem2\n-\tmov.w\tSAH,r0\n-\tmulu.w\tSBL,r0\t\t/* writes to r2r0 */\n-\tadd.w\tr0,mem2\n-\tpop.w\tr2\n-\texitd\n-#endif\n-\n-#ifdef L__m32c_cmpsi2\n-\t.text\n-\t.global ___cmpsi2\n-___cmpsi2:\n-\tenter\t#0\n-\tcmp.w\tSBH,SAH\n-\tjgt\tcmpsi_gt\n-\tjlt\tcmpsi_lt\n-\tcmp.w\tSBL,SAL\n-\tjgt\tcmpsi_gt\n-\tjlt\tcmpsi_lt\n-\tmov.w\t#1,r0\n-\texitd\n-cmpsi_gt:\n-\tmov.w\t#2,r0\n-\texitd\n-cmpsi_lt:\n-\tmov.w\t#0,r0\n-\texitd\n-#endif\n-\n-#ifdef L__m32c_ucmpsi2\n-\t.text\n-\t.global ___ucmpsi2\n-___ucmpsi2:\n-\tenter\t#0\n-\tcmp.w\tSBH,SAH\n-\tjgtu\tcmpsi_gt\n-\tjltu\tcmpsi_lt\n-\tcmp.w\tSBL,SAL\n-\tjgtu\tcmpsi_gt\n-\tjltu\tcmpsi_lt\n-\tmov.w\t#1,r0\n-\texitd\n-cmpsi_gt:\n-\tmov.w\t#2,r0\n-\texitd\n-cmpsi_lt:\n-\tmov.w\t#0,r0\n-\texitd\n-#endif\n-\n-#ifdef L__m32c_jsri16\n-\t.text\n-#ifdef A16\n-\t.global\tm32c_jsri16\n-m32c_jsri16:\n-\tadd.w\t#-1, sp\n-\n-\t/* Read the address (16 bits) and return address (24 bits) off\n-\tthe stack.  */\n-\tmov.w\t4[sp], r0\n-\tmov.w\t1[sp], r3\n-\tmov.b\t3[sp], a0 /* This zero-extends, so the high byte has\n-\t\t\t     zero in it.  */\n-\n-\t/* Write the return address, then new address, to the stack.  */\n-\tmov.w\ta0, 1[sp] /* Just to get the zero in 2[sp].  */\n-\tmov.w\tr0, 0[sp]\n-\tmov.w\tr3, 3[sp]\n-\tmov.b\ta0, 5[sp]\n-\n-\t/* This \"returns\" to the target address, leaving the pending\n-\treturn address on the stack.  */\n-\trts\n-#endif\n-\n-#endif\ndiff --git a/libgcc/config/m32c/lib2funcs.c b/libgcc/config/m32c/lib2funcs.c\ndeleted file mode 100644\nindex 796f2a45d2d..00000000000\n--- a/libgcc/config/m32c/lib2funcs.c\n+++ /dev/null\n@@ -1,147 +0,0 @@\n-/* libgcc routines for R8C/M16C/M32C\n-   Copyright (C) 2005-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   Under Section 7 of GPL version 3, you are granted additional\n-   permissions described in the GCC Runtime Library Exception, version\n-   3.1, as published by the Free Software Foundation.\n-\n-   You should have received a copy of the GNU General Public License and\n-   a copy of the GCC Runtime Library Exception along with this program;\n-   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-typedef          int  sint32_type   __attribute__ ((mode (SI)));\n-typedef unsigned int  uint32_type   __attribute__ ((mode (SI)));\n-typedef int           word_type     __attribute__ ((mode (__word__)));\n-\n-uint32_type udivmodsi4 (uint32_type, uint32_type, word_type);\n-sint32_type __divsi3   (sint32_type, sint32_type);\n-sint32_type __modsi3   (sint32_type, sint32_type);\n-\n-uint32_type\n-udivmodsi4 (uint32_type num, uint32_type den, word_type modwanted)\n-{\n-  uint32_type bit = 1;\n-  uint32_type res = 0;\n-\n-  while (den < num && bit && !(den & (1L << 31)))\n-    {\n-      den <<= 1;\n-      bit <<= 1;\n-    }\n-  while (bit)\n-    {\n-      if (num >= den)\n-\t{\n-\t  num -= den;\n-\t  res |= bit;\n-\t}\n-      bit >>= 1;\n-      den >>= 1;\n-    }\n-  if (modwanted)\n-    return num;\n-  return res;\n-}\n-\n-sint32_type\n-__divsi3 (sint32_type a, sint32_type b)\n-{\n-  word_type neg = 0;\n-  sint32_type res;\n-\n-  if (a < 0)\n-    {\n-      a = -a;\n-      neg = !neg;\n-    }\n-\n-  if (b < 0)\n-    {\n-      b = -b;\n-      neg = !neg;\n-    }\n-\n-  res = udivmodsi4 (a, b, 0);\n-\n-  if (neg)\n-    res = -res;\n-\n-  return res;\n-}\n-\n-sint32_type\n-__modsi3 (sint32_type a, sint32_type b)\n-{\n-  word_type neg = 0;\n-  sint32_type res;\n-\n-  if (a < 0)\n-    {\n-      a = -a;\n-      neg = 1;\n-    }\n-\n-  if (b < 0)\n-    b = -b;\n-\n-  res = udivmodsi4 (a, b, 1);\n-\n-  if (neg)\n-    res = -res;\n-\n-  return res;\n-}\n-\n-/* See the comment by the definition of LIBGCC2_UNITS_PER_WORD in\n-   m32c.h for why we are creating extra versions of some of the\n-   functions defined in libgcc2.c.  */\n-\n-#define LIBGCC2_UNITS_PER_WORD 2\n-\n-#define L_clzsi2\n-#define L_ctzsi2\n-#define L_ffssi2\n-#define L_paritysi2\n-#define L_popcountsi2\n-\n-#include \"libgcc2.c\"\n-\n-uint32_type\n-__udivsi3 (uint32_type a, uint32_type b)\n-{\n-  return udivmodsi4 (a, b, 0);\n-}\n-\n-uint32_type\n-__umoddi3 (uint32_type a, uint32_type b)\n-{\n-  return udivmodsi4 (a, b, 1);\n-}\n-\n-/* Returns the number of leading redundant sign bits in X.\n-   I.e. the number of bits following the most significant bit which are\n-   identical to it.  There are no special cases for 0 or other values.  */\n-\n-int\n-__clrsbhi2 (word_type x)\n-{\n-  if (x < 0)\n-    x = ~x;\n-  if (x == 0)\n-    return 15;\n-  return __builtin_clz (x) - 1;\n-}\ndiff --git a/libgcc/config/m32c/t-m32c b/libgcc/config/m32c/t-m32c\ndeleted file mode 100644\nindex dac99ec652f..00000000000\n--- a/libgcc/config/m32c/t-m32c\n+++ /dev/null\n@@ -1,13 +0,0 @@\n-LIB1ASMSRC = m32c/lib1funcs.S\n-\n-LIB1ASMFUNCS = \\\n-\t__m32c_memregs \\\n-\t__m32c_eh_return \\\n-\t__m32c_mulsi3 \\\n-\t__m32c_cmpsi2 \\\n-\t__m32c_ucmpsi2 \\\n-\t__m32c_jsri16\n-\n-LIB2ADD = $(srcdir)/config/m32c/lib2funcs.c \\\n-\t  $(srcdir)/config/m32c/trapv.c\n-\ndiff --git a/libgcc/config/m32c/trapv.c b/libgcc/config/m32c/trapv.c\ndeleted file mode 100644\nindex 27cfc01b85d..00000000000\n--- a/libgcc/config/m32c/trapv.c\n+++ /dev/null\n@@ -1,42 +0,0 @@\n-/* 16-bit trapping arithmetic routines for R8C/M16C/M32C\n-   Copyright (C) 2009-2026 Free Software Foundation, Inc.\n-   Contributed by Red Hat.\n-\n-   This file is part of GCC.\n-\n-   GCC is free software; you can redistribute it and/or modify it\n-   under the terms of the GNU General Public License as published\n-   by the Free Software Foundation; either version 3, or (at your\n-   option) any later version.\n-\n-   GCC is distributed in the hope that it will be useful, but WITHOUT\n-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public\n-   License for more details.\n-\n-   Under Section 7 of GPL version 3, you are granted additional\n-   permissions described in the GCC Runtime Library Exception, version\n-   3.1, as published by the Free Software Foundation.\n-\n-   You should have received a copy of the GNU General Public License and\n-   a copy of the GCC Runtime Library Exception along with this program;\n-   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see\n-   <http://www.gnu.org/licenses/>.  */\n-\n-/* See the comment by the definition of LIBGCC2_UNITS_PER_WORD in\n-   m32c.h for why we are creating extra versions of some of the\n-   functions defined in libgcc2.c.\n-\n-   Note - this file is separate from lib2funcs.c so that the following\n-   functions will appear in the their object file.  This is necessary\n-   because they call abort() which is defined in the C library whereas\n-   the functions in lib2funcs.c are completely self sufficient.  */\n-\n-#define LIBGCC2_UNITS_PER_WORD 2\n-\n-#define L_mulvsi3\n-#define L_negvsi2\n-#define L_addvsi3\n-#define L_subvsi3\n-\n-#include \"libgcc2.c\"\ndiff --git a/libgcc/config/rl78/lib2div.c b/libgcc/config/rl78/lib2div.c\nindex 5ba3b3ed197..6298c6860a7 100644\n--- a/libgcc/config/rl78/lib2div.c\n+++ b/libgcc/config/rl78/lib2div.c\n@@ -35,7 +35,7 @@ typedef int           word_type     __attribute__ ((mode (__word__)));\n #define C3(a,b,c) C3B(a,b,c)\n \n /* See the comment by the definition of LIBGCC2_UNITS_PER_WORD in\n-   m32c.h for why we are creating extra versions of some of the\n+   msp430.h for why we are creating extra versions of some of the\n    functions defined in libgcc2.c.  */\n \n #define LIBGCC2_UNITS_PER_WORD 2\n",
    "prefixes": [
        "GCC17-stage1"
    ]
}