Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2226488/?format=api
{ "id": 2226488, "url": "http://patchwork.ozlabs.org/api/patches/2226488/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260422134926.653211-1-ankita@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422134926.653211-1-ankita@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T13:49:26", "name": "[v6,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9d9a3b7597ae12b86d937b296df5d02a7485a984", "submitter": { "id": 86155, "url": "http://patchwork.ozlabs.org/api/people/86155/?format=api", "name": "Ankit Agrawal", "email": "ankita@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260422134926.653211-1-ankita@nvidia.com/mbox/", "series": [ { "id": 501013, "url": "http://patchwork.ozlabs.org/api/series/501013/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501013", "date": "2026-04-22T13:49:26", "name": "[v6,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/501013/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226488/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226488/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52971-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ki79IvRo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52971-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"ki79IvRo\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.201.60", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g10zK42LJz1yD5\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 23:52:45 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id C1BFB300D443\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 13:49:56 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 8BBAF2BF3F3;\n\tWed, 22 Apr 2026 13:49:54 +0000 (UTC)", "from PH7PR06CU001.outbound.protection.outlook.com\n (mail-westus3azon11010060.outbound.protection.outlook.com [52.101.201.60])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id E84443168FB;\n\tWed, 22 Apr 2026 13:49:50 +0000 (UTC)", "from PH7P220CA0069.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:32c::18)\n by SN7PR12MB6863.namprd12.prod.outlook.com (2603:10b6:806:264::19) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.16; Wed, 22 Apr\n 2026 13:49:44 +0000", "from CY4PEPF0000E9CD.namprd03.prod.outlook.com\n (2603:10b6:510:32c:cafe::ee) by PH7P220CA0069.outlook.office365.com\n (2603:10b6:510:32c::18) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9791.48 via Frontend Transport; Wed,\n 22 Apr 2026 13:49:44 +0000", "from mail.nvidia.com (216.228.117.161) by\n CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.132) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9846.18 via Frontend Transport; Wed, 22 Apr 2026 13:49:43 +0000", "from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 22 Apr\n 2026 06:49:27 -0700", "from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail202.nvidia.com\n (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 22 Apr\n 2026 06:49:26 -0700", "from localhost.nvidia.com (10.127.8.12) by mail.nvidia.com\n (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend\n Transport; Wed, 22 Apr 2026 06:49:26 -0700" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776865794; cv=fail;\n b=CSrmnyfQQkK7WFPOaWP+mDmU1TKQUD2CJ/sI2NSM0pIHUQaRMxqJLC/JZLca+yER7XbZ8vtRKA6S3mg3fM4G96UraZsPXowlZg7c2ztEoZnai8vM/CaET1AtTbp2iMy6SS0PylZV/GHyeIfjG56l8cyDPIqFuA9Iux11ipHbzOI=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=qIXg/KD4qBs1yIkcaig9eKG3gGk3/lvYdQ5gD2mvyih0wYUHAnwTJ/mpt4A9Iq45izqvX93WElZMZ4geGFIGFxTMKctYumITP9kfJ5ZI8oPv27VDGxKbVS6wmj1O8JHj6SBEjmO8/uSriizRS/CxCqG09hddDRXYx/GrLc8w+s4rugBuoMIxKA1tatcqnGa3hGEcc6C1VrrapWVQJwJ+RoBXS+JwuD7D1I7ItIjBHZ55fc9VgUJzNbMFMWsZTnp9CyUhfJxd3Z1JwaR0+mIMuzCnXIX3ppKubDjYh/zj+CWO7qqOh1+zfKiGADstdC7jaCV2OyalllrgJ37ETF7SOQ==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776865794; c=relaxed/simple;\n\tbh=O8HLv/YmzGRgf3PDSDPmYeV5mPmG9MlUo4yRgit/v24=;\n\th=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type;\n b=jv6JSDQS8yzDz5ggiXWfroe+6eLLItZVApCiGYqmCGLsgHQc4BkdKEcayY4xGyYtYoWsNu00yqr6x7qQJSi1HcIVIGc8VFTUxKT/atIk3cld1eaDVn1J5SyuC3p7OVnmunqCo2dwQdj1lDWBXE2cTklbtAJx6pebMc179JV+psU=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=1N7lqhEExXkzNpxPJoBMFISj4bPUtzKeYFLFQkVAyqU=;\n b=jsRmhacz/VHDbsdOxGZPxVow7gQC3b1IiwlpG8UmeuLCG2Tp6uUDBpoVc6/ql3Z+2JmV/UKaKSzjejl9f/+OFMgSxiZCW0Znox2/2IHBrj1HsCI/n64kbMwXk9h/9xgXwp33cLbN+OYEbX1stcDfVCTJduPeqYDPjmnfDNiNcYiizQt4vHb8CY6gkcF79MCwsGyfyAikX+fuQh9GCquEznBpy6RcPwOhY4YYYqnRn2eDbgUxtA9KKiBMcnu8t+qHp9jHd3iTAbaGxFxXrMwgLiRd6JUyRPwSX+qkmDoQgTxpaf0EuTyDZCu2Ka9twm4JDXfMPzdNYZFpIZIgn5axjg==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=ki79IvRo; arc=fail smtp.client-ip=52.101.201.60", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=shazbot.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=1N7lqhEExXkzNpxPJoBMFISj4bPUtzKeYFLFQkVAyqU=;\n b=ki79IvRon8oBQp+L/2NikbrBJ+BKEN58LYK4ML/NIMdeNIIJjc+3fiVfuIv0afgNqmGadnRlmE6Rp0yO5Xo0k72vCykWrKQ5+4wezzqr/SEbOd+CmxO1muTc45MXHHqJTBpBm+7P+J0IT4cnlzWWM5/uhI2BiQ8x6A0UAiRh4sqzEX6tMbQkXJxdswo/Cx0jsbKg1hPQWWwJxwzegCNuo8UMA2T1O34U9t26+XDYE20Fzd+jtFyTDJyjEces+x0RuMpkJk90toIsZJvP4Mg+kj461Ks8c+6rqcJ6+/keDGii2xYZNC2tw+wIW7I0MIk7740q7X3VIYmhbufWCf1MvQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Ankit Agrawal <ankita@nvidia.com>", "To": "<alex@shazbot.org>, <kvm@vger.kernel.org>", "CC": "<jgg@ziepe.ca>, <yishaih@nvidia.com>, <skolothumtho@nvidia.com>,\n\t<kevin.tian@intel.com>, <ankita@nvidia.com>, <bhelgaas@google.com>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v6 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC", "Date": "Wed, 22 Apr 2026 13:49:26 +0000", "Message-ID": "<20260422134926.653211-1-ankita@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9CD:EE_|SN7PR12MB6863:EE_", "X-MS-Office365-Filtering-Correlation-Id": "edc38090-702b-4f14-6ec1-08dea076026f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|376014|36860700016|82310400026|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tLdah7swR7/6naHksrK6xh6IZx5UAJpKywtogj+YEphT1SctFAazAX5XJ8xzL8lu5mFKl9TatdF3S4dZNenVsUn/YN4vsPx8vJ1ah/jxkRrsuDa7VfZaMDpRf4BtOoHjiXPDE887ulRCEb4lkcNt6akA3axRWcsGzOhIdo0ZLaPfXrlSbsPALlZpbcpjad3ap4r58r9uzdSVjXkcdiMcKzeIdfqvHg/WLFiAVaEfTZ71yVqjW4IopQLM1lKkuwLxYG/u/5YoBBJiOEBZKUbU4pSCJTBtka97pYJsFn2KCbs8zcgxZlC9AV8/kXZJ+xp3v5ImwYljnzDoAZKQKUzLY0HSJJwMGdAzyoj/FuKDsu8jOiw85TH0N2Wht2/547KVM6vdBAlFe2UJls5+elR8E95UPJp3A2TFdUmgh94biSY3HmZVjWbyG8PNcH4jqRmA4eStzyqe75zpZ0UHmGHmdht/ra0srmMUaPugwLmrTc+fBRX+OWrkut/iyGEQZH4CUUa8d6XQMU/N6DoxOxet1CS3YDsD8fFH1uQkuLM228cVE6kq83TtJSaUGtLmYRl6hRS8oiJDWWr+Jxr+Wx1PuSjQoeTY8Pad3dZl6F2dvUmiCadqYk36UvH5gHa8gwMqoKl1FEbAiig8XWSsCeLHuEOvHKgJx2ug4KWf+FuLNk0Hci5fVl4GfOj70rF00cpDzrSI+gpm4WzineN3qEcfOiQe6rj/lPgeVhe08GEoH9Wvtwf7ooi3Y6ZXXtqv70ENHIAXwBXb/qfpIgI5af5+zIQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tWBTk3pKJTiozCBZAuyOFCLgbXd1g0AKGGxApZH+y+u2EqJwy1/SZdq4srFRWyH/C6MenOexu0kZVYJA/f11Q6bphRWyFzwh70maJ/ZXwWQ62GoudGKvGCN4RRqLztierK/Q7CV3I7G2asjmin5ufQBOWqQ0tyoKDx6p1a/J2Xo6cPBlkdmN/E203hmL5VrbpXLmZV+UCF6q00E1K/zriTDNS5CM1twQXC2r8nAjgGdMHXTRU5nqK4lI0HejipTht6zusDsb0h5Qp7NfS/anIdHltySzR4p/Na1g78o1ZvJefuqrWDIft92l0YBjHtWPR7t29+VA0ocUvEl68vQ5BEQ5oqslTd5F8rN2kg2SzmeRnRsucIHR00SNpOGA+0nOAwAYEcU3yU07bYEZt7BTAnsHzhzWYBQvqqxuaJS3EaqV3QqZZGS5AYu75N6J787eA", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Apr 2026 13:49:43.9318\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n edc38090-702b-4f14-6ec1-08dea076026f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000E9CD.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB6863" }, "content": "Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside\nthe existing legacy BAR0 polling path. On probe and after reset, the\ndriver reads the CXL Device DVSEC capability to determine whether the\nGPU memory is ready. A static inline wrapper dispatches to the\nappropriate readiness check (legacy v/s blackwell-next based on whether\nthe CXL DVSEC capability is present.\n\nThe memory readiness is checked by polling on the Memory_Active bit\nbased on the Memory_Active_Timeout. It also checks if MEM_INFO_VALID\nis set within 1 second. If not, return error. This is based on the\nCXL spec 4.0 Tables 8-13.\n\nAdd PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout\nfield encoding.\n\nCc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>\nCc: Kevin Tian <kevin.tian@intel.com>\nSuggested-by: Alex Williamson <alex@shazbot.org>\nSigned-off-by: Ankit Agrawal <ankita@nvidia.com>\n---\n drivers/vfio/pci/nvgrace-gpu/main.c | 107 +++++++++++++++++++++++++---\n include/uapi/linux/pci_regs.h | 1 +\n 2 files changed, 99 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c\nindex fa056b69f899..4e1d20ad7510 100644\n--- a/drivers/vfio/pci/nvgrace-gpu/main.c\n+++ b/drivers/vfio/pci/nvgrace-gpu/main.c\n@@ -3,7 +3,9 @@\n * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved\n */\n \n+#include <linux/bitfield.h>\n #include <linux/sizes.h>\n+#include <linux/time64.h>\n #include <linux/vfio_pci_core.h>\n #include <linux/delay.h>\n #include <linux/jiffies.h>\n@@ -64,6 +66,8 @@ struct nvgrace_gpu_pci_core_device {\n \tbool has_mig_hw_bug;\n \t/* GPU has just been reset */\n \tbool reset_done;\n+\t/* CXL Device DVSEC offset; 0 if not present (legacy GB path) */\n+\tint cxl_dvsec;\n };\n \n static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vdev)\n@@ -242,7 +246,7 @@ static void nvgrace_gpu_close_device(struct vfio_device *core_vdev)\n \tvfio_pci_core_close_device(core_vdev);\n }\n \n-static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n+static int nvgrace_gpu_wait_device_ready_legacy(void __iomem *io)\n {\n \tunsigned long timeout = jiffies + msecs_to_jiffies(POLL_TIMEOUT_MS);\n \n@@ -256,6 +260,81 @@ static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n \treturn -ETIME;\n }\n \n+/*\n+ * Decode the 3-bit Memory_Active_Timeout field from CXL DVSEC Range 1 Low\n+ * (bits 15:13) into milliseconds. Encoding per CXL spec r4.0 sec 8.1.3.8.2:\n+ * 000b = 1s, 001b = 4s, 010b = 16s, 011b = 64s, 100b = 256s,\n+ * 101b-111b = reserved (clamped to 256s).\n+ */\n+static inline unsigned long cxl_mem_active_timeout_ms(u8 timeout)\n+{\n+\treturn MSEC_PER_SEC << (2 * min_t(u8, timeout, 4));\n+}\n+\n+/*\n+ * Check if CXL DVSEC reports memory as valid and active.\n+ */\n+static inline bool cxl_dvsec_mem_is_active(u32 status)\n+{\n+\treturn (status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n+\t (status & PCI_DVSEC_CXL_MEM_ACTIVE);\n+}\n+\n+static int nvgrace_gpu_wait_device_ready_cxl(struct nvgrace_gpu_pci_core_device *nvdev)\n+{\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n+\tint cxl_dvsec = nvdev->cxl_dvsec;\n+\tunsigned long mem_info_valid_deadline;\n+\tunsigned long timeout = 0;\n+\tu32 dvsec_memory_status;\n+\n+\tmem_info_valid_deadline = jiffies + msecs_to_jiffies(POLL_QUANTUM_MS);\n+\n+\tdo {\n+\t\tpci_read_config_dword(pdev,\n+\t\t\t\t cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n+\t\t\t\t &dvsec_memory_status);\n+\n+\t\tif (dvsec_memory_status == ~0U)\n+\t\t\treturn -ENODEV;\n+\n+\t\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n+\t\t\treturn 0;\n+\n+\t\t/*\n+\t\t * Once MEM_INFO_VALID is set, derive the MEM_ACTIVE timeout\n+\t\t * from the register.\n+\t\t */\n+\t\tif (dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) {\n+\t\t\tif (!timeout) {\n+\t\t\t\tu8 mem_active_timeout =\n+\t\t\t\t\tFIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n+\t\t\t\t\t\t dvsec_memory_status);\n+\n+\t\t\t\ttimeout = jiffies +\n+\t\t\t\t\t msecs_to_jiffies(cxl_mem_active_timeout_ms(mem_active_timeout));\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Bail early if MEM_INFO_VALID is not set within 1 second */\n+\t\tif (!(dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n+\t\t time_after(jiffies, mem_info_valid_deadline))\n+\t\t\treturn -ETIME;\n+\n+\t\tmsleep(POLL_QUANTUM_MS);\n+\t} while (!timeout || !time_after(jiffies, timeout));\n+\n+\treturn -ETIME;\n+}\n+\n+static inline int nvgrace_gpu_wait_device_ready(struct nvgrace_gpu_pci_core_device *nvdev,\n+\t\t\t\t\t\tvoid __iomem *io)\n+{\n+\treturn nvdev->cxl_dvsec ?\n+\t\tnvgrace_gpu_wait_device_ready_cxl(nvdev) :\n+\t\tnvgrace_gpu_wait_device_ready_legacy(io);\n+}\n+\n /*\n * If the GPU memory is accessed by the CPU while the GPU is not ready\n * after reset, it can cause harmless corrected RAS events to be logged.\n@@ -275,7 +354,7 @@ nvgrace_gpu_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n \tif (!__vfio_pci_memory_enabled(vdev))\n \t\treturn -EIO;\n \n-\tret = nvgrace_gpu_wait_device_ready(vdev->barmap[0]);\n+\tret = nvgrace_gpu_wait_device_ready(nvdev, vdev->barmap[0]);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1143,14 +1222,21 @@ static bool nvgrace_gpu_has_mig_hw_bug(struct pci_dev *pdev)\n * is beneficial to make the check to ensure the device is in an\n * expected state.\n *\n- * Ensure that the BAR0 region is enabled before accessing the\n+ * On Blackwell-Next systems, memory readiness is determined via the\n+ * CXL Device DVSEC in PCI config space and does not require BAR0.\n+ * For the legacy path, ensure BAR0 is enabled before accessing the\n * registers.\n */\n-static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n+static int nvgrace_gpu_probe_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n {\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n \tvoid __iomem *io;\n \tint ret;\n \n+\t/* CXL path only reads PCI config space; no need to map BAR0. */\n+\tif (nvdev->cxl_dvsec)\n+\t\treturn nvgrace_gpu_wait_device_ready_cxl(nvdev);\n+\n \tret = pci_enable_device(pdev);\n \tif (ret)\n \t\treturn ret;\n@@ -1165,7 +1251,7 @@ static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n \t\tgoto iomap_exit;\n \t}\n \n-\tret = nvgrace_gpu_wait_device_ready(io);\n+\tret = nvgrace_gpu_wait_device_ready_legacy(io);\n \n \tpci_iounmap(pdev, io);\n iomap_exit:\n@@ -1183,10 +1269,6 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \tu64 memphys, memlength;\n \tint ret;\n \n-\tret = nvgrace_gpu_probe_check_device_ready(pdev);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tret = nvgrace_gpu_fetch_memory_property(pdev, &memphys, &memlength);\n \tif (!ret)\n \t\tops = &nvgrace_gpu_pci_ops;\n@@ -1198,6 +1280,13 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \n \tdev_set_drvdata(&pdev->dev, &nvdev->core_device);\n \n+\tnvdev->cxl_dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n+\t\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n+\n+\tret = nvgrace_gpu_probe_check_device_ready(nvdev);\n+\tif (ret)\n+\t\tgoto out_put_vdev;\n+\n \tif (ops == &nvgrace_gpu_pci_ops) {\n \t\tnvdev->has_mig_hw_bug = nvgrace_gpu_has_mig_hw_bug(pdev);\n \ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex 14f634ab9350..718fb630f5bb 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -1357,6 +1357,7 @@\n #define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i)\t\t(0x1C + (i * 0x10))\n #define PCI_DVSEC_CXL_MEM_INFO_VALID\t\t\t_BITUL(0)\n #define PCI_DVSEC_CXL_MEM_ACTIVE\t\t\t_BITUL(1)\n+#define PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT\t\t__GENMASK(15, 13)\n #define PCI_DVSEC_CXL_MEM_SIZE_LOW\t\t\t__GENMASK(31, 28)\n #define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i)\t\t(0x20 + (i * 0x10))\n #define PCI_DVSEC_CXL_RANGE_BASE_LOW(i)\t\t(0x24 + (i * 0x10))\n", "prefixes": [ "v6", "1/1" ] }