Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2226163/?format=api
{ "id": 2226163, "url": "http://patchwork.ozlabs.org/api/patches/2226163/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-30-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422101043.1234229-30-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2026-04-22T10:10:40", "name": "[v2,29/31] target/arm: implement global monitor events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "de78f4173d1f4fd933fe2c213fa0cbbe9d35ca43", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-30-alex.bennee@linaro.org/mbox/", "series": [ { "id": 500957, "url": "http://patchwork.ozlabs.org/api/series/500957/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957", "date": "2026-04-22T10:10:11", "name": "target/arm: fully model WFxT instructions for A-profile", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500957/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226163/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226163/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=fArmz0Pb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0wFD1qnkz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 20:19:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFUey-0007W8-Vm; Wed, 22 Apr 2026 06:18:21 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alex.bennee@linaro.org>)\n id 1wFUeM-0006yv-7w\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 06:17:43 -0400", "from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <alex.bennee@linaro.org>)\n id 1wFUeD-0002Ne-LZ\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 06:17:36 -0400", "by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-4891d7164ddso20264915e9.3\n for <qemu-devel@nongnu.org>; Wed, 22 Apr 2026 03:17:31 -0700 (PDT)", "from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4e4d5b1sm48556196f8f.30.2026.04.22.03.17.25\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 22 Apr 2026 03:17:28 -0700 (PDT)", "from draig.lan (localhost [IPv6:::1])\n by draig.lan (Postfix) with ESMTP id CF1A4616F5;\n Wed, 22 Apr 2026 11:10:45 +0100 (BST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776853051; x=1777457851; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=gSYzG4w2krdb3nT01JqHA9xtpgh1UWf3StMYQUTc4bg=;\n b=fArmz0PbBkq28AMLdMgSbpAv/cUpBHGo4I/DAj22+KywMjndnEotuLki9TrydBg3wx\n 6oQbjZ0Q1bNxDT/Ip8XE0wPNABBNb8cd1mjKOTnq/nAxGI6rI+yOUqU7fpXlEEJfZ5Ll\n kV/iHmo6R22URvemdRe9EJSKI18NdXhj3wpQLmOqnvYNfGKNvqF2hg/59iGnEnOl8kUP\n 9oivF8WWIJginRd3SuRU/GkP5dy0RCXWceDhBKB2bXCCoOJ7JBIlW7q0O7ZltCYGMv23\n JSw6fqpUvlgYvXctAALT5pnE4S4EyhA8aFsEgx2TG1qyZQZsR9M1pksaz1rQD7FUTjsq\n BvFg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776853051; x=1777457851;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=gSYzG4w2krdb3nT01JqHA9xtpgh1UWf3StMYQUTc4bg=;\n b=qsZDOd1OiJAW4/s6F0H/Oa7dvXFzsLYmw+xGzOiWz4kNIJ+bcb6+f2zpFIjdiLP1ct\n eM5u1bQ6G/ZAwR6+LiFLPFljCT96aOBQMJhYjpmYJVcYG7huzEtQA5laTpfNbB8kwePu\n GawANUlaTee4nCh7NTqdjOR4/IAm4IKos11DmfEZrm0bU81emHe8vGwiTvL/w7t+5J0B\n K4f4RIt6EwTZ9IjwfVntPKYR2z84jLETl9WP+jRBya0FBJt0RwWkLxwYPhgLR2usmGA7\n WmAiW+/8tg7gF6bxxcfhSjgtvztP7Ul4T+xFsVBxfSGqNd3XVIpeD8x0TceDMx4HoMea\n 6VkA==", "X-Gm-Message-State": "AOJu0Ywai4dw4KxvoFbNnMlQqgpfJgY+ykOIexhu1QeuV8ypto4A+LO+\n FEhuNrF3rriz1MITrCmKi9M9Bi+fkggE0eBcGwfYOO8AaFh78XUnuMAv+QcaksonLmw=", "X-Gm-Gg": "AeBDiesoqjK3YFs2ZyJhuDG7EIBaElJ3GpgR2qG8g9RBUqbGBu1NK8GlMuQ2nX3hFhD\n xEtvhfUniX5T2DFaHh0exB6opiq7A60rbTxDgNAHSdwG/rIm8ZsunY9iIf1yGhiVC7wEBL0v53X\n kfz7QEH9R8knzGwbge8vOhe9q51WWvrre6NIWB8RXfV2Ai9RrS+X9oJ/x2A0zTlxfOSWEWxUnUX\n 8Np3gmH7eqq4pPI2Og/ERLOK5rRS6iBvldb342UCMTyhykkP5B7FmmRw0x95F1MI0AMzl4d03zL\n YxmNNbpKqJCu2HonjtpT6BHoidYLwI1R/08osEcN03Nuda8HY4JPyZLJXF6uxd5V3uchtZgSC5Z\n 4yu5iFLqcSPbNJuFOGzg/AyPI/SGfW5BhdbjUdnjqf1IwFl/27FS72tZbHV7lM4zCqWW1pJa3XR\n eYSUGurpVLIHV3wte9KkkpxsgLZzSN9JGSjg==", "X-Received": "by 2002:a05:600c:3e1a:b0:489:1ca2:eafd with SMTP id\n 5b1f17b1804b1-4891ca2ee65mr169059005e9.11.1776853050447;\n Wed, 22 Apr 2026 03:17:30 -0700 (PDT)", "From": "=?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "Alexander Graf <agraf@csgraf.de>, qemu-arm@nongnu.org,\n Peter Maydell <peter.maydell@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>, kvm@vger.kernel.org,\n Pedro Barbuda <pbarbuda@microsoft.com>,\n =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>", "Subject": "[PATCH v2 29/31] target/arm: implement global monitor events", "Date": "Wed, 22 Apr 2026 11:10:40 +0100", "Message-ID": "<20260422101043.1234229-30-alex.bennee@linaro.org>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260422101043.1234229-1-alex.bennee@linaro.org>", "References": "<20260422101043.1234229-1-alex.bennee@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::329;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Moving from Exclusive to Open Access should generate event stream\nevents. Technically a non-exclusive store to any address range covered\nby the global monitor should also trigger such an event but we can\nonly detect that after the event by seeing if memory doesn't match\ncpu_exclusive_val when processing the eventual store exclusive.\n\nThe CLREX instruction has the same effect as do other operations\nclearing the exclusive state (such as eret).\n\nWe special case STLR/STL (Store Release) instructions to generate\nevents because their use is a suggested pattern for clearing locks\nthat might be sleeping. We only trigger the event if we detect an\nexclusive instruction is running.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\n---\nv2\n - add gen_global_event_reg() and use that\n - add handling for STL/STLR\n---\n target/arm/internals.h | 1 +\n target/arm/tcg/translate.h | 14 ++++++++++++++\n target/arm/tcg/translate-a64.c | 23 +++++++++++++++++++++++\n target/arm/tcg/translate.c | 20 ++++++++++++++++++++\n 4 files changed, 58 insertions(+)", "diff": "diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 089f679ac0a..7045b4a56bd 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -709,6 +709,7 @@ static inline void arm_broadcast_event(void)\n static inline void arm_clear_exclusive(CPUARMState *env)\n {\n env->exclusive_addr = -1;\n+ arm_broadcast_event();\n }\n \n /**\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 9bf2701a56b..01053060af4 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -882,6 +882,20 @@ static inline void gen_event_reg(void)\n #endif\n }\n \n+/*\n+ * Some events affect all PEs in the same shareability domain. In\n+ * practice as we currently model SMP systems as single SoC devices so\n+ * we signal them all.\n+ */\n+static inline void gen_global_event_reg(void)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ /* re-use the SEV helper */\n+ gen_helper_sev(tcg_env);\n+#endif\n+}\n+\n+\n /*\n * Helpers for implementing sets of trans_* functions.\n * Defer the implementation of NAME to FUNC, with optional extra arguments.\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex f30df5dbfed..a1b0cc9508e 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -2253,6 +2253,7 @@ static bool trans_CHKFEAT(DisasContext *s, arg_CHKFEAT *a)\n static bool trans_CLREX(DisasContext *s, arg_CLREX *a)\n {\n tcg_gen_movi_i64(cpu_exclusive_addr, -1);\n+ gen_global_event_reg();\n return true;\n }\n \n@@ -3407,6 +3408,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);\n }\n tcg_gen_mov_i64(cpu_reg(s, rd), tmp);\n+\n+ /*\n+ * On a successful StoreExcl the global monitor transitions from\n+ * Exclusive to Open Access and at that point generate an Event\n+ * for PEs in the same memory sharing domain.\n+ */\n+ gen_global_event_reg();\n+\n tcg_gen_br(done_label);\n \n gen_set_label(fail_label);\n@@ -3544,6 +3553,7 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n TCGv_i64 clean_addr;\n MemOp memop;\n bool iss_sf = ldst_iss_sf(a->sz, false, false);\n+ TCGLabel *skip_monitor_event = gen_new_label();\n \n /*\n * StoreLORelease is the same as Store-Release for QEMU, but\n@@ -3562,6 +3572,19 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n true, a->rn != 31, memop);\n do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt,\n iss_sf, a->lasr);\n+\n+ /*\n+ * We don't fully model the global monitor as it would be very\n+ * expensive for every memory access. However in the Arm ARM \"Use\n+ * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n+ * give the example of using STLR to clear a lock. So if a lock is\n+ * active trigger the global event register so we don't deadlock\n+ * while sleeping.\n+ */\n+ tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n+ gen_global_event_reg();\n+ gen_set_label(skip_monitor_event);\n+\n return true;\n }\n \ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 59925151fc3..18d64620e40 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -2116,6 +2116,12 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t2);\n }\n tcg_gen_mov_i32(cpu_R[rd], t0);\n+ /*\n+ * On a successful StoreExcl the global monitor transitions from\n+ * Exclusive to Open Access and at that point generate an Event\n+ * for PEs in the same memory sharing domain.\n+ */\n+ gen_global_event_reg();\n tcg_gen_br(done_label);\n \n gen_set_label(fail_label);\n@@ -4218,6 +4224,7 @@ static bool trans_STLEXH(DisasContext *s, arg_STREX *a)\n static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)\n {\n TCGv_i32 addr, tmp;\n+ TCGLabel *skip_monitor_event;\n \n if (!ENABLE_ARCH_8) {\n return false;\n@@ -4230,10 +4237,23 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)\n \n addr = load_reg(s, a->rn);\n tmp = load_reg(s, a->rt);\n+ skip_monitor_event = gen_new_label();\n tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);\n gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN);\n disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite);\n \n+ /*\n+ * We don't fully model the global monitor as it would be very\n+ * expensive for every memory access. However in the Arm ARM \"Use\n+ * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n+ * give the example of using STL to clear a lock. So if a lock is\n+ * active trigger the global event register so we don't deadlock\n+ * while sleeping.\n+ */\n+ tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n+ gen_global_event_reg();\n+ gen_set_label(skip_monitor_event);\n+\n return true;\n }\n \n", "prefixes": [ "v2", "29/31" ] }