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GET /api/patches/2226037/?format=api
{ "id": 2226037, "url": "http://patchwork.ozlabs.org/api/patches/2226037/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260422023239.1171963-3-mrathor@linux.microsoft.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422023239.1171963-3-mrathor@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-22T02:32:28", "name": "[V1,02/13] x86/hyperv: cosmetic changes in irqdomain.c for readability", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2a62243d6f442ee5383128ab97853c079d7342f6", "submitter": { "id": 91512, "url": "http://patchwork.ozlabs.org/api/people/91512/?format=api", "name": "Mukesh R", "email": "mrathor@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260422023239.1171963-3-mrathor@linux.microsoft.com/mbox/", "series": [ { "id": 500915, "url": "http://patchwork.ozlabs.org/api/series/500915/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500915", "date": "2026-04-22T02:32:26", "name": "PCI passthru on Hyper-V (Part I)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500915/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226037/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226037/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52898-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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19:33:38 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776825232; cv=none;\n b=mOTs3XURcoJ8SU4KXmy6BpCm6lErR3BeoI7uDYF3DLpF/J+9nuF/a1t/7IQiNn2rfwMJdRu/7ujXt5eTcDgxmz8tIjeWLwew+QrvkxlXrXKxVIdPM4QjaGpsAJdTZe4hqUMB5I2H2gUKAqiQdT1xh9YevKO/iNTh+s8Xp0gsTzk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776825232; c=relaxed/simple;\n\tbh=aZ5nQ4kWLyHURBZkrlbygyaJvL1p2ds7QkhsVlbg7P4=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=BOkOkLd8k03U6NTP4sQ+wGZg8DdFtcTtEZw7F66bSOeVxLv93kyeuvQzyVjfxuSY+C4ZPLxI2nFdXH/J84l6F4cgmPVcovlaJoPuJDUWornYC4B0e50/LForHEGOrnWVoRz9IYAyzSiSGD/V5xh66KAD/4jrNX8Cbhaz+k0W0ns=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.microsoft.com;\n spf=pass smtp.mailfrom=linux.microsoft.com;\n dkim=pass (1024-bit key) header.d=linux.microsoft.com\n header.i=@linux.microsoft.com header.b=KKA6qZW5;\n arc=none smtp.client-ip=13.77.154.182", "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com E897520B6F0C", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n\ts=default; t=1776825219;\n\tbh=/FJ9bsIxu/JI3kZjnk9v7T9zslA2gv7h8SLu9mSngSI=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=KKA6qZW5BjTGetTHaXr1H8yflRGSL50UrgxIwpnE1ji/CbxmlmQ2lYeHJZ6lF3qeF\n\t E5VhCdLpQ8kJNyFLS1ku5GfIrK7k35JBcqlwOBGGqu9ai1FDNXcgts90myQ4H+0XQ5\n\t qupbxfCETPcRTSgtEui/pD/BAuxy0B1D6+OP/UqQ=", "From": "Mukesh R <mrathor@linux.microsoft.com>", "To": "hpa@zytor.com,\n\trobin.murphy@arm.com,\n\trobh@kernel.org,\n\twei.liu@kernel.org,\n\tmrathor@linux.microsoft.com,\n\tmhklinux@outlook.com,\n\tmuislam@microsoft.com,\n\tnamjain@linux.microsoft.com,\n\tmagnuskulke@linux.microsoft.com,\n\tanbelski@linux.microsoft.com,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-hyperv@vger.kernel.org,\n\tiommu@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arch@vger.kernel.org", "Cc": "kys@microsoft.com,\n\thaiyangz@microsoft.com,\n\tdecui@microsoft.com,\n\tlongli@microsoft.com,\n\ttglx@kernel.org,\n\tmingo@redhat.com,\n\tbp@alien8.de,\n\tdave.hansen@linux.intel.com,\n\tx86@kernel.org,\n\tjoro@8bytes.org,\n\twill@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tbhelgaas@google.com,\n\tarnd@arndb.de", "Subject": "[PATCH V1 02/13] x86/hyperv: cosmetic changes in irqdomain.c for\n readability", "Date": "Tue, 21 Apr 2026 19:32:28 -0700", "Message-ID": "<20260422023239.1171963-3-mrathor@linux.microsoft.com>", "X-Mailer": "git-send-email 2.51.2.vfs.0.1", "In-Reply-To": "<20260422023239.1171963-1-mrathor@linux.microsoft.com>", "References": "<20260422023239.1171963-1-mrathor@linux.microsoft.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Make cosmetic changes:\n o Rename struct pci_dev *dev to *pdev since there are cases of\n struct device *dev in the file and all over the kernel\n o Rename hv_build_pci_dev_id to hv_build_devid_type_pci in anticipation\n of building different types of device ids\n o Fix checkpatch.pl issues with return and extraneous printk\n o Replace spaces with tabs\n o Rename struct hv_devid *xxx to struct hv_devid *hv_devid given code\n paths involve many types of device ids\n o Fix indentation in a large if block by using goto.\n\nThere are no functional changes.\n\nReviewed-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>\nSigned-off-by: Mukesh R <mrathor@linux.microsoft.com>\n---\n arch/x86/hyperv/irqdomain.c | 198 +++++++++++++++++++-----------------\n 1 file changed, 104 insertions(+), 94 deletions(-)", "diff": "diff --git a/arch/x86/hyperv/irqdomain.c b/arch/x86/hyperv/irqdomain.c\nindex 365e364268d9..b3ad50a874dc 100644\n--- a/arch/x86/hyperv/irqdomain.c\n+++ b/arch/x86/hyperv/irqdomain.c\n@@ -1,5 +1,4 @@\n // SPDX-License-Identifier: GPL-2.0\n-\n /*\n * Irqdomain for Linux to run as the root partition on Microsoft Hypervisor.\n *\n@@ -14,8 +13,8 @@\n #include <linux/irqchip/irq-msi-lib.h>\n #include <asm/mshyperv.h>\n \n-static int hv_map_interrupt(union hv_device_id device_id, bool level,\n-\t\tint cpu, int vector, struct hv_interrupt_entry *entry)\n+static int hv_map_interrupt(union hv_device_id hv_devid, bool level,\n+\t\tint cpu, int vector, struct hv_interrupt_entry *ret_entry)\n {\n \tstruct hv_input_map_device_interrupt *input;\n \tstruct hv_output_map_device_interrupt *output;\n@@ -32,7 +31,7 @@ static int hv_map_interrupt(union hv_device_id device_id, bool level,\n \tintr_desc = &input->interrupt_descriptor;\n \tmemset(input, 0, sizeof(*input));\n \tinput->partition_id = hv_current_partition_id;\n-\tinput->device_id = device_id.as_uint64;\n+\tinput->device_id = hv_devid.as_uint64;\n \tintr_desc->interrupt_type = HV_X64_INTERRUPT_TYPE_FIXED;\n \tintr_desc->vector_count = 1;\n \tintr_desc->target.vector = vector;\n@@ -44,7 +43,7 @@ static int hv_map_interrupt(union hv_device_id device_id, bool level,\n \n \tintr_desc->target.vp_set.valid_bank_mask = 0;\n \tintr_desc->target.vp_set.format = HV_GENERIC_SET_SPARSE_4K;\n-\tnr_bank = cpumask_to_vpset(&(intr_desc->target.vp_set), cpumask_of(cpu));\n+\tnr_bank = cpumask_to_vpset(&intr_desc->target.vp_set, cpumask_of(cpu));\n \tif (nr_bank < 0) {\n \t\tlocal_irq_restore(flags);\n \t\tpr_err(\"%s: unable to generate VP set\\n\", __func__);\n@@ -61,7 +60,7 @@ static int hv_map_interrupt(union hv_device_id device_id, bool level,\n \n \tstatus = hv_do_rep_hypercall(HVCALL_MAP_DEVICE_INTERRUPT, 0, var_size,\n \t\t\tinput, output);\n-\t*entry = output->interrupt_entry;\n+\t*ret_entry = output->interrupt_entry;\n \n \tlocal_irq_restore(flags);\n \n@@ -71,21 +70,19 @@ static int hv_map_interrupt(union hv_device_id device_id, bool level,\n \treturn hv_result_to_errno(status);\n }\n \n-static int hv_unmap_interrupt(u64 id, struct hv_interrupt_entry *old_entry)\n+static int hv_unmap_interrupt(u64 id, struct hv_interrupt_entry *irq_entry)\n {\n \tunsigned long flags;\n \tstruct hv_input_unmap_device_interrupt *input;\n-\tstruct hv_interrupt_entry *intr_entry;\n \tu64 status;\n \n \tlocal_irq_save(flags);\n \tinput = *this_cpu_ptr(hyperv_pcpu_input_arg);\n \n \tmemset(input, 0, sizeof(*input));\n-\tintr_entry = &input->interrupt_entry;\n \tinput->partition_id = hv_current_partition_id;\n \tinput->device_id = id;\n-\t*intr_entry = *old_entry;\n+\tinput->interrupt_entry = *irq_entry;\n \n \tstatus = hv_do_hypercall(HVCALL_UNMAP_DEVICE_INTERRUPT, input, NULL);\n \tlocal_irq_restore(flags);\n@@ -115,67 +112,71 @@ static int get_rid_cb(struct pci_dev *pdev, u16 alias, void *data)\n \treturn 0;\n }\n \n-static union hv_device_id hv_build_pci_dev_id(struct pci_dev *dev)\n+static union hv_device_id hv_build_devid_type_pci(struct pci_dev *pdev)\n {\n-\tunion hv_device_id dev_id;\n+\tint pos;\n+\tunion hv_device_id hv_devid;\n \tstruct rid_data data = {\n \t\t.bridge = NULL,\n-\t\t.rid = PCI_DEVID(dev->bus->number, dev->devfn)\n+\t\t.rid = PCI_DEVID(pdev->bus->number, pdev->devfn)\n \t};\n \n-\tpci_for_each_dma_alias(dev, get_rid_cb, &data);\n+\tpci_for_each_dma_alias(pdev, get_rid_cb, &data);\n \n-\tdev_id.as_uint64 = 0;\n-\tdev_id.device_type = HV_DEVICE_TYPE_PCI;\n-\tdev_id.pci.segment = pci_domain_nr(dev->bus);\n+\thv_devid.as_uint64 = 0;\n+\thv_devid.device_type = HV_DEVICE_TYPE_PCI;\n+\thv_devid.pci.segment = pci_domain_nr(pdev->bus);\n \n-\tdev_id.pci.bdf.bus = PCI_BUS_NUM(data.rid);\n-\tdev_id.pci.bdf.device = PCI_SLOT(data.rid);\n-\tdev_id.pci.bdf.function = PCI_FUNC(data.rid);\n-\tdev_id.pci.source_shadow = HV_SOURCE_SHADOW_NONE;\n+\thv_devid.pci.bdf.bus = PCI_BUS_NUM(data.rid);\n+\thv_devid.pci.bdf.device = PCI_SLOT(data.rid);\n+\thv_devid.pci.bdf.function = PCI_FUNC(data.rid);\n+\thv_devid.pci.source_shadow = HV_SOURCE_SHADOW_NONE;\n \n-\tif (data.bridge) {\n-\t\tint pos;\n+\tif (data.bridge == NULL)\n+\t\tgoto out;\n \n-\t\t/*\n-\t\t * Microsoft Hypervisor requires a bus range when the bridge is\n-\t\t * running in PCI-X mode.\n-\t\t *\n-\t\t * To distinguish conventional vs PCI-X bridge, we can check\n-\t\t * the bridge's PCI-X Secondary Status Register, Secondary Bus\n-\t\t * Mode and Frequency bits. See PCI Express to PCI/PCI-X Bridge\n-\t\t * Specification Revision 1.0 5.2.2.1.3.\n-\t\t *\n-\t\t * Value zero means it is in conventional mode, otherwise it is\n-\t\t * in PCI-X mode.\n-\t\t */\n+\t/*\n+\t * Microsoft Hypervisor requires a bus range when the bridge is\n+\t * running in PCI-X mode.\n+\t *\n+\t * To distinguish conventional vs PCI-X bridge, we can check\n+\t * the bridge's PCI-X Secondary Status Register, Secondary Bus\n+\t * Mode and Frequency bits. See PCI Express to PCI/PCI-X Bridge\n+\t * Specification Revision 1.0 5.2.2.1.3.\n+\t *\n+\t * Value zero means it is in conventional mode, otherwise it is\n+\t * in PCI-X mode.\n+\t */\n \n-\t\tpos = pci_find_capability(data.bridge, PCI_CAP_ID_PCIX);\n-\t\tif (pos) {\n-\t\t\tu16 status;\n+\tpos = pci_find_capability(data.bridge, PCI_CAP_ID_PCIX);\n+\tif (pos) {\n+\t\tu16 status;\n \n-\t\t\tpci_read_config_word(data.bridge, pos +\n-\t\t\t\t\tPCI_X_BRIDGE_SSTATUS, &status);\n+\t\tpci_read_config_word(data.bridge, pos + PCI_X_BRIDGE_SSTATUS,\n+\t\t\t\t &status);\n \n-\t\t\tif (status & PCI_X_SSTATUS_FREQ) {\n-\t\t\t\t/* Non-zero, PCI-X mode */\n-\t\t\t\tu8 sec_bus, sub_bus;\n+\t\tif (status & PCI_X_SSTATUS_FREQ) {\n+\t\t\t/* Non-zero, PCI-X mode */\n+\t\t\tu8 sec_bus, sub_bus;\n \n-\t\t\t\tdev_id.pci.source_shadow = HV_SOURCE_SHADOW_BRIDGE_BUS_RANGE;\n+\t\t\thv_devid.pci.source_shadow =\n+\t\t\t\t\t HV_SOURCE_SHADOW_BRIDGE_BUS_RANGE;\n \n-\t\t\t\tpci_read_config_byte(data.bridge, PCI_SECONDARY_BUS, &sec_bus);\n-\t\t\t\tdev_id.pci.shadow_bus_range.secondary_bus = sec_bus;\n-\t\t\t\tpci_read_config_byte(data.bridge, PCI_SUBORDINATE_BUS, &sub_bus);\n-\t\t\t\tdev_id.pci.shadow_bus_range.subordinate_bus = sub_bus;\n-\t\t\t}\n+\t\t\tpci_read_config_byte(data.bridge, PCI_SECONDARY_BUS,\n+\t\t\t\t\t &sec_bus);\n+\t\t\thv_devid.pci.shadow_bus_range.secondary_bus = sec_bus;\n+\t\t\tpci_read_config_byte(data.bridge, PCI_SUBORDINATE_BUS,\n+\t\t\t\t\t &sub_bus);\n+\t\t\thv_devid.pci.shadow_bus_range.subordinate_bus = sub_bus;\n \t\t}\n \t}\n \n-\treturn dev_id;\n+out:\n+\treturn hv_devid;\n }\n \n-/**\n- * hv_map_msi_interrupt() - \"Map\" the MSI IRQ in the hypervisor.\n+/*\n+ * hv_map_msi_interrupt() - Map the MSI IRQ in the hypervisor.\n * @data: Describes the IRQ\n * @out_entry: Hypervisor (MSI) interrupt entry (can be NULL)\n *\n@@ -188,22 +189,23 @@ int hv_map_msi_interrupt(struct irq_data *data,\n {\n \tstruct irq_cfg *cfg = irqd_cfg(data);\n \tstruct hv_interrupt_entry dummy;\n-\tunion hv_device_id device_id;\n+\tunion hv_device_id hv_devid;\n \tstruct msi_desc *msidesc;\n-\tstruct pci_dev *dev;\n+\tstruct pci_dev *pdev;\n \tint cpu;\n \n \tmsidesc = irq_data_get_msi_desc(data);\n-\tdev = msi_desc_to_pci_dev(msidesc);\n-\tdevice_id = hv_build_pci_dev_id(dev);\n+\tpdev = msi_desc_to_pci_dev(msidesc);\n+\thv_devid = hv_build_devid_type_pci(pdev);\n \tcpu = cpumask_first(irq_data_get_effective_affinity_mask(data));\n \n-\treturn hv_map_interrupt(device_id, false, cpu, cfg->vector,\n+\treturn hv_map_interrupt(hv_devid, false, cpu, cfg->vector,\n \t\t\t\tout_entry ? out_entry : &dummy);\n }\n EXPORT_SYMBOL_GPL(hv_map_msi_interrupt);\n \n-static inline void entry_to_msi_msg(struct hv_interrupt_entry *entry, struct msi_msg *msg)\n+static void entry_to_msi_msg(struct hv_interrupt_entry *entry,\n+\t\t\t struct msi_msg *msg)\n {\n \t/* High address is always 0 */\n \tmsg->address_hi = 0;\n@@ -211,17 +213,19 @@ static inline void entry_to_msi_msg(struct hv_interrupt_entry *entry, struct msi\n \tmsg->data = entry->msi_entry.data.as_uint32;\n }\n \n-static int hv_unmap_msi_interrupt(struct pci_dev *dev, struct hv_interrupt_entry *old_entry);\n+static int hv_unmap_msi_interrupt(struct pci_dev *pdev,\n+\t\t\t\t struct hv_interrupt_entry *irq_entry);\n+\n static void hv_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)\n {\n \tstruct hv_interrupt_entry *stored_entry;\n \tstruct irq_cfg *cfg = irqd_cfg(data);\n \tstruct msi_desc *msidesc;\n-\tstruct pci_dev *dev;\n+\tstruct pci_dev *pdev;\n \tint ret;\n \n \tmsidesc = irq_data_get_msi_desc(data);\n-\tdev = msi_desc_to_pci_dev(msidesc);\n+\tpdev = msi_desc_to_pci_dev(msidesc);\n \n \tif (!cfg) {\n \t\tpr_debug(\"%s: cfg is NULL\", __func__);\n@@ -240,7 +244,7 @@ static void hv_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)\n \t\tstored_entry = data->chip_data;\n \t\tdata->chip_data = NULL;\n \n-\t\tret = hv_unmap_msi_interrupt(dev, stored_entry);\n+\t\tret = hv_unmap_msi_interrupt(pdev, stored_entry);\n \n \t\tkfree(stored_entry);\n \n@@ -249,10 +253,8 @@ static void hv_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)\n \t}\n \n \tstored_entry = kzalloc_obj(*stored_entry, GFP_ATOMIC);\n-\tif (!stored_entry) {\n-\t\tpr_debug(\"%s: failed to allocate chip data\\n\", __func__);\n+\tif (!stored_entry)\n \t\treturn;\n-\t}\n \n \tret = hv_map_msi_interrupt(data, stored_entry);\n \tif (ret) {\n@@ -262,18 +264,21 @@ static void hv_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)\n \n \tdata->chip_data = stored_entry;\n \tentry_to_msi_msg(data->chip_data, msg);\n-\n-\treturn;\n }\n \n-static int hv_unmap_msi_interrupt(struct pci_dev *dev, struct hv_interrupt_entry *old_entry)\n+static int hv_unmap_msi_interrupt(struct pci_dev *pdev,\n+\t\t\t\t struct hv_interrupt_entry *irq_entry)\n {\n-\treturn hv_unmap_interrupt(hv_build_pci_dev_id(dev).as_uint64, old_entry);\n+\tunion hv_device_id hv_devid;\n+\n+\thv_devid = hv_build_devid_type_pci(pdev);\n+\treturn hv_unmap_interrupt(hv_devid.as_uint64, irq_entry);\n }\n \n-static void hv_teardown_msi_irq(struct pci_dev *dev, struct irq_data *irqd)\n+/* NB: during map, hv_interrupt_entry is saved via data->chip_data */\n+static void hv_teardown_msi_irq(struct pci_dev *pdev, struct irq_data *irqd)\n {\n-\tstruct hv_interrupt_entry old_entry;\n+\tstruct hv_interrupt_entry irq_entry;\n \tstruct msi_msg msg;\n \n \tif (!irqd->chip_data) {\n@@ -281,13 +286,13 @@ static void hv_teardown_msi_irq(struct pci_dev *dev, struct irq_data *irqd)\n \t\treturn;\n \t}\n \n-\told_entry = *(struct hv_interrupt_entry *)irqd->chip_data;\n-\tentry_to_msi_msg(&old_entry, &msg);\n+\tirq_entry = *(struct hv_interrupt_entry *)irqd->chip_data;\n+\tentry_to_msi_msg(&irq_entry, &msg);\n \n \tkfree(irqd->chip_data);\n \tirqd->chip_data = NULL;\n \n-\t(void)hv_unmap_msi_interrupt(dev, &old_entry);\n+\t(void)hv_unmap_msi_interrupt(pdev, &irq_entry);\n }\n \n /*\n@@ -302,7 +307,8 @@ static struct irq_chip hv_pci_msi_controller = {\n };\n \n static bool hv_init_dev_msi_info(struct device *dev, struct irq_domain *domain,\n-\t\t\t\t struct irq_domain *real_parent, struct msi_domain_info *info)\n+\t\t\t\t struct irq_domain *real_parent,\n+\t\t\t\t struct msi_domain_info *info)\n {\n \tstruct irq_chip *chip = info->chip;\n \n@@ -317,7 +323,8 @@ static bool hv_init_dev_msi_info(struct device *dev, struct irq_domain *domain,\n }\n \n #define HV_MSI_FLAGS_SUPPORTED\t(MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX)\n-#define HV_MSI_FLAGS_REQUIRED\t(MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS)\n+#define HV_MSI_FLAGS_REQUIRED\t(MSI_FLAG_USE_DEF_DOM_OPS |\t\\\n+\t\t\t\t MSI_FLAG_USE_DEF_CHIP_OPS)\n \n static struct msi_parent_ops hv_msi_parent_ops = {\n \t.supported_flags\t= HV_MSI_FLAGS_SUPPORTED,\n@@ -329,14 +336,14 @@ static struct msi_parent_ops hv_msi_parent_ops = {\n \t.init_dev_msi_info\t= hv_init_dev_msi_info,\n };\n \n-static int hv_msi_domain_alloc(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs,\n-\t\t\t void *arg)\n+/* Allocate nr_irqs IRQs for the given irq domain */\n+static int hv_msi_domain_alloc(struct irq_domain *d, unsigned int virq,\n+\t\t\t unsigned int nr_irqs, void *arg)\n {\n \t/*\n-\t * TODO: The allocation bits of hv_irq_compose_msi_msg(), i.e. everything except\n-\t * entry_to_msi_msg() should be in here.\n+\t * TODO: The allocation bits of hv_irq_compose_msi_msg(), i.e.\n+\t *\t everything except entry_to_msi_msg() should be in here.\n \t */\n-\n \tint ret;\n \n \tret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, arg);\n@@ -344,13 +351,15 @@ static int hv_msi_domain_alloc(struct irq_domain *d, unsigned int virq, unsigned\n \t\treturn ret;\n \n \tfor (int i = 0; i < nr_irqs; ++i) {\n-\t\tirq_domain_set_info(d, virq + i, 0, &hv_pci_msi_controller, NULL,\n-\t\t\t\t handle_edge_irq, NULL, \"edge\");\n+\t\tirq_domain_set_info(d, virq + i, 0, &hv_pci_msi_controller,\n+\t\t\t\t NULL, handle_edge_irq, NULL, \"edge\");\n \t}\n+\n \treturn 0;\n }\n \n-static void hv_msi_domain_free(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs)\n+static void hv_msi_domain_free(struct irq_domain *d, unsigned int virq,\n+\t\t\t unsigned int nr_irqs)\n {\n \tfor (int i = 0; i < nr_irqs; ++i) {\n \t\tstruct irq_data *irqd = irq_domain_get_irq_data(d, virq);\n@@ -362,6 +371,7 @@ static void hv_msi_domain_free(struct irq_domain *d, unsigned int virq, unsigned\n \n \t\thv_teardown_msi_irq(to_pci_dev(desc->dev), irqd);\n \t}\n+\n \tirq_domain_free_irqs_top(d, virq, nr_irqs);\n }\n \n@@ -394,25 +404,25 @@ struct irq_domain * __init hv_create_pci_msi_domain(void)\n \n int hv_unmap_ioapic_interrupt(int ioapic_id, struct hv_interrupt_entry *entry)\n {\n-\tunion hv_device_id device_id;\n+\tunion hv_device_id hv_devid;\n \n-\tdevice_id.as_uint64 = 0;\n-\tdevice_id.device_type = HV_DEVICE_TYPE_IOAPIC;\n-\tdevice_id.ioapic.ioapic_id = (u8)ioapic_id;\n+\thv_devid.as_uint64 = 0;\n+\thv_devid.device_type = HV_DEVICE_TYPE_IOAPIC;\n+\thv_devid.ioapic.ioapic_id = (u8)ioapic_id;\n \n-\treturn hv_unmap_interrupt(device_id.as_uint64, entry);\n+\treturn hv_unmap_interrupt(hv_devid.as_uint64, entry);\n }\n EXPORT_SYMBOL_GPL(hv_unmap_ioapic_interrupt);\n \n int hv_map_ioapic_interrupt(int ioapic_id, bool level, int cpu, int vector,\n \t\tstruct hv_interrupt_entry *entry)\n {\n-\tunion hv_device_id device_id;\n+\tunion hv_device_id hv_devid;\n \n-\tdevice_id.as_uint64 = 0;\n-\tdevice_id.device_type = HV_DEVICE_TYPE_IOAPIC;\n-\tdevice_id.ioapic.ioapic_id = (u8)ioapic_id;\n+\thv_devid.as_uint64 = 0;\n+\thv_devid.device_type = HV_DEVICE_TYPE_IOAPIC;\n+\thv_devid.ioapic.ioapic_id = (u8)ioapic_id;\n \n-\treturn hv_map_interrupt(device_id, level, cpu, vector, entry);\n+\treturn hv_map_interrupt(hv_devid, level, cpu, vector, entry);\n }\n EXPORT_SYMBOL_GPL(hv_map_ioapic_interrupt);\n", "prefixes": [ "V1", "02/13" ] }