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GET /api/patches/2225825/?format=api
{ "id": 2225825, "url": "http://patchwork.ozlabs.org/api/patches/2225825/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162912.3295598-3-jim.shu@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421162912.3295598-3-jim.shu@sifive.com>", "list_archive_url": null, "date": "2026-04-21T16:29:09", "name": "[v2,2/5] accel/tcg: address_space_translate*() will pass the correct iommu_flags", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2ce704339efe8b10036c0a66f88786d7e10236e0", "submitter": { "id": 83153, "url": "http://patchwork.ozlabs.org/api/people/83153/?format=api", "name": "Jim Shu", "email": "jim.shu@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162912.3295598-3-jim.shu@sifive.com/mbox/", "series": [ { "id": 500851, "url": "http://patchwork.ozlabs.org/api/series/500851/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500851", "date": "2026-04-21T16:29:09", "name": "Defer the IOMMU translation and support access_type", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500851/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225825/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225825/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=IbfLGVPn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" <edgar.iglesias@gmail.com>,\n Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Stafford Horne <shorne@gmail.com>,\n Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>,\n Glenn Miles <milesg@linux.ibm.com>, Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>,\n Yoshinori Sato <yoshinori.sato@nifty.com>,\n Ilya Leoshkevich <iii@linux.ibm.com>, David Hildenbrand <david@kernel.org>,\n Cornelia Huck <cohuck@redhat.com>, Eric Farman <farman@linux.ibm.com>,\n Matthew Rosato <mjrosato@linux.ibm.com>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Artyom Tarasenko <atar4qemu@gmail.com>,\n Bastian Koppelmann <kbastian@rumtueddeln.de>,\n Max Filippov <jcmvbkbc@gmail.com>,\n qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs),\n qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu <jim.shu@sifive.com>", "Subject": "[PATCH v2 2/5] accel/tcg: address_space_translate*() will pass the\n correct iommu_flags", "Date": "Wed, 22 Apr 2026 00:29:09 +0800", "Message-ID": "<20260421162912.3295598-3-jim.shu@sifive.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260421162912.3295598-1-jim.shu@sifive.com>", "References": "<20260421162912.3295598-1-jim.shu@sifive.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::102c;\n envelope-from=jim.shu@sifive.com; helo=mail-pj1-x102c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Instead of IOMMU_NONE, address_space_translate_for_iotlb() now can pass\nthe correct iommu_flags to the IOMMU translate function from the\naccess_type.\n\nSince RISC-V wgChecker [1] could permit access in RO or WO permission\nonly, the IOMMUMemoryRegion could return different section for\nread and write access. To support this kind of IOMMUMemoryRegion\nin the path of CPU access, we should pass correct iommu_flags here.\n\n[1] RISC-V WG:\nhttps://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/\n\nSigned-off-by: Jim Shu <jim.shu@sifive.com>\n---\n accel/tcg/cputlb.c | 3 ++-\n include/accel/tcg/iommu.h | 12 +++++-------\n system/physmem.c | 16 +++++++++++-----\n 3 files changed, 18 insertions(+), 13 deletions(-)", "diff": "diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c\nindex 3bc951603dc..4ca4152579b 100644\n--- a/accel/tcg/cputlb.c\n+++ b/accel/tcg/cputlb.c\n@@ -1050,7 +1050,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,\n prot = full->prot;\n asidx = cpu_asidx_from_attrs(cpu, full->attrs);\n section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,\n- &xlat, &sz, full->attrs, &prot);\n+ &xlat, &sz, full->attrs, &prot,\n+ access_type);\n assert(sz >= TARGET_PAGE_SIZE);\n \n tlb_debug(\"vaddr=%016\" VADDR_PRIx \" paddr=0x\" HWADDR_FMT_plx\ndiff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h\nindex 547f8ea0ef0..30655aab4ba 100644\n--- a/include/accel/tcg/iommu.h\n+++ b/include/accel/tcg/iommu.h\n@@ -14,13 +14,11 @@\n #include \"exec/hwaddr.h\"\n #include \"exec/memattrs.h\"\n \n-MemoryRegionSection *address_space_translate_for_iotlb(CPUState *cpu,\n- int asidx,\n- hwaddr addr,\n- hwaddr *xlat,\n- hwaddr *plen,\n- MemTxAttrs attrs,\n- int *prot);\n+MemoryRegionSection *\n+address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot,\n+ MMUAccessType access_type);\n \n #endif\n \ndiff --git a/system/physmem.c b/system/physmem.c\nindex 4e26f1a1d42..d3d111392c1 100644\n--- a/system/physmem.c\n+++ b/system/physmem.c\n@@ -685,12 +685,14 @@ void tcg_iommu_init_notifier_list(CPUState *cpu)\n MemoryRegionSection *\n address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n hwaddr *xlat, hwaddr *plen,\n- MemTxAttrs attrs, int *prot)\n+ MemTxAttrs attrs, int *prot,\n+ MMUAccessType access_type)\n {\n MemoryRegionSection *section;\n IOMMUMemoryRegion *iommu_mr;\n IOMMUMemoryRegionClass *imrc;\n IOMMUTLBEntry iotlb;\n+ IOMMUAccessFlags iommu_flags;\n int iommu_idx;\n hwaddr addr = orig_addr;\n AddressSpaceDispatch *d = address_space_to_dispatch(cpu->cpu_ases[asidx].as);\n@@ -707,10 +709,14 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n \n iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);\n tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);\n- /* We need all the permissions, so pass IOMMU_NONE so the IOMMU\n- * doesn't short-cut its translation table walk.\n- */\n- iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);\n+\n+ if (access_type == MMU_DATA_STORE) {\n+ iommu_flags = IOMMU_WO;\n+ } else {\n+ iommu_flags = IOMMU_RO;\n+ }\n+\n+ iotlb = imrc->translate(iommu_mr, addr, iommu_flags, iommu_idx);\n addr = ((iotlb.translated_addr & ~iotlb.addr_mask)\n | (addr & iotlb.addr_mask));\n /* Update the caller's prot bits to remove permissions the IOMMU\n", "prefixes": [ "v2", "2/5" ] }