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GET /api/patches/2225772/?format=api
{ "id": 2225772, "url": "http://patchwork.ozlabs.org/api/patches/2225772/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260421-io_projection-v2-9-4c251c692ef4@garyguo.net/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-io_projection-v2-9-4c251c692ef4@garyguo.net>", "list_archive_url": null, "date": "2026-04-21T14:56:20", "name": "[v2,09/11] gpu: nova-core: use I/O projection for cleaner encapsulation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "231ecb3c383619b1e0508f1aa825fc0ac4213474", "submitter": { "id": 76823, "url": "http://patchwork.ozlabs.org/api/people/76823/?format=api", "name": "Gary Guo", "email": "gary@garyguo.net" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260421-io_projection-v2-9-4c251c692ef4@garyguo.net/mbox/", "series": [ { "id": 500833, "url": "http://patchwork.ozlabs.org/api/series/500833/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500833", "date": "2026-04-21T14:56:19", "name": "rust: I/O type generalization and projection", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500833/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225772/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225772/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52846-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=garyguo.net header.i=@garyguo.net header.a=rsa-sha256\n header.s=selector1 header.b=gzRkEzbu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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Wysocki\" <rafael@kernel.org>, Danilo Krummrich <dakr@kernel.org>,\n Miguel Ojeda <ojeda@kernel.org>, Boqun Feng <boqun@kernel.org>,\n Gary Guo <gary@garyguo.net>,\n =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= <bjorn3_gh@protonmail.com>,\n Benno Lossin <lossin@kernel.org>, Andreas Hindborg <a.hindborg@kernel.org>,\n Alice Ryhl <aliceryhl@google.com>, Trevor Gross <tmgross@umich.edu>,\n Daniel Almeida <daniel.almeida@collabora.com>,\n Bjorn Helgaas <bhelgaas@google.com>,\n =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= <kwilczynski@kernel.org>,\n Abdiel Janulgue <abdiel.janulgue@gmail.com>,\n Robin Murphy <robin.murphy@arm.com>,\n Alexandre Courbot <acourbot@nvidia.com>, David Airlie <airlied@gmail.com>,\n Simona Vetter <simona@ffwll.ch>", "Cc": "driver-core@lists.linux.dev, rust-for-linux@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=ed25519-sha256; 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"X-OriginatorOrg": "garyguo.net", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5c296a16-dfaa-4fd9-dd00-08de9fb62c0d", "X-MS-Exchange-CrossTenant-AuthSource": "LOVP265MB8871.GBRP265.PROD.OUTLOOK.COM", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Apr 2026 14:56:30.5875\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "bbc898ad-b10f-4e10-8552-d9377b823d45", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n Gg69nrHXe4QMRqc7yH4sTiMLuBCps5XOEV1dwENujYmYhwC78E5xtjZVSJMtQ2GPyj1qkMRusR2Ckh3s/6G2Aw==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CWLP265MB5674" }, "content": "Use `io_project!` for PTE array and message queues to remove the\nbreak off encapsulation.\n\nThe remaining `dma_read!` and `dma_write!` is now only acting on\nprimitives; thus replace by `io_read!` and `io_write!`.\n\nSigned-off-by: Gary Guo <gary@garyguo.net>\n---\n drivers/gpu/nova-core/gsp.rs | 44 +++++++++++---------\n drivers/gpu/nova-core/gsp/cmdq.rs | 65 +++++++++++++++++-------------\n drivers/gpu/nova-core/gsp/fw.rs | 84 +++++++++++++++------------------------\n 3 files changed, 94 insertions(+), 99 deletions(-)", "diff": "diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs\nindex ba5b7f990031..225a77a2f464 100644\n--- a/drivers/gpu/nova-core/gsp.rs\n+++ b/drivers/gpu/nova-core/gsp.rs\n@@ -10,8 +10,14 @@\n CoherentBox,\n DmaAddress, //\n },\n+ io::{\n+ self,\n+ io_project,\n+ io_write, //\n+ },\n pci,\n prelude::*,\n+ ptr::KnownSize,\n transmute::{\n AsBytes,\n FromBytes, //\n@@ -55,12 +61,20 @@ unsafe impl<const NUM_ENTRIES: usize> FromBytes for PteArray<NUM_ENTRIES> {}\n unsafe impl<const NUM_ENTRIES: usize> AsBytes for PteArray<NUM_ENTRIES> {}\n \n impl<const NUM_PAGES: usize> PteArray<NUM_PAGES> {\n- /// Returns the page table entry for `index`, for a mapping starting at `start`.\n- // TODO: Replace with `IoView` projection once available.\n- fn entry(start: DmaAddress, index: usize) -> Result<u64> {\n- start\n- .checked_add(num::usize_as_u64(index) << GSP_PAGE_SHIFT)\n- .ok_or(EOVERFLOW)\n+ /// Initialize a new page table array mapping `NUM_PAGES` GSP pages starting at address `start`.\n+ fn init<T: KnownSize + ?Sized>(\n+ view: io::View<'_, Coherent<T>, Self>,\n+ start: DmaAddress,\n+ ) -> Result<()> {\n+ for i in 0..NUM_PAGES {\n+ io_write!(view, .0[build: i],\n+ start\n+ .checked_add(num::usize_as_u64(i) << GSP_PAGE_SHIFT)\n+ .ok_or(EOVERFLOW)?\n+ );\n+ }\n+\n+ Ok(())\n }\n }\n \n@@ -86,18 +100,12 @@ fn new(dev: &device::Device<device::Bound>) -> Result<Self> {\n let obj = Self(Coherent::zeroed(dev, GFP_KERNEL)?);\n \n let start_addr = obj.0.dma_handle();\n-\n- // SAFETY: `obj` has just been created and we are its sole user.\n- let pte_region = unsafe {\n- &mut obj.0.as_mut()[size_of::<u64>()..][..RM_LOG_BUFFER_NUM_PAGES * size_of::<u64>()]\n- };\n-\n- // Write values one by one to avoid an on-stack instance of `PteArray`.\n- for (i, chunk) in pte_region.chunks_exact_mut(size_of::<u64>()).enumerate() {\n- let pte_value = PteArray::<0>::entry(start_addr, i)?;\n-\n- chunk.copy_from_slice(&pte_value.to_ne_bytes());\n- }\n+ let pte_view = io_project!(\n+ obj.0,\n+ [build: size_of::<u64>()..][build: ..RM_LOG_BUFFER_NUM_PAGES * size_of::<u64>()]\n+ )\n+ .try_cast::<PteArray<RM_LOG_BUFFER_NUM_PAGES>>()?;\n+ PteArray::init(pte_view, start_addr)?;\n \n Ok(obj)\n }\ndiff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs\nindex 0b51e10e2cfc..d424d047c970 100644\n--- a/drivers/gpu/nova-core/gsp/cmdq.rs\n+++ b/drivers/gpu/nova-core/gsp/cmdq.rs\n@@ -2,16 +2,23 @@\n \n mod continuation;\n \n-use core::mem;\n+use core::{\n+ mem,\n+ sync::atomic::{\n+ fence,\n+ Ordering, //\n+ },\n+};\n \n use kernel::{\n device,\n dma::{\n Coherent,\n+ CoherentBox,\n DmaAddress, //\n },\n- dma_write,\n io::{\n+ io_project,\n poll::read_poll_timeout,\n Io, //\n },\n@@ -171,20 +178,18 @@ struct MsgqData {\n #[repr(C)]\n // There is no struct defined for this in the open-gpu-kernel-source headers.\n // Instead it is defined by code in `GspMsgQueuesInit()`.\n-// TODO: Revert to private once `IoView` projections replace the `gsp_mem` module.\n-pub(super) struct Msgq {\n+struct Msgq {\n /// Header for sending messages, including the write pointer.\n- pub(super) tx: MsgqTxHeader,\n+ tx: MsgqTxHeader,\n /// Header for receiving messages, including the read pointer.\n- pub(super) rx: MsgqRxHeader,\n+ rx: MsgqRxHeader,\n /// The message queue proper.\n msgq: MsgqData,\n }\n \n /// Structure shared between the driver and the GSP and containing the command and message queues.\n #[repr(C)]\n-// TODO: Revert to private once `IoView` projections replace the `gsp_mem` module.\n-pub(super) struct GspMem {\n+struct GspMem {\n /// Self-mapping page table entries.\n ptes: PteArray<{ Self::PTE_ARRAY_SIZE }>,\n /// CPU queue: the driver writes commands here, and the GSP reads them. It also contains the\n@@ -192,13 +197,13 @@ pub(super) struct GspMem {\n /// index into the GSP queue.\n ///\n /// This member is read-only for the GSP.\n- pub(super) cpuq: Msgq,\n+ cpuq: Msgq,\n /// GSP queue: the GSP writes messages here, and the driver reads them. It also contains the\n /// write and read pointers that the GSP updates. This means that the read pointer here is an\n /// index into the CPU queue.\n ///\n /// This member is read-only for the driver.\n- pub(super) gspq: Msgq,\n+ gspq: Msgq,\n }\n \n impl GspMem {\n@@ -232,20 +237,13 @@ fn new(dev: &device::Device<device::Bound>) -> Result<Self> {\n const MSGQ_SIZE: u32 = num::usize_into_u32::<{ size_of::<Msgq>() }>();\n const RX_HDR_OFF: u32 = num::usize_into_u32::<{ mem::offset_of!(Msgq, rx) }>();\n \n- let gsp_mem = Coherent::<GspMem>::zeroed(dev, GFP_KERNEL)?;\n+ let mut gsp_mem = CoherentBox::<GspMem>::zeroed(dev, GFP_KERNEL)?;\n+ gsp_mem.cpuq.tx = MsgqTxHeader::new(MSGQ_SIZE, RX_HDR_OFF, MSGQ_NUM_PAGES);\n+ gsp_mem.cpuq.rx = MsgqRxHeader::new();\n \n+ let gsp_mem: Coherent<_> = gsp_mem.into();\n let start = gsp_mem.dma_handle();\n- // Write values one by one to avoid an on-stack instance of `PteArray`.\n- for i in 0..GspMem::PTE_ARRAY_SIZE {\n- dma_write!(gsp_mem, .ptes.0[build: i], PteArray::<0>::entry(start, i)?);\n- }\n-\n- dma_write!(\n- gsp_mem,\n- .cpuq.tx,\n- MsgqTxHeader::new(MSGQ_SIZE, RX_HDR_OFF, MSGQ_NUM_PAGES)\n- );\n- dma_write!(gsp_mem, .cpuq.rx, MsgqRxHeader::new());\n+ PteArray::init(io_project!(gsp_mem, .ptes), start)?;\n \n Ok(Self(gsp_mem))\n }\n@@ -420,7 +418,7 @@ fn allocate_command(&mut self, size: usize, timeout: Delta) -> Result<GspCommand\n //\n // - The returned value is within `0..MSGQ_NUM_PAGES`.\n fn gsp_write_ptr(&self) -> u32 {\n- super::fw::gsp_mem::gsp_write_ptr(&self.0)\n+ MsgqTxHeader::write_ptr(io_project!(self.0, .gspq.tx)) % MSGQ_NUM_PAGES\n }\n \n // Returns the index of the memory page the GSP will read the next command from.\n@@ -429,7 +427,7 @@ fn gsp_write_ptr(&self) -> u32 {\n //\n // - The returned value is within `0..MSGQ_NUM_PAGES`.\n fn gsp_read_ptr(&self) -> u32 {\n- super::fw::gsp_mem::gsp_read_ptr(&self.0)\n+ MsgqRxHeader::read_ptr(io_project!(self.0, .gspq.rx)) % MSGQ_NUM_PAGES\n }\n \n // Returns the index of the memory page the CPU can read the next message from.\n@@ -438,12 +436,18 @@ fn gsp_read_ptr(&self) -> u32 {\n //\n // - The returned value is within `0..MSGQ_NUM_PAGES`.\n fn cpu_read_ptr(&self) -> u32 {\n- super::fw::gsp_mem::cpu_read_ptr(&self.0)\n+ MsgqRxHeader::read_ptr(io_project!(self.0, .cpuq.rx)) % MSGQ_NUM_PAGES\n }\n \n // Informs the GSP that it can send `elem_count` new pages into the message queue.\n fn advance_cpu_read_ptr(&mut self, elem_count: u32) {\n- super::fw::gsp_mem::advance_cpu_read_ptr(&self.0, elem_count)\n+ let rx = io_project!(self.0, .cpuq.rx);\n+ let rptr = MsgqRxHeader::read_ptr(rx).wrapping_add(elem_count) % MSGQ_NUM_PAGES;\n+\n+ // Ensure read pointer is properly ordered.\n+ fence(Ordering::SeqCst);\n+\n+ MsgqRxHeader::set_read_ptr(rx, rptr)\n }\n \n // Returns the index of the memory page the CPU can write the next command to.\n@@ -452,12 +456,17 @@ fn advance_cpu_read_ptr(&mut self, elem_count: u32) {\n //\n // - The returned value is within `0..MSGQ_NUM_PAGES`.\n fn cpu_write_ptr(&self) -> u32 {\n- super::fw::gsp_mem::cpu_write_ptr(&self.0)\n+ MsgqTxHeader::write_ptr(io_project!(self.0, .cpuq.tx)) % MSGQ_NUM_PAGES\n }\n \n // Informs the GSP that it can process `elem_count` new pages from the command queue.\n fn advance_cpu_write_ptr(&mut self, elem_count: u32) {\n- super::fw::gsp_mem::advance_cpu_write_ptr(&self.0, elem_count)\n+ let tx = io_project!(self.0, .cpuq.tx);\n+ let wptr = MsgqTxHeader::write_ptr(tx).wrapping_add(elem_count) % MSGQ_NUM_PAGES;\n+ MsgqTxHeader::set_write_ptr(tx, wptr);\n+\n+ // Ensure all command data is visible before triggering the GSP read.\n+ fence(Ordering::SeqCst);\n }\n }\n \ndiff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs\nindex 0c8a74f0e8ac..f2ba2f13e415 100644\n--- a/drivers/gpu/nova-core/gsp/fw.rs\n+++ b/drivers/gpu/nova-core/gsp/fw.rs\n@@ -10,6 +10,11 @@\n \n use kernel::{\n dma::Coherent,\n+ io::{\n+ self,\n+ io_read,\n+ io_write, //\n+ },\n prelude::*,\n ptr::{\n Alignable,\n@@ -40,59 +45,6 @@\n },\n };\n \n-// TODO: Replace with `IoView` projections once available.\n-pub(super) mod gsp_mem {\n- use core::sync::atomic::{\n- fence,\n- Ordering, //\n- };\n-\n- use kernel::{\n- dma::Coherent,\n- dma_read,\n- dma_write, //\n- };\n-\n- use crate::gsp::cmdq::{\n- GspMem,\n- MSGQ_NUM_PAGES, //\n- };\n-\n- pub(in crate::gsp) fn gsp_write_ptr(qs: &Coherent<GspMem>) -> u32 {\n- dma_read!(qs, .gspq.tx.0.writePtr) % MSGQ_NUM_PAGES\n- }\n-\n- pub(in crate::gsp) fn gsp_read_ptr(qs: &Coherent<GspMem>) -> u32 {\n- dma_read!(qs, .gspq.rx.0.readPtr) % MSGQ_NUM_PAGES\n- }\n-\n- pub(in crate::gsp) fn cpu_read_ptr(qs: &Coherent<GspMem>) -> u32 {\n- dma_read!(qs, .cpuq.rx.0.readPtr) % MSGQ_NUM_PAGES\n- }\n-\n- pub(in crate::gsp) fn advance_cpu_read_ptr(qs: &Coherent<GspMem>, count: u32) {\n- let rptr = cpu_read_ptr(qs).wrapping_add(count) % MSGQ_NUM_PAGES;\n-\n- // Ensure read pointer is properly ordered.\n- fence(Ordering::SeqCst);\n-\n- dma_write!(qs, .cpuq.rx.0.readPtr, rptr);\n- }\n-\n- pub(in crate::gsp) fn cpu_write_ptr(qs: &Coherent<GspMem>) -> u32 {\n- dma_read!(qs, .cpuq.tx.0.writePtr) % MSGQ_NUM_PAGES\n- }\n-\n- pub(in crate::gsp) fn advance_cpu_write_ptr(qs: &Coherent<GspMem>, count: u32) {\n- let wptr = cpu_write_ptr(qs).wrapping_add(count) % MSGQ_NUM_PAGES;\n-\n- dma_write!(qs, .cpuq.tx.0.writePtr, wptr);\n-\n- // Ensure all command data is visible before triggering the GSP read.\n- fence(Ordering::SeqCst);\n- }\n-}\n-\n /// Maximum size of a single GSP message queue element in bytes.\n pub(crate) const GSP_MSG_QUEUE_ELEMENT_SIZE_MAX: usize =\n num::u32_as_usize(bindings::GSP_MSG_QUEUE_ELEMENT_SIZE_MAX);\n@@ -706,6 +658,19 @@ pub(crate) fn new(msgq_size: u32, rx_hdr_offset: u32, msg_count: u32) -> Self {\n entryOff: num::usize_into_u32::<GSP_PAGE_SIZE>(),\n })\n }\n+\n+ /// Returns the value of the write pointer for this queue.\n+ pub(crate) fn write_ptr<T: KnownSize + ?Sized>(this: io::View<'_, Coherent<T>, Self>) -> u32 {\n+ io_read!(this, .0.writePtr)\n+ }\n+\n+ /// Sets the value of the write pointer for this queue.\n+ pub(crate) fn set_write_ptr<T: KnownSize + ?Sized>(\n+ this: io::View<'_, Coherent<T>, Self>,\n+ val: u32,\n+ ) {\n+ io_write!(this, .0.writePtr, val)\n+ }\n }\n \n // SAFETY: Padding is explicit and does not contain uninitialized data.\n@@ -721,6 +686,19 @@ impl MsgqRxHeader {\n pub(crate) fn new() -> Self {\n Self(Default::default())\n }\n+\n+ /// Returns the value of the read pointer for this queue.\n+ pub(crate) fn read_ptr<T: KnownSize + ?Sized>(this: io::View<'_, Coherent<T>, Self>) -> u32 {\n+ io_read!(this, .0.readPtr)\n+ }\n+\n+ /// Sets the value of the read pointer for this queue.\n+ pub(crate) fn set_read_ptr<T: KnownSize + ?Sized>(\n+ this: io::View<'_, Coherent<T>, Self>,\n+ val: u32,\n+ ) {\n+ io_write!(this, .0.readPtr, val)\n+ }\n }\n \n // SAFETY: Padding is explicit and does not contain uninitialized data.\n", "prefixes": [ "v2", "09/11" ] }