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GET /api/patches/2225703/?format=api
{ "id": 2225703, "url": "http://patchwork.ozlabs.org/api/patches/2225703/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-emmc-v2-1-0ebd3322b676@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-emmc-v2-1-0ebd3322b676@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-21T13:00:08", "name": "[v2,1/3] clk: qcom: qcs615: Add SDCC1 and SDCC2 clock support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9eee6e7b99fd9ef886a81faa3ee8ce17f1d5dd43", "submitter": { "id": 90810, "url": "http://patchwork.ozlabs.org/api/people/90810/?format=api", "name": "Balaji Selvanathan", "email": "balaji.selvanathan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-emmc-v2-1-0ebd3322b676@oss.qualcomm.com/mbox/", "series": [ { "id": 500798, "url": "http://patchwork.ozlabs.org/api/series/500798/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500798", "date": "2026-04-21T13:00:07", "name": "Enable eMMC and SD card support for QCS615", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500798/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225703/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225703/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=do0VXhA5;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=f5Lx5Y0R;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"do0VXhA5\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"f5Lx5Y0R\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=balaji.selvanathan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0Msj33RXz1yGt\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 23:00:41 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id A3A4384258;\n\tTue, 21 Apr 2026 15:00:31 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 2CB3F83BC8; Tue, 21 Apr 2026 15:00:30 +0200 (CEST)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id E0256841D6\n for <u-boot@lists.denx.de>; Tue, 21 Apr 2026 15:00:27 +0200 (CEST)", "from pps.filterd (m0279862.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63LB4H0t1011843\n for <u-boot@lists.denx.de>; Tue, 21 Apr 2026 13:00:26 GMT", "from mail-pl1-f198.google.com (mail-pl1-f198.google.com\n [209.85.214.198])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dnt9036kd-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Tue, 21 Apr 2026 13:00:25 +0000 (GMT)", "by mail-pl1-f198.google.com with SMTP id\n d9443c01a7336-2b4654f9bb6so44854175ad.2\n for <u-boot@lists.denx.de>; Tue, 21 Apr 2026 06:00:25 -0700 (PDT)", "from hu-bselvana-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260421-emmc-v2-1-0ebd3322b676@oss.qualcomm.com>", "References": "<20260421-emmc-v2-0-0ebd3322b676@oss.qualcomm.com>", "In-Reply-To": "<20260421-emmc-v2-0-0ebd3322b676@oss.qualcomm.com>", "To": "Sumit Garg <sumit.garg@kernel.org>, u-boot-qcom@groups.io,\n u-boot@lists.denx.de", "Cc": "Lukasz Majewski <lukma@denx.de>,\n Casey Connolly <casey.connolly@linaro.org>,\n Neil Armstrong <neil.armstrong@linaro.org>, Tom Rini <trini@konsulko.com>,\n Aswin Murugan <aswin.murugan@oss.qualcomm.com>,\n Stephan Gerhold <stephan.gerhold@linaro.org>,\n Varadarajan Narayanan <quic_varada@quicinc.com>,\n Peng Fan <peng.fan@nxp.com>, Jaehoon Chung <jh80.chung@samsung.com>,\n Loic Poulain <loic.poulain@oss.qualcomm.com>,\n Patrice Chotard <patrice.chotard@foss.st.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Paul Sajna <sajattack@postmarketos.org>,\n Abbarapu Venkatesh Yadav <venkyada@qti.qualcomm.com>,\n Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>,\n Sumit Garg <sumit.garg@oss.qualcomm.com>,\n Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; 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This enables proper clock configuration for both\nstorage interfaces.\n\nReviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>\nReviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>\nSigned-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>\n---\nChanges in v2:\n- No changes\n---\n drivers/clk/qcom/clock-qcom.h | 2 ++\n drivers/clk/qcom/clock-qcs615.c | 46 ++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 47 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h\nindex 3a4550d8536..9899cd28aad 100644\n--- a/drivers/clk/qcom/clock-qcom.h\n+++ b/drivers/clk/qcom/clock-qcom.h\n@@ -14,6 +14,8 @@\n #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)\n #define CFG_CLK_SRC_GPLL2 (2 << 8)\n #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8)\n+#define CFG_CLK_SRC_GPLL6_OUT_MAIN (2 << 8)\n+#define CFG_CLK_SRC_GPLL8 (2 << 8)\n #define CFG_CLK_SRC_GPLL9 (2 << 8)\n #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)\n #define CFG_CLK_SRC_GPLL6 (4 << 8)\ndiff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c\nindex 2087fc38f63..094155e2034 100644\n--- a/drivers/clk/qcom/clock-qcs615.c\n+++ b/drivers/clk/qcom/clock-qcs615.c\n@@ -19,6 +19,34 @@\n #define USB30_PRIM_MASTER_CLK_CMD_RCGR\t\t0xf01c\n #define USB3_PRIM_PHY_AUX_CMD_RCGR\t\t0xf060\n \n+#define SDCC1_APPS_CLK_CMD_RCGR\t\t\t0x12028\n+#define SDCC2_APPS_CLK_CMD_RCGR\t\t\t0x1400c\n+\n+/*\n+ * Frequency tables for SDCC clocks\n+ */\n+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {\n+\tF(144000, CFG_CLK_SRC_CXO, 16, 3, 25),\n+\tF(400000, CFG_CLK_SRC_CXO, 12, 1, 4),\n+\tF(20000000, CFG_CLK_SRC_GPLL0_AUX2, 5, 1, 3),\n+\tF(25000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 1, 2),\n+\tF(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),\n+\tF(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),\n+\tF(192000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 2, 0, 0),\n+\tF(384000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 1, 0, 0),\n+\t{ }\n+};\n+\n+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {\n+\tF(400000, CFG_CLK_SRC_CXO, 12, 1, 4),\n+\tF(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),\n+\tF(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0),\n+\tF(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),\n+\tF(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),\n+\tF(202000000, CFG_CLK_SRC_GPLL8, 2, 0, 0),\n+\t{ }\n+};\n+\n #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)\n #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)\n #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)\n@@ -36,6 +64,7 @@\n static ulong qcs615_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct freq_tbl *freq;\n \n \tif (clk->id < priv->data->num_clks)\n \t\tdebug(\"%s: %s, requested rate=%ld\\n\", __func__,\n@@ -52,6 +81,16 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)\n \t\t\t\t 5, 0, 0, CFG_CLK_SRC_GPLL0, 8);\n \t\tclk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);\n \t\treturn rate;\n+\tcase GCC_SDCC1_APPS_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_SDCC2_APPS_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n \tdefault:\n \t\treturn 0;\n \t}\n@@ -81,7 +120,12 @@ static const struct gate_clk qcs615_clks[] = {\n \tGATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),\n \tGATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),\n \tGATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),\n-\tGATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0))\n+\tGATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),\n+\tGATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)),\n+\tGATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)),\n+\tGATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)),\n+\tGATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),\n+\tGATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0))\n };\n \n static int qcs615_enable(struct clk *clk)\n", "prefixes": [ "v2", "1/3" ] }