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GET /api/patches/2225687/?format=api
{ "id": 2225687, "url": "http://patchwork.ozlabs.org/api/patches/2225687/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-10-0e2b490542b1@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-imx8mq-dm-pmic-v1-10-0e2b490542b1@nxp.com>", "list_archive_url": null, "date": "2026-04-21T13:41:22", "name": "[10/15] imx8mq: evk: Migrate to DM PMIC framework", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "0e10a6f0fcbcf4769a67a340bdb3635265f22f0f", "submitter": { "id": 80723, "url": "http://patchwork.ozlabs.org/api/people/80723/?format=api", "name": "Peng Fan", "email": "peng.fan@oss.nxp.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-10-0e2b490542b1@nxp.com/mbox/", "series": [ { "id": 500790, "url": "http://patchwork.ozlabs.org/api/series/500790/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500790", "date": "2026-04-21T13:41:12", "name": "i.MX8MQ: Convert to DM_PMIC for a few boards", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500790/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225687/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225687/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=rWFg6dlw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com;\n dkim=pass header.d=oss.nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com;\n s=selector1-NXP1-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=ZH7f9yhWeZFm3YZvZr7DWSiwy9O4/el39TnZGM/o3xo=;\n b=rWFg6dlwEwIYxcalh8bxAStkd6MQP0XqHTfb7lsAG0evHYQehcHdp0u/N5xBcd+kwu46Fz/8pxu41BiHozTb9KWjn/YNkmQwts2linWkSnLF/FI8SafmRSP05L59Ef2xRRS7xqacBGFPoVrQm0Z/2L42HvQ9u08AN9ri71DT/z9oTeS5/2uZHDEIWMY0ERwiFS1D16Zy+wzQx38+jc9AaC5kjGSDmk/M0X6OcSjpjUkhawb0qtcUlrzt80bZ1Ui8Rize4Rr7g7RqwBvosqsULKWCyjbKHYjn6WF+g+x7tvff+DgdJQYl8zrwViWcvGT8lD2ufbz4JmQiP+BEkGChPA==", "From": "\"Peng Fan (OSS)\" <peng.fan@oss.nxp.com>", "Date": "Tue, 21 Apr 2026 21:41:22 +0800", "Subject": "[PATCH 10/15] imx8mq: evk: Migrate to DM PMIC framework", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260421-imx8mq-dm-pmic-v1-10-0e2b490542b1@nxp.com>", "References": "<20260421-imx8mq-dm-pmic-v1-0-0e2b490542b1@nxp.com>", "In-Reply-To": "<20260421-imx8mq-dm-pmic-v1-0-0e2b490542b1@nxp.com>", "To": "\"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>, u-boot@lists.denx.de,\n kernel@puri.sm", "Cc": "Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Tom Rini <trini@konsulko.com>, Yannic Moog <y.moog@phytec.de>,\n Ye Li <ye.li@nxp.com>, Ilias Apalodimas <ilias.apalodimas@linaro.org>,\n Alice Guo <alice.guo@nxp.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Marco Franchi <marcofrk@gmail.com>, Alifer Moraes <alifer.wsdm@gmail.com>,\n \"Lukas F. Hartmann\" <lukas@mntre.com>, Patrick Wildt <patrick@blueri.se>,\n Marek Vasut <marex@denx.de>, Heiko Thiery <heiko.thiery@gmail.com>,\n Ilko Iliev <iliev@ronetix.at>, Angus Ainslie <angus@akkea.ca>,\n Peng Fan <peng.fan@nxp.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "MAXP287CA0011.INDP287.PROD.OUTLOOK.COM\n (2603:1096:a00:49::24) To PAXPR04MB8459.eurprd04.prod.outlook.com\n (2603:10a6:102:1da::15)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PAXPR04MB8459:EE_|PAXPR04MB9349:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ee616c7f-133b-4182-2d33-08de9fa12412", "X-MS-Exchange-SharedMailbox-RoutingAgent-Processed": "True", "X-LD-Processed": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n 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"X-OriginatorOrg": "oss.nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ee616c7f-133b-4182-2d33-08de9fa12412", "X-MS-Exchange-CrossTenant-AuthSource": "PAXPR04MB8459.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Apr 2026 12:25:57.8909 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n v2fegZS07sd9h50smqWtSEekrWrACiSmXp2pmZbelUTBvTWKQkXmVBzQ83ZLSmkztvqQtxWrdkdYX3oTM8EZoA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PAXPR04MB9349", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Peng Fan <peng.fan@nxp.com>\n\nMigrate the i.MX8MQ EVK board to the Driver Model (DM) PMIC framework.\nThis replaces legacy PMIC handling with DM_PMIC and enables proper\ndevice-model support during SPL.\n\nAs part of this transition, enable CONFIG_SPL_DM and the required\nDM subsystems such as I2C, PINCTRL, MMC, GPIO, and regulators so the\nSPL boot flow continues to work correctly.\n\nBoard-specific SPL code is simplified accordingly by removing legacy\nI2C, USDHC, and PMIC handling, relying instead on device tree\ndescriptions and DM drivers.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n arch/arm/dts/imx8mq-evk-u-boot.dtsi | 88 ++++++++++++++++-\n board/nxp/imx8mq_evk/spl.c | 185 +++++++-----------------------------\n configs/imx8mq_evk_defconfig | 21 ++--\n 3 files changed, 129 insertions(+), 165 deletions(-)", "diff": "diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi\nindex d987f68b6ba..ca80dc994b1 100644\n--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi\n+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi\n@@ -2,19 +2,105 @@\n \n #include \"imx8mq-u-boot.dtsi\"\n \n+&aips1 {\n+\tbootph-all;\n+};\n+\n+&gpio2 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_i2c1 {\n+\tbootph-all;\n+};\n+\n+&i2c1 {\n+\tbootph-all;\n+};\n+\n+&soc {\n+\tbootph-all;\n+\tbootph-pre-ram;\n+};\n+\n+&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {\n+\tbootph-all;\n+};\n+\n+&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {\n+\tbootph-all;\n+};\n+\n &pinctrl_uart1 {\n \tbootph-pre-ram;\n };\n \n+&uart1 {\n+\tbootph-pre-ram;\n+};\n+\n &usdhc1 {\n+\tbootph-pre-ram;\n \tmmc-hs400-1_8v;\n+\t/delete-property/ vqmmc-supply;\n+};\n+\n+&pinctrl_usdhc1 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc1_100mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc1_200mhz {\n+\tbootph-pre-ram;\n };\n \n &usdhc2 {\n+\tbootph-pre-ram;\n \tsd-uhs-sdr104;\n \tsd-uhs-ddr50;\n };\n \n-&uart1 {\n+&pinctrl_usdhc2 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2_100mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2_200mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2_gpio {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_reg_usdhc2 {\n+\tbootph-pre-ram;\n+};\n+\n+®_usdhc2_vmmc {\n+\tbootph-pre-ram;\n+};\n+\n+#ifdef CONFIG_FSL_CAAM\n+&crypto {\n+\tbootph-pre-ram;\n+};\n+\n+&sec_jr0 {\n+\tbootph-pre-ram;\n+};\n+\n+&sec_jr1 {\n+\tbootph-pre-ram;\n+};\n+\n+&sec_jr2 {\n \tbootph-pre-ram;\n };\n+#endif\ndiff --git a/board/nxp/imx8mq_evk/spl.c b/board/nxp/imx8mq_evk/spl.c\nindex 6686fe34126..80322a2ed19 100644\n--- a/board/nxp/imx8mq_evk/spl.c\n+++ b/board/nxp/imx8mq_evk/spl.c\n@@ -9,23 +9,16 @@\n #include <image.h>\n #include <init.h>\n #include <log.h>\n-#include <asm/io.h>\n #include <errno.h>\n #include <asm/io.h>\n #include <asm/arch/ddr.h>\n-#include <asm/arch/imx8mq_pins.h>\n #include <asm/arch/sys_proto.h>\n #include <asm/arch/clock.h>\n-#include <asm/mach-imx/iomux-v3.h>\n-#include <asm/mach-imx/gpio.h>\n-#include <asm/mach-imx/mxc_i2c.h>\n #include <asm/sections.h>\n-#include <fsl_esdhc_imx.h>\n-#include <fsl_sec.h>\n-#include <mmc.h>\n-#include <linux/delay.h>\n #include <power/pmic.h>\n #include <power/pfuze100_pmic.h>\n+#include <dm/uclass.h>\n+#include <dm/device.h>\n #include <spl.h>\n #include \"../common/pfuze.h\"\n \n@@ -40,166 +33,52 @@ static void spl_dram_init(void)\n \t\tddr_init(&dram_timing_b0);\n }\n \n-#define I2C_PAD_CTRL\t(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)\n-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)\n-static struct i2c_pads_info i2c_pad_info1 = {\n-\t.scl = {\n-\t\t.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,\n-\t\t.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,\n-\t\t.gp = IMX_GPIO_NR(5, 14),\n-\t},\n-\t.sda = {\n-\t\t.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,\n-\t\t.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,\n-\t\t.gp = IMX_GPIO_NR(5, 15),\n-\t},\n-};\n-\n-#define USDHC2_CD_GPIO\tIMX_GPIO_NR(2, 12)\n-#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)\n-#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)\n-\n-int board_mmc_getcd(struct mmc *mmc)\n-{\n-\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n-\tint ret = 0;\n-\n-\tswitch (cfg->esdhc_base) {\n-\tcase USDHC1_BASE_ADDR:\n-\t\tret = 1;\n-\t\tbreak;\n-\tcase USDHC2_BASE_ADDR:\n-\t\tret = !gpio_get_value(USDHC2_CD_GPIO);\n-\t\treturn ret;\n-\t}\n-\n-\treturn 1;\n-}\n-\n-#define USDHC_PAD_CTRL\t(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \\\n-\t\t\t PAD_CTL_FSEL2)\n-#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)\n-\n-static iomux_v3_cfg_t const usdhc1_pads[] = {\n-\tIMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),\n-};\n-\n-static iomux_v3_cfg_t const usdhc2_pads[] = {\n-\tIMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */\n-\tIMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),\n-\tIMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),\n-};\n-\n-static struct fsl_esdhc_cfg usdhc_cfg[2] = {\n-\t{USDHC1_BASE_ADDR, 0, 8},\n-\t{USDHC2_BASE_ADDR, 0, 4},\n-};\n-\n-int board_mmc_init(struct bd_info *bis)\n-{\n-\tint i, ret;\n-\t/*\n-\t * According to the board_mmc_init() the following map is done:\n-\t * (U-Boot device node) (Physical Port)\n-\t * mmc0 USDHC1\n-\t * mmc1 USDHC2\n-\t */\n-\tfor (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {\n-\t\tswitch (i) {\n-\t\tcase 0:\n-\t\t\tinit_clk_usdhc(0);\n-\t\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);\n-\t\t\timx_iomux_v3_setup_multiple_pads(usdhc1_pads,\n-\t\t\t\t\t\t\t ARRAY_SIZE(usdhc1_pads));\n-\t\t\tgpio_request(USDHC1_PWR_GPIO, \"usdhc1_reset\");\n-\t\t\tgpio_direction_output(USDHC1_PWR_GPIO, 0);\n-\t\t\tudelay(500);\n-\t\t\tgpio_direction_output(USDHC1_PWR_GPIO, 1);\n-\t\t\tbreak;\n-\t\tcase 1:\n-\t\t\tinit_clk_usdhc(1);\n-\t\t\tusdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);\n-\t\t\timx_iomux_v3_setup_multiple_pads(usdhc2_pads,\n-\t\t\t\t\t\t\t ARRAY_SIZE(usdhc2_pads));\n-\t\t\tgpio_request(USDHC2_PWR_GPIO, \"usdhc2_reset\");\n-\t\t\tgpio_direction_output(USDHC2_PWR_GPIO, 0);\n-\t\t\tudelay(500);\n-\t\t\tgpio_direction_output(USDHC2_PWR_GPIO, 1);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Warning: you configured more USDHC controllers(%d) than supported by the board\\n\", i + 1);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-#if CONFIG_IS_ENABLED(POWER_LEGACY)\n-#define I2C_PMIC\t0\n int power_init_board(void)\n {\n-\tstruct pmic *p;\n+\tstruct udevice *dev;\n+\tint reg;\n \tint ret;\n-\tunsigned int reg;\n \n-\tret = power_pfuze100_init(I2C_PMIC);\n-\tif (ret)\n-\t\treturn -ENODEV;\n-\n-\tp = pmic_get(\"PFUZE100\");\n-\tret = pmic_probe(p);\n-\tif (ret)\n-\t\treturn -ENODEV;\n+\tret = pmic_get(\"pmic@8\", &dev);\n+\tif (ret == -ENODEV) {\n+\t\tputs(\"No pmic@8\\n\");\n+\t\treturn 0;\n+\t}\n+\tif (ret < 0)\n+\t\treturn ret;\n \n-\tpmic_reg_read(p, PFUZE100_DEVICEID, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_DEVICEID);\n \tprintf(\"PMIC: PFUZE100 ID=0x%02x\\n\", reg);\n \n-\tpmic_reg_read(p, PFUZE100_SW3AVOL, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW3AVOL);\n \tif ((reg & 0x3f) != 0x18) {\n \t\treg &= ~0x3f;\n \t\treg |= 0x18;\n-\t\tpmic_reg_write(p, PFUZE100_SW3AVOL, reg);\n+\t\tpmic_reg_write(dev, PFUZE100_SW3AVOL, reg);\n \t}\n \n-\tret = pfuze_mode_init(p, APS_PFM);\n+\tret = pfuze_mode_init(dev, APS_PFM);\n \tif (ret < 0)\n \t\treturn ret;\n \n \t/* set SW3A standby mode to off */\n-\tpmic_reg_read(p, PFUZE100_SW3AMODE, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW3AMODE);\n \treg &= ~0xf;\n \treg |= APS_OFF;\n-\tpmic_reg_write(p, PFUZE100_SW3AMODE, reg);\n+\tpmic_reg_write(dev, PFUZE100_SW3AMODE, reg);\n \n \treturn 0;\n }\n-#endif\n \n void spl_board_init(void)\n {\n \tif (IS_ENABLED(CONFIG_FSL_CAAM)) {\n-\t\tif (sec_init())\n-\t\t\tprintf(\"\\nsec_init failed!\\n\");\n+\t\tstruct udevice *dev;\n+\t\tint ret;\n+\n+\t\tret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);\n+\t\tif (ret)\n+\t\t\tprintf(\"Failed to initialize caam_jr: %d\\n\", ret);\n \t}\n \tputs(\"Normal Boot\\n\");\n }\n@@ -218,6 +97,9 @@ void board_init_f(ulong dummy)\n {\n \tint ret;\n \n+\t/* Clear the BSS. */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\n \tarch_cpu_init();\n \n \tinit_uart_clk(0);\n@@ -226,25 +108,22 @@ void board_init_f(ulong dummy)\n \n \ttimer_init();\n \n-\tpreloader_console_init();\n-\n-\t/* Clear the BSS. */\n-\tmemset(__bss_start, 0, __bss_end - __bss_start);\n-\n-\tret = spl_init();\n+\tret = spl_early_init();\n \tif (ret) {\n-\t\tdebug(\"spl_init() failed: %d\\n\", ret);\n+\t\tdebug(\"spl_early_init() failed: %d\\n\", ret);\n \t\thang();\n \t}\n+\tpreloader_console_init();\n \n \tenable_tzc380();\n \n-\tsetup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);\n-\n \tpower_init_board();\n \n \t/* DDR initialization */\n \tspl_dram_init();\n \n+\tinit_clk_usdhc(0);\n+\tinit_clk_usdhc(1);\n+\n \tboard_init_r(NULL, 0);\n }\ndiff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig\nindex 3dd6554733d..a03b241a72f 100644\n--- a/configs/imx8mq_evk_defconfig\n+++ b/configs/imx8mq_evk_defconfig\n@@ -4,12 +4,8 @@ CONFIG_TEXT_BASE=0x40200000\n CONFIG_SYS_MALLOC_LEN=0x600000\n CONFIG_SPL_GPIO=y\n CONFIG_SPL_LIBCOMMON_SUPPORT=y\n-CONFIG_SPL_LIBGENERIC_SUPPORT=y\n CONFIG_ENV_SIZE=0x4000\n CONFIG_ENV_OFFSET=0x200000\n-CONFIG_SYS_I2C_MXC_I2C1=y\n-CONFIG_SYS_I2C_MXC_I2C2=y\n-CONFIG_SYS_I2C_MXC_I2C3=y\n CONFIG_DM_GPIO=y\n CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mq-evk\"\n CONFIG_TARGET_IMX8MQ_EVK=y\n@@ -18,7 +14,7 @@ CONFIG_SYS_MONITOR_LEN=524288\n CONFIG_SPL_MMC=y\n CONFIG_SPL_SERIAL=y\n CONFIG_SPL_DRIVERS_MISC=y\n-CONFIG_SPL_STACK=0x187ff0\n+CONFIG_SPL_STACK=0x920000\n CONFIG_SPL_TEXT_BASE=0x7E1000\n CONFIG_SPL_HAS_BSS_LINKER_SECTION=y\n CONFIG_SPL_BSS_START_ADDR=0x180000\n@@ -73,6 +69,7 @@ CONFIG_CMD_EFIDEBUG=y\n CONFIG_CMD_REGULATOR=y\n CONFIG_CMD_EXT4_WRITE=y\n CONFIG_OF_CONTROL=y\n+CONFIG_SPL_OF_CONTROL=y\n CONFIG_ENV_OVERWRITE=y\n CONFIG_ENV_IS_IN_MMC=y\n CONFIG_ENV_REDUNDANT=y\n@@ -80,31 +77,33 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y\n CONFIG_ENV_MMC_DEVICE_INDEX=1\n CONFIG_USE_ETHPRIME=y\n CONFIG_ETHPRIME=\"FEC\"\n+CONFIG_SPL_DM=y\n CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000\n CONFIG_DFU_MMC=y\n CONFIG_MXC_GPIO=y\n CONFIG_DM_I2C=y\n-CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_SUPPORT_EMMC_RPMB=y\n CONFIG_SUPPORT_EMMC_BOOT=y\n CONFIG_FSL_USDHC=y\n-CONFIG_PHYLIB=y\n-CONFIG_PHY_ATHEROS=y\n CONFIG_PHY_GIGE=y\n CONFIG_FEC_MXC=y\n CONFIG_MII=y\n+CONFIG_PHYLIB=y\n+CONFIG_PHY_ATHEROS=y\n CONFIG_PHY=y\n CONFIG_PHY_IMX8MQ_USB=y\n CONFIG_PINCTRL=y\n+CONFIG_SPL_PINCTRL=y\n CONFIG_PINCTRL_IMX8M=y\n-CONFIG_SPL_POWER_LEGACY=y\n CONFIG_POWER_DOMAIN=y\n CONFIG_IMX8M_POWER_DOMAIN=y\n-CONFIG_POWER_PFUZE100=y\n+CONFIG_DM_PMIC=y\n+CONFIG_DM_PMIC_PFUZE100=n\n+CONFIG_SPL_DM_PMIC_PFUZE100=y\n CONFIG_DM_REGULATOR=y\n CONFIG_DM_REGULATOR_FIXED=y\n CONFIG_DM_REGULATOR_GPIO=y\n-CONFIG_SPL_POWER_I2C=y\n+CONFIG_SPL_DM_REGULATOR_GPIO=y\n CONFIG_DM_SERIAL=y\n CONFIG_MXC_UART=y\n CONFIG_TEE=y\n", "prefixes": [ "10/15" ] }