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GET /api/patches/2225621/?format=api
{ "id": 2225621, "url": "http://patchwork.ozlabs.org/api/patches/2225621/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421093715.2995067-6-frank.chang@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421093715.2995067-6-frank.chang@sifive.com>", "list_archive_url": null, "date": "2026-04-21T09:37:14", "name": "[v4,5/6] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a429ec511b104d93a4ce5ae13a76989f5a2dd82a", "submitter": { "id": 79604, "url": "http://patchwork.ozlabs.org/api/people/79604/?format=api", "name": "Frank Chang", "email": "frank.chang@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421093715.2995067-6-frank.chang@sifive.com/mbox/", "series": [ { "id": 500769, "url": "http://patchwork.ozlabs.org/api/series/500769/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500769", "date": "2026-04-21T09:37:09", "name": "Fix Zjpm implementation", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500769/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225621/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225621/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=enyY/qiK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x52a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Frank Chang <frank.chang@sifive.com>\n\nRename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() to better\nreflect its actual usage. This function is used when checking the PMM\nfield for virtual-machine load/store instructions (HLV.* and HSV.*),\nrather than for VS/VU modes.\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\nReviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\n---\n target/riscv/cpu.h | 2 +-\n target/riscv/cpu_helper.c | 2 +-\n target/riscv/internals.h | 2 +-\n 3 files changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 672f0dab0fb..138183e017c 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -890,7 +890,7 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu);\n \n bool riscv_cpu_virt_mem_enabled(CPURISCVState *env);\n RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);\n-RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env);\n+RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env);\n uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);\n \n RISCVException riscv_csrr(CPURISCVState *env, int csrno,\ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex 2b3fea81d50..ef1ff7cb0bd 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -214,7 +214,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n #endif\n }\n \n-RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env)\n+RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env)\n {\n #ifndef CONFIG_USER_ONLY\n int priv_mode;\ndiff --git a/target/riscv/internals.h b/target/riscv/internals.h\nindex 43b77d30f27..82d24f433dc 100644\n--- a/target/riscv/internals.h\n+++ b/target/riscv/internals.h\n@@ -203,7 +203,7 @@ static inline target_ulong adjust_addr_body(CPURISCVState *env,\n \n /* get pmm field depending on whether addr is */\n if (is_virt_addr) {\n- pmm = riscv_pm_get_virt_pmm(env);\n+ pmm = riscv_pm_get_vm_ldst_pmm(env);\n } else {\n pmm = riscv_pm_get_pmm(env);\n }\n", "prefixes": [ "v4", "5/6" ] }