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GET /api/patches/2225511/?format=api
{ "id": 2225511, "url": "http://patchwork.ozlabs.org/api/patches/2225511/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/84947901-9891-4d0f-be75-47bf0213b683@linux.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<84947901-9891-4d0f-be75-47bf0213b683@linux.ibm.com>", "list_archive_url": null, "date": "2026-04-21T06:04:12", "name": "rs6000: Add Future Vector Integer Arithmetic Instructions [RFC02680]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "515b33fc71971e82089dd67ab83dc134f0f2fb89", "submitter": { "id": 88218, "url": "http://patchwork.ozlabs.org/api/people/88218/?format=api", "name": "jeevitha", "email": "jeevitha@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/84947901-9891-4d0f-be75-47bf0213b683@linux.ibm.com/mbox/", "series": [ { "id": 500736, "url": "http://patchwork.ozlabs.org/api/series/500736/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500736", "date": "2026-04-21T06:04:12", "name": "rs6000: Add Future Vector Integer Arithmetic Instructions [RFC02680]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500736/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225511/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225511/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=FKDxGsOT;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=UTF-8", "Content-Transfer-Encoding": "7bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-ORIG-GUID": "bwKZz8SPnUu64Yl-5YySdDnPEGFbmMwz", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIxMDA1NCBTYWx0ZWRfX40d3f+7dt3Ru\n t0fg66eo8VyLO81UgwE3tFhC39CTtxpnaTcn8LUcWKG8lGZAgMicvgjdtKtYpM8VbvowosgMS2s\n qSs+ImRf0YFuQSlRC470TQ6wg6L66h5Orponvl9B5pOoE7wJJPVaHQg2OBy62Rde57Iaeq5O8+j\n IQyuonLC7nvIrdeWWpGfazgi6AatXSiLxVtc8SSE6iSoBI0AH5sgxbq7BK6y2uGoMHiUT+SYTL0\n vU+ZPEuPri8lSPrQ8LtjEKHDA+ph9R4Ot/FWbH0FdprvMzVSM+66LetVAo9Zqz1Bfm0bxhMXPRF\n ZpqBYn1R/rJQU7EOwnkA/XhgqbMGp5bKIqjY0Cof8GOxtpSc8Q3IitM2DvKSkUAuahHxBpbCacq\n QPWV9sLIGe0ldUdTdG+s7uLDCEstbaEKPpRW1lyHDBflmGEHl4xQMb1eK5R3tasiYowSy/zbDeX\n sSMUBSxu7FQTewiLokw==", "X-Authority-Analysis": "v=2.4 cv=PtujqQM3 c=1 sm=1 tr=0 ts=69e71362 cx=c_pps\n a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8\n a=eaHpQ2aFeMPArbCVpk4A:9 a=QEXdDO2ut3YA:10", "X-Proofpoint-GUID": "bwKZz8SPnUu64Yl-5YySdDnPEGFbmMwz", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-21_01,2026-04-20_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 suspectscore=0 clxscore=1015 spamscore=0 impostorscore=0\n priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210054", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch depends on the -mcpu=future infrastructure and the\nsmul/umul pattern fix patches. This will be upstreamed after those\npatches are upstreamed. These changes have been bootstrapped and\nregression tested on powerpc64le-linux.\n\nThis patch adds support for VSX vector arithmetic instructions that may\nbe added to future PowerPC processors. Note that the names of these\nbuiltins may change in the future.\n\nAdd new VSX patterns for vector add, subtract, multiply, and\nmultiply-high instructions guarded by TARGET_FUTURE. Rename existing\nAltivec patterns to altivec_* to avoid name conflicts and introduce\ncorresponding VSX patterns.\n\n2026-04-21 Jeevitha Palanisamy <jeevitha@linux.ibm.com>\n\ngcc/\n\t* config/rs6000/altivec.md (vsx_add<mode>3): New pattern for\n\tVSX vector add for halfword and word.\n\t(altivec_add<mode>3): Renamed from add<mode>3.\n\t(vsx_sub<mode>3): New pattern for VSX vector subtract for\n\thalfword and word.\n\t(altivec_sub<mode>3): Renamed from sub<mode>3.\n\t* config/rs6000/vector.md (VIlong1): New mode iterator for\n\tV4SI and V2DI.\n\t(VI_1): New mode iterator for V8HI and V4SI.\n\t(add<mode>3): New expand pattern for integer vector add.\n\t(sub<mode>3): New expand pattern for integer vector subtract.\n\t(smul<mode>3_highpart): New expand pattern for signed vector\n\tmultiply-high part on VIlong1 modes.\n\t(umul<mode>3_highpart): New expand pattern for unsigned vector\n\tmultiply-high part on VIlong1 modes.\n\t* config/rs6000/vsx.md (vsx_mul<mode>3): New VSX vector multiply\n\tpattern for halfword and word.\n\t(vsx_smul<mode>3_highpart): New VSX signed multiply-high\n\tpattern for halfword and word.\n\t(vsx_umul<mode>3_highpart): New VSX unsigned multiply-high\n\tpattern for halfword and word.\n\t(altivec_smul<mode>3_highpart): Renamed from smul<mode>3_highpart.\n\t(altivec_umul<mode>3_highpart): Renamed from umul<mode>3_highpart.\n\t* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvmulhuh):\n\tNew builtin for VSX unsigned multiply-high halfword.\n\t(__builtin_vsx_xvmulhsh): New builtin for VSX signed multiply-high\n\thalfword.\n\t* config/rs6000/rs6000-overload.def (__builtin_vec_mulh): Add\n\toverloads for vector multiply-high signed/unsigned halfword.\n\t* doc/extend.texi (PowerPC AltiVec Built-in Functions that may be\n\tavailable on future PowerPCs): Document new functions.\n\ngcc/testsuite/\n\t* gcc.target/powerpc/vsx_simd-1.c: New test.\n\t* gcc.target/powerpc/vsx_simd-2.c: New test.", "diff": "diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md\nindex 129f56245cd..dcae4547f84 100644\n--- a/gcc/config/rs6000/altivec.md\n+++ b/gcc/config/rs6000/altivec.md\n@@ -503,8 +503,15 @@\n \n ;; Simple binary operations.\n \n+(define_insn \"vsx_add<mode>3\"\n+ [(set (match_operand:VI_1 0 \"vsx_register_operand\" \"=wa\")\n+ (plus:VI_1 (match_operand:VI_1 1 \"vsx_register_operand\" \"wa\")\n+ (match_operand:VI_1 2 \"vsx_register_operand\" \"wa\")))]\n+ \"TARGET_FUTURE\"\n+ \"xvaddu<VI_char>m %x0,%x1,%x2\")\n+\n ;; add\n-(define_insn \"add<mode>3\"\n+(define_insn \"altivec_add<mode>3\"\n [(set (match_operand:VI2 0 \"register_operand\" \"=v\")\n (plus:VI2 (match_operand:VI2 1 \"register_operand\" \"v\")\n \t\t (match_operand:VI2 2 \"register_operand\" \"v\")))]\n@@ -547,8 +554,15 @@\n \"vadds<VI_char>s %0,%1,%2\"\n [(set_attr \"type\" \"vecsimple\")])\n \n+(define_insn \"vsx_sub<mode>3\"\n+ [(set (match_operand:VI_1 0 \"vsx_register_operand\" \"=wa\")\n+ (minus:VI_1 (match_operand:VI_1 1 \"vsx_register_operand\" \"wa\")\n+ (match_operand:VI_1 2 \"vsx_register_operand\" \"wa\")))]\n+ \"TARGET_FUTURE\"\n+ \"xvsubu<VI_char>m %x0,%x1,%x2\")\n+\n ;; sub\n-(define_insn \"sub<mode>3\"\n+(define_insn \"altivec_sub<mode>3\"\n [(set (match_operand:VI2 0 \"register_operand\" \"=v\")\n (minus:VI2 (match_operand:VI2 1 \"register_operand\" \"v\")\n \t\t (match_operand:VI2 2 \"register_operand\" \"v\")))]\ndiff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def\nindex 7e5a4fb96e7..3bcf310eac8 100644\n--- a/gcc/config/rs6000/rs6000-builtins.def\n+++ b/gcc/config/rs6000/rs6000-builtins.def\n@@ -3924,3 +3924,10 @@\n \n void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);\n STXVP nothing {mma,pair}\n+\n+[future]\n+ const vus __builtin_vsx_xvmulhuh (vus, vus);\n+ XVMULHUH vsx_umulv8hi3_highpart {}\n+\n+ const vss __builtin_vsx_xvmulhsh (vss, vss);\n+ XVMULHSH vsx_smulv8hi3_highpart {}\ndiff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def\nindex 5238c81b214..3690a6dce7b 100644\n--- a/gcc/config/rs6000/rs6000-overload.def\n+++ b/gcc/config/rs6000/rs6000-overload.def\n@@ -2530,6 +2530,10 @@\n VMULEUD\n \n [VEC_MULH, vec_mulh, __builtin_vec_mulh]\n+ vss __builtin_vec_mulh (vss, vss);\n+ XVMULHSH\n+ vus __builtin_vec_mulh (vus, vus);\n+ XVMULHUH\n vsi __builtin_vec_mulh (vsi, vsi);\n VMULHSW\n vui __builtin_vec_mulh (vui, vui);\ndiff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md\nindex e6adf91002e..44cf811d0d3 100644\n--- a/gcc/config/rs6000/vector.md\n+++ b/gcc/config/rs6000/vector.md\n@@ -71,6 +71,10 @@\n ;; Vector integer modes\n (define_mode_iterator VI [V4SI V8HI V16QI])\n \n+(define_mode_iterator VIlong1 [V4SI V2DI])\n+\n+(define_mode_iterator VI_1 [V8HI V4SI])\n+\n ;; Base type from vector mode\n (define_mode_attr VEC_base [(V16QI \"QI\")\n \t\t\t (V8HI \"HI\")\n@@ -188,6 +192,13 @@\n \"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)\"\n \"\")\n \n+(define_expand \"add<mode>3\"\n+ [(set (match_operand:VEC_I 0 \"register_operand\")\n+ (plus:VEC_I (match_operand:VEC_I 1 \"register_operand\")\n+ (match_operand:VEC_I 2 \"register_operand\")))]\n+ \"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)\"\n+ \"\")\n+\n (define_expand \"sub<mode>3\"\n [(set (match_operand:VEC_F 0 \"vfloat_operand\")\n \t(minus:VEC_F (match_operand:VEC_F 1 \"vfloat_operand\")\n@@ -195,6 +206,13 @@\n \"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)\"\n \"\")\n \n+(define_expand \"sub<mode>3\"\n+ [(set (match_operand:VEC_I 0 \"register_operand\")\n+ (minus:VEC_I (match_operand:VEC_I 1 \"register_operand\")\n+ (match_operand:VEC_I 2 \"register_operand\")))]\n+ \"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)\"\n+ \"\")\n+\n (define_expand \"mul<mode>3\"\n [(set (match_operand:VEC_F 0 \"vfloat_operand\")\n \t(mult:VEC_F (match_operand:VEC_F 1 \"vfloat_operand\")\n@@ -208,6 +226,22 @@\n }\n })\n \n+(define_expand \"smul<mode>3_highpart\"\n+ [(set (match_operand:VIlong1 0 \"register_operand\")\n+ (unspec:VIlong1 [(match_operand:VIlong1 1 \"register_operand\")\n+ (match_operand:VIlong1 2 \"register_operand\")]\n+ UNSPEC_VMULHS))]\n+ \"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && TARGET_POWER10\"\n+ \"\")\n+\n+(define_expand \"umul<mode>3_highpart\"\n+ [(set (match_operand:VIlong1 0 \"register_operand\")\n+ (unspec:VIlong1 [(match_operand:VIlong1 1 \"register_operand\")\n+ (match_operand:VIlong1 2 \"register_operand\")]\n+ UNSPEC_VMULHU))]\n+ \"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && TARGET_POWER10\"\n+ \"\")\n+\n (define_expand \"div<mode>3\"\n [(set (match_operand:VEC_F 0 \"vfloat_operand\")\n \t(div:VEC_F (match_operand:VEC_F 1 \"vfloat_operand\")\ndiff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex f4979e447de..ae3c88a2b6e 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -1711,6 +1711,13 @@\n \"xvsub<sd>p %x0,%x1,%x2\"\n [(set_attr \"type\" \"<VStype_simple>\")])\n \n+(define_insn \"vsx_mul<mode>3\"\n+ [(set (match_operand:VI_1 0 \"vsx_register_operand\" \"=wa\")\n+ (mult:VI_1 (match_operand:VI_1 1 \"vsx_register_operand\" \"wa\")\n+ (match_operand:VI_1 2 \"vsx_register_operand\" \"wa\")))]\n+ \"TARGET_FUTURE\"\n+ \"xvmulu<wd>m %x0,%x1,%x2\")\n+\n (define_insn \"*vsx_mul<mode>3\"\n [(set (match_operand:VSX_F 0 \"vsx_register_operand\" \"=wa\")\n (mult:VSX_F (match_operand:VSX_F 1 \"vsx_register_operand\" \"wa\")\n@@ -6546,7 +6553,23 @@\n [(set_attr \"type\" \"vecdiv\")\n (set_attr \"size\" \"<bits>\")])\n \n-(define_insn \"smul<mode>3_highpart\"\n+(define_insn \"vsx_smul<mode>3_highpart\"\n+ [(set (match_operand:VI_1 0 \"vsx_register_operand\" \"=wa\")\n+ (unspec:VI_1 [(match_operand:VI_1 1 \"vsx_register_operand\" \"wa\")\n+ (match_operand:VI_1 2 \"vsx_register_operand\" \"wa\")]\n+ UNSPEC_VMULHS))]\n+ \"TARGET_FUTURE\"\n+ \"xvmulhs<wd> %x0,%x1,%x2\")\n+\n+(define_insn \"vsx_umul<mode>3_highpart\"\n+ [(set (match_operand:VI_1 0 \"vsx_register_operand\" \"=wa\")\n+ (unspec:VI_1 [(match_operand:VI_1 1 \"vsx_register_operand\" \"wa\")\n+ (match_operand:VI_1 2 \"vsx_register_operand\" \"wa\")]\n+ UNSPEC_VMULHU))]\n+ \"TARGET_FUTURE\"\n+ \"xvmulhu<wd> %x0,%x1,%x2\")\n+\n+(define_insn \"altivec_smul<mode>3_highpart\"\n [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n (unspec:VIlong [(match_operand:VIlong 1 \"altivec_register_operand\" \"v\")\n (match_operand:VIlong 2 \"altivec_register_operand\" \"v\")]\n@@ -6555,7 +6578,7 @@\n \"vmulhs<wd> %0,%1,%2\"\n [(set_attr \"type\" \"veccomplex\")])\n \n-(define_insn \"umul<mode>3_highpart\"\n+(define_insn \"altivec_umul<mode>3_highpart\"\n [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n (unspec:VIlong [(match_operand:VIlong 1 \"altivec_register_operand\" \"v\")\n (match_operand:VIlong 2 \"altivec_register_operand\" \"v\")]\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex a22ef39226a..f8225fa2a24 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -24608,6 +24608,7 @@ The PVIPR documents the following overloaded functions:\n * PowerPC AltiVec Built-in Functions Available on ISA 2.07::\n * PowerPC AltiVec Built-in Functions Available on ISA 3.0::\n * PowerPC AltiVec Built-in Functions Available on ISA 3.1::\n+* PowerPC AltiVec Built-in Functions that may be available on future PowerPCs::\n @end menu\n \n @node PowerPC AltiVec Built-in Functions on ISA 2.05\n@@ -26641,6 +26642,27 @@ vector unsigned char);\n vector unsigned char);\n @end smallexample\n \n+@node PowerPC AltiVec Built-in Functions that may be available on future PowerPCs\n+@subsubsection PowerPC Future AltiVec Built-in Functions\n+The built-in functions described in this section may be available on\n+future PowerPC processors. At present, these built-ins exist to allow\n+testing of new instructions. There is no guarantee that these\n+instructions will actually be implemented.\n+\n+Vector Integer Multiply High\n+\n+@smallexample\n+@exdent vector signed short\n+@exdent vec_mulh (vector signed short @var{a}, vector signed short @var{b});\n+@exdent vector unsigned short\n+@exdent vec_mulh (vector unsigned short @var{a}, vector unsigned short @var{b});\n+@end smallexample\n+\n+For each integer value @code{i} from 0 to 7, do the following. The integer\n+value in halfword element @code{i} of a is multiplied by the integer value in\n+halfword element @code{i} of b. The high-order 16 bits of the 32-bit product are\n+placed into halfword element @code{i} of the vector returned.\n+\n @node PowerPC Hardware Transactional Memory Built-in Functions\n @subsection PowerPC Hardware Transactional Memory Built-in Functions\n GCC provides two interfaces for accessing the Hardware Transactional\ndiff --git a/gcc/testsuite/gcc.target/powerpc/vsx_simd-1.c b/gcc/testsuite/gcc.target/powerpc/vsx_simd-1.c\nnew file mode 100644\nindex 00000000000..8bff745aaba\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/vsx_simd-1.c\n@@ -0,0 +1,65 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n+\n+#include <altivec.h>\n+\n+typedef vector signed int v4si_t;\n+typedef vector signed short v8hi_t;\n+\n+__attribute__((noinline))\n+v4si_t int_add (v4si_t x, v4si_t y)\n+{\n+ return vec_add (x, y); /* xvadduwm */\n+}\n+\n+__attribute__((noinline))\n+v4si_t int_sub (v4si_t x, v4si_t y)\n+{\n+ return vec_sub (x, y); /* xvsubuwm */\n+}\n+\n+__attribute__((noinline))\n+v4si_t int_mul (v4si_t x, v4si_t y)\n+{\n+ return vec_mul (x, y); /* xvmuluwm */\n+}\n+\n+__attribute__((noinline))\n+v4si_t int_mulhi (v4si_t x, v4si_t y)\n+{\n+ return vec_mulh (x, y); /* xvmulhsw */\n+}\n+\n+__attribute__((noinline))\n+v8hi_t short_add (v8hi_t x, v8hi_t y)\n+{\n+ return vec_add (x, y); /* xvadduhm */\n+}\n+\n+__attribute__((noinline))\n+v8hi_t short_sub (v8hi_t x, v8hi_t y)\n+{\n+ return vec_sub (x, y); /* xvsubuhm */\n+}\n+\n+__attribute__((noinline))\n+v8hi_t short_mul (v8hi_t x, v8hi_t y)\n+{\n+ return vec_mul (x, y); /* xvmuluhm */\n+}\n+\n+\n+__attribute__((noinline))\n+v8hi_t short_mulhi (v8hi_t x, v8hi_t y)\n+{\n+ return vec_mulh (x, y); /* xvmulhsh */\n+}\n+\n+/* { dg-final { scan-assembler-times \"xvadduwm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvsubuwm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmuluwm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmulhsw\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvadduhm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvsubuhm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmuluhm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmulhsh\" 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/powerpc/vsx_simd-2.c b/gcc/testsuite/gcc.target/powerpc/vsx_simd-2.c\nnew file mode 100644\nindex 00000000000..782efb67473\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/vsx_simd-2.c\n@@ -0,0 +1,65 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n+\n+#include <altivec.h>\n+\n+typedef vector unsigned int v4si_t;\n+typedef vector unsigned short v8hi_t;\n+\n+__attribute__((noinline))\n+v4si_t int_add (v4si_t x, v4si_t y)\n+{\n+ return vec_add (x, y); /* xvadduwm */\n+}\n+\n+__attribute__((noinline))\n+v4si_t int_sub (v4si_t x, v4si_t y)\n+{\n+ return vec_sub (x, y); /* xvsubuwm */\n+}\n+\n+__attribute__((noinline))\n+v4si_t int_mul (v4si_t x, v4si_t y)\n+{\n+ return vec_mul (x, y); /* xvmuluwm */\n+}\n+\n+__attribute__((noinline))\n+v4si_t int_mulhi (v4si_t x, v4si_t y)\n+{\n+ return vec_mulh (x, y); /* xvmulhuw */\n+}\n+\n+__attribute__((noinline))\n+v8hi_t short_add (v8hi_t x, v8hi_t y)\n+{\n+ return vec_add (x, y); /* xvadduhm */\n+}\n+\n+__attribute__((noinline))\n+v8hi_t short_sub (v8hi_t x, v8hi_t y)\n+{\n+ return vec_sub (x, y); /* xvsubuhm */\n+}\n+\n+__attribute__((noinline))\n+v8hi_t short_mul (v8hi_t x, v8hi_t y)\n+{\n+ return vec_mul (x, y); /* xvmuluhm */\n+}\n+\n+\n+__attribute__((noinline))\n+v8hi_t short_mulhi (v8hi_t x, v8hi_t y)\n+{\n+ return vec_mulh (x, y); /* xvmulhuh */\n+}\n+\n+/* { dg-final { scan-assembler-times \"xvadduwm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvsubuwm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmuluwm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmulhuw\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvadduhm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvsubuhm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmuluhm\" 1 } } */\n+/* { dg-final { scan-assembler-times \"xvmulhuh\" 1 } } */\n", "prefixes": [] }